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Just a guess, but did you copy over from CD? Is it possible some files are still read-only? -Clark "chakra" <narashimanc@gmail.com> wrote in message news:1144247452.780354.138410@u72g2000cwu.googlegroups.com... > Hi all, > > I am haveing trouble creating BSPs and Libraries using EDK7.1 for Linux > OS. > > here is my software Platform settings > > OS: linux_mvl31 1.01.a > > memsize 0x8000000 > plb frequency 100000000 > connected peripherals : Rs232uart1, opb sysace, opb intc and ethernet > MAC > > > here is the error which i am getting while running the libgen > > ............... > ........................ > #-------------------------------------- > # Linux BSP DRC...! > #-------------------------------------- > > Running generate for OS'es, Drivers and Libraries ... > #-------------------------------------- > # Linux BSP generate... > #-------------------------------------- > > Running post_generate for OS'es, Drivers and Libraries ... > linux > linux/drivers > linux/drivers/char > linux/drivers/net > linux/drivers/net/xilinx_enet > linux/drivers/net/xilinx_enet/xemac.c > ERROR:MDT - ERROR FROM TCL:- linux_mvl31 () - bash: line 1: > /usr/local/EDK/sw/ThirdParty/bsp/linux_mvl31_v1_01_a/data/Ltypes: > Permission > denied > while executing > "exec bash -c "$ltypes $filename"" > (procedure "xltype_file" line 14) > invoked from within > "xltype_file $entry" > (procedure "xltype_file" line 11) > invoked from within > "xltype_file $entry" > (procedure "xltype_file" line 11) > invoked from within > "xltype_file $entry" > (procedure "xltype_file" line 11) > invoked from within > "xltype_file $entry" > (procedure "xltype_file" line 11) > invoked from within > "xltype_file $linux" > (procedure "::sw_linux_mvl31_v1_01_a::post_generate" line 137) > invoked from within > "::sw_linux_mvl31_v1_01_a::post_generate 171701592" > ERROR:MDT - Error while running "post_generate" for processor > ppc405_0... > make: *** [ppc405_0/lib/libxil.a] Error 2 > Done. > > > If anyone could throw light on where i amgoing wrong it will be helpful > and greatly appreciated. > > with warm regards, > Chakra. >Article: 100226
No, i did'nt. I created a new project. -chakraArticle: 100227
The best way to compress it would be a 3D wavelet like is done in MP4. Buy a core for it. Or if you're company is like mine and cannot compute the idea that time == money, code it yourself. You don't need to encode the output, though. Just Z-order the result, quantize all the data, and RLE the result of that. However, as that is a scatter-gather algorithm, I have trouble recommending that you program it in gates. However, two PPCs might be able to pull it off quickly enough. Get the GPL source code from here: http://www.math.wustl.edu/~victor/awaftts/index.html There are plenty of JPEG or MPEG2 cores around. You could modify one to do 16 bit color fairly easily. Or there again, Q up 8x8pix (or larger) blocks of image data, run the DCT, z-order it, quantize it, and RLE the result. Don't worry about the huffman coding portion of the JPEG.Article: 100228
Paul Leventis wrote: > Referenced links: > (1) > http://www.altera.com/products/devices/stratix2/features/io/st2-source_synch.htm that's missing the trailing 'L': http://www.altera.com/products/devices/stratix2/features/io/st2-source_synch.htmlArticle: 100229
Does Quartus II v.5.1 SOPC component editor support Avalon burstcount signal? If not, why?Article: 100230
100ns is 10 MHz. This isn't correct. What do you see that tells you "100 ns?" ...tool, verbiage. "Milind" <milindt@gmail.com> wrote in message news:1144248035.095781.142510@v46g2000cwv.googlegroups.com... > Hi, > > I found that the delay value of the element FDDRCPE is 100 ns after > running a timing simulation. > > Is it supposed to be so high? > (to confirm it, I also ran a separate simulation of this single element > and with different clk frequencies) > > FDDRCPE is "Dual Data Rate D Flip-Flop with Clock Enable and > Asynchronous > Preset and Clear", used when interfacing DDR with FPGA. It is present > in the simlibs library. > > I'm using ISE 8.1 (and found the same thing in 7.1 too) > > If it is supposed to be that high, what may be the reason behind it? > > See a related post here: > > http://groups.google.co.in/group/comp.arch.fpga/browse_thread/thread/790b589a01726678/66426daa7240b82e?lnk=st&q=fddrcpe&rnum=3&hl=en#66426daa7240b82e > > Thanks and Regards, > Milind >Article: 100231
You could just do 5/6/5 color - 16 bit - rather than 24 bit color. Do you intend to use a compressor/decompressor on each end for real-time display? Is memory your problem or is it strictly bandwidth? Dual-DVI links are also available to supply double the bandwitdh. <ALuPin@web.de> wrote in message news:1144246476.647470.60190@u72g2000cwu.googlegroups.com... Hi, I want to know what approach you would recommend to compress an incoming DVI data stream (data width 24 bit, pixel clock 25-165MHz) from 24 bit colour depth to 16 bit colour depth. The DVI data are stored as 64 bit chunks into DDR memory at 133MHz. For higher resolutions (fPIX > fDDR) I would like to reduce the colour depth so that performance (frame rate) at the read side of the DDR memory (image display) is not downgraded in such a way that moved images judder. Are there algorithms for parallel data processing (24bit/16bit) you can recommend ? Any hints are appreciated. Rgds AndréArticle: 100232
Stephen, We used to contract with another university to handle university support, but that went away. In the interim, we must still support that important group, and the webcase method was the only means that could be used without affecting the commercial customers (who are also important!). You will not get the same response time as a commecial customer, but I am assured your case will be handled. Did you also read: http://www.xilinx.com/xlnx/xil_ans_display.jsp?iCountryID=1&iLanguageID=1&getPagePath=19893&BV_SessionID=@@@@1734967960.1144251887@@@@&BV_EngineID=cccdaddhhemhelmcefeceihdffhdfjf.0 (answer 19893) http://toolbox.xilinx.com/docsan/xilinx7/books/data/docs/v4ldl/v4ldl0044_36.html http://toolbox.xilinx.com/docsan/xilinx8/books/docs/v4ldl/v4ldl.pdf page 135 We use ICAP a lot for verification and characterization. There are also cores that use it to get around silicon bugs (by adjusting bits to optimize performance while operating). Make sure you are not trying to use ICAP when something else is already trying to use it, too. Austin Stephen Craven wrote: > I don't know if we do or not, but I'll check. > > In the past I had been rejected from WebCase support as a student, but > I'll pass along that support is now available. > > Thank you, > Stephen >Article: 100233
hi guys After i synthesis the vhdl codes, my design consist of 609 combination modules, im using the actel 1280XL 84 pin FPGA. it only has like 608 comb modules + 624 seq modules Therefore i think my design will not fit in the FPGA. Im really new into FPGAs. Since im not using any sequential modules do you think I will be able to fit the design in the above mentioned FPGA using the some of the seq modules? The overall report says design has 609/1232 modules (50%) of the FPGA !! But it has exceeded the amount of comb modules!! I haven't got a clue whether I can make it using some of the seq module!! PLEASE help me out!! Thanks a lot PraviendreArticle: 100234
In article <1144246476.647470.60190@u72g2000cwu.googlegroups.com>, ALuPin@web.de <ALuPin@web.de> wrote: >Hi, > >I want to know what approach you would recommend to >compress an incoming DVI data stream (data width 24 bit, pixel clock >25-165MHz) >from 24 bit colour depth to 16 bit colour depth. Throwing away three bits of R and B and two of G is the traditional one. If you've got enough time per pixel, a way of improving the quality would be to remember the error you've made at one pixel and apply it to the next before correcting that - this produces dithering patterns instead of areas of uniformly the wrong colour. But that's not particularly parallelisable. >The DVI data are stored as 64 bit chunks into DDR memory at 133MHz. That seems a rather odd size if it's coming in as 24-bit colour depth, but I suppose it's the accepted bit width for DVI; would it work to use 48-bit chunks instead to avoid having shifting logic to deal with blocks of 2+2/3 pixels? TomArticle: 100235
Hi Gabor, When I click on link to download I get following message: "The file you have attempted to retrieve is not available at this time. We apologize for the inconvenience." The same thing for every module and for licensing option. I never reach to agree "to license terms and export control". I have tried to investigate this recently, and Latttice tech. support concluded that the problem is in my ISP. But ISP people says that they get the same behavior when they try to download from their central. They claim that there is something wrong with website ! Anybody tried to download it for Europe? Thanks, Best regards, Maki.Article: 100236
Hi all, I am trying to interface a ADC with FPGA through SPI interface. FPGA will have SPI slave implemmented. Once i receive the data from ADC i am required to have some kind of data validity and freshness check. One way to check validity is to have data parity embedded with data but ARE THERE ANY OTHER OPTIONS because parity is prone to bit(s) error. Also i am required to have some logic for freshness. Please any suggestions or directions will be apperitiated. Thanks.Article: 100237
Hi, I've one basic doubt. If suppose I use opensource processor like leon/openrisc am I reducing my BOM as processor is concerned, compared to powerPC/microblaze/NIOS. If suppose I make huge quantities of them in ASIC (with my own logic added) may I be able to comedown below the cost of FPGA with some hardcored processor + my defined logic. PrakashArticle: 100238
Hi, While porting hdl codes in xilinx, I synthesized using synplify with my constraints.Then I place& routed in xilinx-ISE the edif file (output of synplify). Now there are some timing errors coming in ise. Now I want to view the P&R 'ed file in synplify, which file I 've to load it in synplify. Is it possible to use synplify as the synthesis tool in ise (wher to set). One more doubt is in synplify I could see its mapping also. Again when I try to P&R the xilinx also maps. In the error in ISE it says try map -timing option. Is it required even if we do auto constrain freq in synthesis using synplify. Please clarify PrakashArticle: 100239
On Wed, 05 Apr 2006 03:28:46 GMT, mk <kal*@dspia.*comdelete> wrote: >On Fri, 31 Mar 2006 21:57:49 +0100, "Slurp" <slip@slop.slap> wrote: >> >>Here is an example I dropped together inside 3 mins, ready to synthesise. >>Only needs the pins and device defining before I can drop it straight into a >>part. >> >>http://www.wheelnut.plus.com/Block1_bdf.pdf > >Here is my verilog take on it: > >module block1_bdf(sysck, a, b, c, d, e, result); >input sysck; >input [17:0] a, b, c, d, e; >output [37:0] result; > >reg [17:0] dataa, datab, datac, datad, datae; > >always @(posedge sysck) >begin > dataa <= a; > datab <= b; > datac <= c; > datad <= d; > datae <= e; >end > >wire [37:0] data3 = dataa * datab; >wire [37:0] data2 = datab * datac; >wire [37:0] data1 = datac * datad; >wire [37:0] data0 = datad * datae; > >reg [37:0] data; >always (posedge sysck) > data <= data0 + data1 + data2 + data3; > > >reg [37:0] result; >always (posedge sysck) > result <= data / 20'd109456; > >endmodule > >I certainly have not been working on it since you posted your pdf ;-) And if I had the Verilog, the first thing I'd do is grab a piece of paper and sketch it out to understand what it does. Some people think verbally, some visually. JohnArticle: 100240
Hi, You'll need to deserialize (via a SERDES) since you can't operate the FPGA core at 1 Ghz. You still need only provide the device your 1 clock and 16 data lines, and the SERDES does the rest. You can also use dynamic phase alignmnet circuitry (DPA) if you want, but you don't have to. In its simplest form, all the SERDES block does in this case is deserialize the data stream by between a factor of 2 and 10 to slow it down to a rate you can handle in the core. Regards, PaulArticle: 100241
Jim Granville wrote: > Steve Knapp (Xilinx Spartan-3 Generation FPGAs) wrote: [ ... snip ...] > >Spartan-3E FPGAs behave differently. > > Whilst we are on this subject, to this detail, > can you give some info on how does Spartan 3E differ, and why ? > > -jg The only difference is in the DLL phase shifter feature included with the DCM. Most everything else is identical between Spartan-3 and Spartan-3E DCMs. There's a summary of the differences in the following Answer Record, but I'll follow up here with the abbreviated version. http://www.xilinx.com/xlnx/xil_ans_display.jsp?getPagePath=23004 In FIXED phase shift mode, the difference depends on which version ISE that you are using, as described in the data sheet and the Answer Record. Physically, the Spartan-3 DLL performs a fixed phase shift by as much as a full clock cycle forward or backward. The Spartan-3E DLL performs a fixed phase shift by as much as _half_ a clock cycle forward or backward. For nearly all applications, the Spartan-3E half-clock shift provides the same flexibility as the full clock shift, but with significantly less silicon. In VARIABLE phase shift mode, the difference is that the Spartan-3 DLL performs a variable phase shift in fractions of a clock period, 1/256th of a full circle. Think degrees, angles, radians, using your favorite angular unit. Extra logic within the Spartan-3 DLL calculates the delay line change. The Spartan-3E DLL also performs a variable phase shift using a delay line. However, in Spartan-3E, you have raw control over the delay. The shift is always in time, not in some angular unit. --------------------------------- Steven K. Knapp Applications Manager, Xilinx Inc. General Products Division Spartan-3/-3E FPGAs http://www.xilinx.com/spartan3e --------------------------------- The Spartan(tm)-3 Generation: The World's Lowest-Cost FPGAs.Article: 100242
Hello folks, I may be starting my first Altera design in a few years but I was disappointed to find that the Cyclone-II LVDS drivers aren't true differential drives: an external resistor network is needed to produce proper LVDS levels like in the "old days." Does anyone here have experience with the LVDS drivers? I imagine I'll end up with 0603 resistors rather than a Bourns network, for instance. What have others used? Was there any problem driving these 2.5V pins at LVDS rates in power supply noise or EMI? I don't have a huge count of output signals so it's reasonable from a space standpoint. The data sheet declares 640 Mbps LVDS transmit rates. Also for receive... my glances through the Cyclone-II data sheet seem to indicate off-chip receive terminations are needed but I saw a post from Antti that said there were on-chip terminations. Did I miss something? Are on-chip terminations available for the Cyclone-II LVDS inputs? The Spartan3E I/O solution is quite possibly better but pricing might push me back to brand A for this next design. Any thoughts? Thanks, John HandworkArticle: 100243
All- If I have an array of registers like: reg [3:0] reg_array [3:0]; how to initialize elements with different values? I tried various combinations such as: // synthesis attribute INIT of reg_array[0] is 4'h1; // synthesis attribute INIT of reg_array[1] is 4'h9; but XST continues to say something like: Cannot find <reg_array[0]> in module <test_mod>, property <INIT> with Value <4'h1> is ignored. I have been searching Xilinx site and group posts for array initialization examples but no luck yet. Thank you. -JeffArticle: 100244
The Spartan-3E I/O do not require external resistors for LVDS or RSDS outputs, which simplifies board routing, number of vias, reliability, etc. For Spartan-3E LVDS or RSDS inputs, you can either use a 100-ohm external termination resistor or the internal DIFF_TERM resistor built into each pair, which is nominally 120 ohms. Just FYI, we just recently released the following application note and reference design on Spartan-3E for LVDS display applications. It is even simpler on 4:1, 8:1, etc. designs. XAPP485: 1:7 Deserialization in Spartan-3E FPGAs at Speeds Up to 666 Mbps http://www.xilinx.com/xlnx/xweb/xil_publications_display.jsp?category=-1209837&show=xapp485 --------------------------------- Steven K. Knapp Applications Manager, Xilinx Inc. General Products Division Spartan-3/-3E FPGAs http://www.xilinx.com/spartan3e --------------------------------- The Spartan(tm)-3 Generation: The World's Lowest-Cost FPGAs.Article: 100245
Dear All, I am a little confused with regards to the clocking arrangement associated with the Xilinx Rocket IO MGT. I want to use the MGT in Half Rate Mode with no 8B/10B encoding / decoding with a byte wide interface (actually 10-bit wide due to not using the 8B/10B). I have the following clocks (as per page 54 of the Rocket IO User Guide [Vertex-II Pro]): REFCLK > tied to the pre-DCM input clock (clkin) RXUSRCLK & TXUSRCLK > tied to the DCM output clock (div2) RXUSRCLK2 & TXUSRCLK2 > tied to the DCM output clock (clk0) My question is which clock do I use to clock my data TO the MGT and conversely FROM the MGT? The user guide says "Each edge of the slower clock must align with the falling edge of the faster clock", as a result it suggests that TXUSRCLK2 & RXUSRCLK2 are inverted so that clk0 can be used instead of clk180. "Since clk0 is needed for feedback, it can be used instead of clk180 to clock USRCLK or USRCLK2 of the transceiver with the use of the transceiver's local inverter, saving a global buffer (BUFG)." My second question is, if the answer to question 1 is TXUSRCLK2 & RXUSRCLK2 as suggested in the User Guide, is it permissible to invert the RXUSRCLK & TXUSRCLK's instead of inverting the TXUSRCLK2 & RXUSRCLK2 to assist with clock alignment in other areas in my design? Many Thanks, SimonArticle: 100246
I read a little bit on this topic and found points which are as follow: 1. Sender should be repsonsible to have a validity bit set with each frame to show the frame has valid data. 2. Sender should compute an incremented CRC for each data frame and attach it with sending data for freshness. 3. Receiver should extract the CRC and see if the CRC has incremented than data is fresh otherwise data is not freshed. 4. Receiver should discard any incomming data if the validity criteria sent by the sender fails to satisfies. Now any more suggestions for checking data validity and freshnessArticle: 100247
XST may support the initial block: initial begin reg_array[0] = 4'h1; reg_array[1] = 4'h9; ... end They *do* support initial assignment to simple registers: reg [3:0] RegArrA = 4'h1; reg [3:0] RegArrB = 4'h9; "Jeff Brower" <jbrower@signalogic.com> wrote in message news:1144259900.086810.25810@g10g2000cwb.googlegroups.com... > All- > > If I have an array of registers like: > > reg [3:0] reg_array [3:0]; > > how to initialize elements with different values? > > I tried various combinations such as: > > // synthesis attribute INIT of reg_array[0] is 4'h1; > // synthesis attribute INIT of reg_array[1] is 4'h9; > > but XST continues to say something like: > > Cannot find <reg_array[0]> in module <test_mod>, property <INIT> with > Value <4'h1> is ignored. > > I have been searching Xilinx site and group posts for array > initialization examples but no luck yet. > > Thank you. > > -Jeff >Article: 100248
Hi all, I made a small fifo module to do some testing. code: http://vis.uky.edu/~sub/Fifotest_Code.doc I first did post implementation simulation using modelsim and the output was as expected. simulation output: http://vis.uky.edu/~sub/Modelsim_Waveform.bmp Then I probed into chip with chipscope analyzer. The values were different. I am not sure what my mistake is. The trigger port was data_in_reg[7:0]. Am I looking at some wrong values instead? Chipscope Analyzer Waveform: http://vis.uky.edu/~sub/CS_Analyzer_Waveform.bmp Thanks for any help. - Subhasri.KArticle: 100249
The Spartan3E LVDS approach is what I've grown to "expect:" a fully integrated solution. The Spartan3E should give great results for those signals in spite of the capacitance issues that nag at other engineers. So now I wonder about the competitor's suboptimal solution. "Steve Knapp (Xilinx Spartan-3 Generation FPGAs)" <steve.knapp@xilinx.com> wrote in message news:1144260012.858146.36290@g10g2000cwb.googlegroups.com... > The Spartan-3E I/O do not require external resistors for LVDS or RSDS > outputs, which simplifies board routing, number of vias, reliability, > etc. > > For Spartan-3E LVDS or RSDS inputs, you can either use a 100-ohm > external termination resistor or the internal DIFF_TERM resistor built > into each pair, which is nominally 120 ohms. > > Just FYI, we just recently released the following application note and > reference design on Spartan-3E for LVDS display applications. It is > even simpler on 4:1, 8:1, etc. designs. > > XAPP485: 1:7 Deserialization in Spartan-3E FPGAs at Speeds Up to 666 > Mbps > http://www.xilinx.com/xlnx/xweb/xil_publications_display.jsp?category=-1209837&show=xapp485 > > --------------------------------- > Steven K. Knapp > Applications Manager, Xilinx Inc. > General Products Division > Spartan-3/-3E FPGAs > http://www.xilinx.com/spartan3e > --------------------------------- > The Spartan(tm)-3 Generation: The World's Lowest-Cost FPGAs. >
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