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On Sep 17, 11:14 am, Shannon <sgo...@sbcglobal.net> wrote: > On Sep 17, 11:03 am, Weng Tianxiang <wtx...@gmail.com> wrote: > > > > > > > Hi, > > OK, a state machine is defined by standard one process or two > > processes in VHDL. > > > There is no short cut. > > > It can be implemented in anywhere in a design and where the state > > machine is located is decided by compilers and beyond the interest of > > this topics. > > > I have to expand the guess to include Verilog group people, because > > VHDL people may have no chance to do the designs. > > > I may know the answer. The final result may surprise everyone who > > gives a guess. > > > Thank you. > > > Weng > > Ok Weng, > > Since you obviously don't understand the questions the people who have > responded... > > let's define a state machine as a process or processes that have a > classic "state variable". Sigh... > Furthermore since you rejected the concept that our guess should not > be based on what is "possible" but instead on what has actually been > done... > > I will answer you question that ***I*** have created the design that > has the most classic state machines in it. And since you know the > answer you will tell ***me** how many I had to use. Hint: It's more > than 27 and I know you ***will*** be surprised by the answer! > > Shannon- Hide quoted text - > > - Show quoted text - Hi Shannon, "let's define a state machine as a process or processes that have a classic "state variable". Sigh... " I don't write code for them, but you can expect how people in VHDL define a state machine: by using type (...) as I like to do, but not necessarily. I cannot guess the largest number of state machines you have written for a design, but I know clearly the number of state machines you may have written in a design is less than 100k. Any question? WengArticle: 124276
Hi all, I'm a newbie in this area. I'm working on a custom board that has Virtex-4 on it and doing my development using XPS. What I'm trying to do is moving some data that's coming into my peripheral (attached to OPB bus) to a certain location on the DDR (attached on the PLB bus). Is there any way to check if that location on the DDR is not being used / still free? (I don't want to overwrite anything on DDR) Can I also copy the data directly to some address located on the DDR? Can anyone suggest any articles that might help me in understanding the data transfer between IPs or any example firmware of how to do this? Thanks SArticle: 124277
On 14 Sep., 21:00, "Brad Smallridge" <bradsmallri...@dslextreme.com> wrote: > That's a nice walkthrough but doesn't address the issue > of incorporating hardware designs. > > > > >http://www.itee.uq.edu.au/~wu/downloads/uClinux_ready_Microblaze_desi...- Zitierten Text ausblenden - > > - Zitierten Text anzeigen - I have written a MicroBlaze tutorial. You find it here: http://www.fpgafromscratch.com SvenArticle: 124278
"Amontec, Larry" <laurent.gauch@ANTI-SPAMamontec.com> wrote in message news:46eeb60f$1_6@news.bluewin.ch... > Hi > > We are searching a small CPLD gate count like a coolrunner 128. > > - Two IO banks 1.4V to 3.3V with 5V tolerant > - VCC should be 3.3V or 1.8V > > The 5V tolerant is important ! > > Volume : 5000 - 10000 pces > > Any CPLDs ? > > Regards, > Laurent For my own senseless curiosity, would you mind mentioning the application? I'm wondering what new designs require the way-over-the-hill 5V standard. The continuing requirements for 5V interfaces baffle me.Article: 124279
Hi Glen, There is a theory behind to resolve the problem. A state machine can be defined in such a scentific way: 1. All states in a state machine have their own names; 2. All states in a state machine are mutually exclusive; 3. Only one state is active in any cycle; 4. The number of states in a state machine must be 2 or more; 5. There must have either asynchronous or a synchronous reset signal for the state machine and after their assertion, the state machine must be in initial state. I guess there are less than 27 engineers in the world who have the experiences to do the designs. If your experiences are fully in FPGA and VHDL worlds, you may never have a chance to get a right guess with any possible wildest imagination, Any more question? WengArticle: 124280
Weng Tianxiang wrote: > Hi, > I would like to pose an interesting guess topics for experienced > engineers: > What is the largest number of state machines in a current chip design: > 1k, 10k or ... > > I have finished 8 projects and only counted 27 state machines in one > of my biggest designs. > > I may know the answer. The final result may surprise everyone who > gives a guess. > > Weng So are you talking about a Silicon Ceiling, or a Software Ceiling ? -jgArticle: 124281
On Sep 17, 11:39 am, Weng Tianxiang <wtx...@gmail.com> wrote: >I know clearly the number of state machines you may > have written in a design is less than 100k. Any question? Ok, so we have your mysterious answer then. The most state machines is 100k. Ok.. ho hum. So? Is there a point to this drivel? ShannonArticle: 124282
On Sep 17, 10:14 am, "Amontec, Larry" <laurent.ga...@ANTI- SPAMamontec.com> wrote: > Hi > > We are searching a small CPLD gate count like a coolrunner 128. > > - Two IO banks 1.4V to 3.3V with 5V tolerant > - VCC should be 3.3V or 1.8V > > The 5V tolerant is important ! > > Volume : 5000 - 10000 pces > > Any CPLDs ? > > Regards, > Laurent My current favorite CPLD is Alter'a MAX-II. Vcc=1.8v, and from the data sheet: "A MAX II device can drive a 5.0-V TTL device by connecting the VCCIO pins of the MAX II device to 3.3 V. This is possible because the output high voltage (VOH) of a 3.3-V interface meets the minimum high- level voltage of 2.4 V of a 5.0-V TTL device" G.Article: 124283
Weng Tianxiang wrote: > I would like to pose an interesting guess topics for experienced > engineers: > What is the largest number of state machines in a current chip design: > 1k, 10k or ... This is not an easy question. I could say that every flip-flop is a state machine, in which case the number is very large. I could say that the entire system is a state machine, in which case the answer is one. We partition systems when we design them, and design separate state machines. Others may look at the system differently, and find a different count. -- glenArticle: 124284
Weng Tianxiang wrote: > [snip] > > Any more question? What are you smoking? Care to share? -- [100~Plax]sb16i0A2172656B63616820636420726568746F6E61207473754A[dZ1!=b]salaxArticle: 124285
Maybe it's a phase issue between your 200 and 100 MHz clocks, and you come in on different phases during your reset. What's your dcm/clocking scheme? "Sylvain Munaut wrote in message > I'm working on a custom DDR2 controller on Virtex 5 and I have a very > weird behavior that I can't explain. > I'm doing my tests on a SO-DIMM of which I only use 8 bits and running > it at 200 MHz. My controller uses > the ISERDES / OSERDES so that it only runs at 100 MHz and expose a 32 > bits data interface to the user. >Article: 124286
John_H <newsgroup@johnhandwork.com> wrote: ... > For my own senseless curiosity, would you mind mentioning the application? > I'm wondering what new designs require the way-over-the-hill 5V standard. > The continuing requirements for 5V interfaces baffle me. For example to interface the Parallelport to a 1.8/2.5/3.3V Jtag Chain in a Byteblaster/Parallel Cable III way... And configurable hysteresis like in the Coolrunner II comes in handy... -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 124287
On Sep 17, 4:08 pm, ghel...@lycos.com wrote: > On Sep 17, 10:14 am, "Amontec, Larry" <laurent.ga...@ANTI- > > > > SPAMamontec.com> wrote: > > Hi > > > We are searching a small CPLD gate count like a coolrunner 128. > > > - Two IO banks 1.4V to 3.3V with 5V tolerant > > - VCC should be 3.3V or 1.8V > > > The 5V tolerant is important ! > > > Volume : 5000 - 10000 pces > > > Any CPLDs ? > > > Regards, > > Laurent > > My current favorite CPLD is Alter'a MAX-II. Vcc=1.8v, and from the > data sheet: > > "A MAX II device can drive a 5.0-V TTL device by connecting the VCCIO > pins of the MAX II device to 3.3 V. This is possible because the > output high voltage (VOH) of a 3.3-V interface meets the minimum high- > level voltage of 2.4 V of a 5.0-V TTL device" > > G. It's generally the 5V inputs where you run into trouble. 5V TTL usually drives up to 3.5 - 4 Volts under light load conditions. 5V CMOS pretty much drives to the 5V rail. I like the Lattice MachXO "C" parts with the built-in core voltage regulator to allow 3.3V only operation even though the core runs at 1.2V Input voltage tolerance is spec'd at 4.25V, not quite enough for 5V CMOS, but perhaps enough to avoid resistors on 5V TTL. Internally MachXO is really an FPGA with fast self configuration from its own flash. The largest MachXO parts also contain some block RAM, which comes in handy. You didn't mention speed requirements, so you need to be careful if you want very fast pin-to-pin throughput, since this is not a traditional sum-of-products CPLD.Article: 124288
Jim Granville wrote: (snip) > It's not clear what you mean by 'vanilla CMOS gates and latches' ? > CPLDs were quite different from FPGAs in structure, and Philips > were the leaders in 'true CMOS' CPLDs, which now sees > Atmel/Lattice/Xilinx(via Philips) offering CMOS CPLDs. > FPGAs have always needed MUX elements (your pass-transistor) > as they have always had a routing element. You can make a MUX out of pass transistors, or NAND gates. Pass transistors have the advantage of being bidirectional. Advantage in early FPGAs (for routing), but as I understand it maybe not anymore. It would likely take a lot more transistors in NAND gates. -- glenArticle: 124289
"Uwe Bonnes" <bon@hertz.ikp.physik.tu-darmstadt.de> wrote in message news:fcmptp$71e$1@lnx107.hrz.tu-darmstadt.de... > John_H <newsgroup@johnhandwork.com> wrote: > ... >> For my own senseless curiosity, would you mind mentioning the >> application? >> I'm wondering what new designs require the way-over-the-hill 5V standard. >> The continuing requirements for 5V interfaces baffle me. > > For example to interface the Parallelport to a 1.8/2.5/3.3V Jtag Chain in > a > Byteblaster/Parallel Cable III way... <snip> The parallel port is the only thing that initially came to mind for me. I understand there are still those who want that connection, but is this all of the 5V applications anymore or is the original poster looking for something else?Article: 124290
On Sep 16, 4:22 pm, Uncle Noah <nk...@skiathos.physics.auth.gr> wrote:
> The URL:http://electronics.physics.auth.gr/people/nkavv/yardstick/
>
> This will link directly for all.
And an example for a custom instruction AUTO-GENERATED for an edge
detection filter.
Ckeck out, the VCG, Graphviz and C outputs from the corresponding
backends.
VCG output:
graph: { title: "main_9"
x: 30
y: 30
height: 380
width: 560
xspace: 20
yspace: 30
display_edge_labels: yes
layoutalgorithm: minbackward
port_sharing: no
node.borderwidth: 3
node.color: white
node.textcolor: black
node.bordercolor: black
edge.color: black
node: { title:"0" shape: ellipse label:" ior" color:yellow }
node: { title:"1" shape: ellipse label:" sl" color:yellow }
node: { title:"2" shape: ellipse label:" abs" color:yellow }
node: { title:"3" shape: ellipse label:" sub" color:yellow }
node: { title:"4" shape: ellipse label:" sl" color:yellow }
node: { title:"5" shape: ellipse label:" abs" color:yellow }
node: { title:"6" shape: ellipse label:" sub" color:yellow }
node: { title:"7" shape: ellipse label:" ldc" color:yellow }
node: { title:"8" shape: rhomb label:" 1" color:magenta }
edge: {sourcename:"8" targetname:"7"}
node: { title:"9" shape: triangle label:" vr234.s32" color:cyan }
edge: {sourcename:"0" targetname:"9"}
node: { title:"10" shape: triangle label:" vr235.s32" color:cyan }
edge: {sourcename:"7" targetname:"10"}
node: { title:"11" shape: box label:" vr60.s32" color:green }
edge: {sourcename:"11" targetname:"1"}
node: { title:"12" shape: box label:" vr207.s32" color:green }
edge: {sourcename:"12" targetname:"3"}
node: { title:"13" shape: box label:" vr210.s32" color:green }
edge: {sourcename:"13" targetname:"3"}
edge: {sourcename:"11" targetname:"4"}
edge: {sourcename:"12" targetname:"6"}
node: { title:"14" shape: box label:" vr220.s32" color:green }
edge: {sourcename:"14" targetname:"6"}
edge: {sourcename:"3" targetname:"2" label:"vr228.s32" }
edge: {sourcename:"2" targetname:"1" label:"vr229.s32" }
edge: {sourcename:"1" targetname:"0" label:"vr230.s32" }
edge: {sourcename:"6" targetname:"5" label:"vr231.s32" }
edge: {sourcename:"5" targetname:"4" label:"vr232.s32" }
edge: {sourcename:"4" targetname:"0" label:"vr233.s32" }
}
Graphviz output:
digraph main_9 {
node [fontname=Courier,fontsize=14,style=filled];
0 [shape=ellipse,label="ior",fillcolor=yellow]
1 [shape=ellipse,label="sl",fillcolor=yellow]
2 [shape=ellipse,label="abs",fillcolor=yellow]
3 [shape=ellipse,label="sub",fillcolor=yellow]
4 [shape=ellipse,label="sl",fillcolor=yellow]
5 [shape=ellipse,label="abs",fillcolor=yellow]
6 [shape=ellipse,label="sub",fillcolor=yellow]
7 [shape=ellipse,label="ldc",fillcolor=yellow]
8 [shape=diamond,label="1",fillcolor=magenta]
8 -> 7;
9 [shape=triangle,label="vr234.s32",fillcolor=cyan]
0 -> 9;
10 [shape=triangle,label="vr235.s32",fillcolor=cyan]
7 -> 10;
11 [shape=invtriangle,label="vr60.s32",fillcolor=green]
11 -> 1;
12 [shape=invtriangle,label="vr207.s32",fillcolor=green]
12 -> 3;
13 [shape=invtriangle,label="vr210.s32",fillcolor=green]
13 -> 3;
11 -> 4;
12 -> 6;
14 [shape=invtriangle,label="vr220.s32",fillcolor=green]
14 -> 6;
3 -> 2 [label="vr228.s32"];
2 -> 1 [label="vr229.s32"];
1 -> 0 [label="vr230.s32"];
6 -> 5 [label="vr231.s32"];
5 -> 4 [label="vr232.s32"];
4 -> 0 [label="vr233.s32"];
}
C output:
void ci_9(
int *d0
,int *d1
,int s0
,int s1
,int s2
,int s3
)
{
int vr228_s32;
int vr229_s32;
int vr230_s32;
int vr231_s32;
int vr232_s32;
int vr233_s32;
*d1 = 1;
vr231_s32 = s1-s3;
vr232_s32 = ((vr231_s32 < 0) ? -vr231_s32 : vr231_s32);
vr233_s32 = s0<vr232_s32;
vr228_s32 = s1-s2;
vr229_s32 = ((vr228_s32 < 0) ? -vr228_s32 : vr228_s32);
vr230_s32 = s0<vr229_s32;
*d0 = vr230_s32|vr233_s32;
#pragma cycles_est_total = 2
}
Article: 124291Hi Let me ask two questions --: According to Virtex-4 configuaration guide (http://www.xilinx.com/bvdocs/userguides/ug071.pdf), ICAP interface is either 8-bit or 32-bit, with up to 60MHz CCLK. Most of diagrams and explanations are based on 8-bit interface. I also saw one document, in which latest VIrtex-4 ICAP provides 32-bit interface with 100 MHz. I wonder if 32-bit interface operates, in a same way as 8-bit interface. Is 32-bit interface 4 times faster than 8-bit interface? In 100 MHz mode, are there any handshaking during the bitstream loading? (There was no handshaking during bitream loading, in Virtex-II Pro, if I am correct)Article: 124292
Hi - Can someone point me to where FVAL, LVAL, DVAL relationship requirements are? I look at the i/f spec on alacron.com, but it doesn't list any. I'm looking for something like After FVAL goes valid, LVAL should go valid within one line time, after LVAL goes valid, DVAL should go valid withone one pixel time, etc. Thanks.Article: 124293
On Sep 17, 10:39 am, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote: > vasile wrote: > > Hi to everybody, > > > I'ts not very clear from the Virtex 5 User guide, Clock resources > > chapter if it's possible to route (on different GCLK inputs) single > > ended and differential CLKs. Then at configuration time use either the > > single ended clock (routed at the P side of the differential input > > pair) or differential clock (say LVDS clock). > > > User manual say: "The 20 global clock pins on Virtex-5 devices can be > > connected to 20 differential or 20 singleended board clocks" > > page20-21 and "Each clock input can be either single-ended or > > differential" page 20. That means only either single ended either > > differential clock is allowed? > > > The second question is about differential clocks routed to XY GTP > > transcievers. Can those be used safely as GCLK or RCLK for the GTP > > opposite banks (banks far away from the GTPs) or an outer clock must > > be routed on PCB? > > You are misinterpreting the documentation. A clock circuit is made > up of multiple resources including an package input pin (IBUF or IBUFDS), > an optional DCM or PLL and a global clock tree (BUFG). > > The paragraph that you quoted was discussing that the package input pin > could be either single ended (LVCMOS, SSTL, HSTL, etc) or differential > (LVDS). These package pins would be connected to a physical on board > clock device that outputs a specific signaling standard. A > > The MGTREFCLK input pins are intended only for use with the RocketIO > transceivers. These can be driven into the array, but it must be done > through an instantiated RocketIO and the only allowed connection from > here is to a BUFG. It is not recommended to use these pins for anything > other than RocketIO based designs. In particular you would not want to > use these pins for system synchronous designs as the timing is not the > same as defined clock input pins. > OK, thank you, this is answering just to a part of my question. Can I route both differential and single ended clocks to the same GCLK dedicated bank (like bank3 in LX330T ) and use both of them (one is LVDS as you say and the other is single ended 2.5V clock) ? Where can I found this info in the datasheet please, so I will not misinterpreting anymore ? thnak you, VasileArticle: 124294
On Sep 17, 10:14 am, "Amontec, Larry" <laurent.ga...@ANTI- SPAMamontec.com> wrote: > Hi > > We are searching a small CPLD gate count like a coolrunner 128. > > - Two IO banks 1.4V to 3.3V with 5V tolerant > - VCC should be 3.3V or 1.8V If do you think you will be able to run a CPLD IO at 1.8V at high speed and keep the 5V tolerant option (only for the inputs of course) using series resistors I think you have limited chance. Compute the delay induced by the parasitical capacitance of the input and the minimum resistor value and see, maybe it's ok. AFIK there is no other safe 5V tolerant device than those using 3.3V logic levels. VasileArticle: 124295
On Sep 17, 10:58 pm, "Brad Smallridge" <bradsmallri...@dslextreme.com>
wrote:
> Maybe it's a phase issue between your 200 and 100 MHz clocks,
> and you come in on different phases during your reset.
> What's your dcm/clocking scheme?
All the clocks comes from a V5 PLL.
I found the issue yesterday.
I plugged in a scope and watched DQS and DQS_n
and it turned out that when the design was failing, DQS and DQS_n were
somehow not in phase, one of them being 1 clock cycle late ... Which
is _very_ weird given that in my design I had :
OSERDES -> IOBUFDS
with the iobuf ds being a differential output buffer connected to dqs
and dqs_n with the same OSERDES as source ...
I replaced that with two independant output buffer OBUFT and two
OSERDES (one of them having inverted data input), and now it works
fine ...
Sylvain
Article: 124296Hi, im implementing a 16bit bus along the lines of AMBA APB for some of my peripherals like IDE ATA controller, LCD dsplay controller, ftdi usb interface etc. But i found that xilinx spartan devices have no internal tristate buffers. I have a dozen or more peripherals to connect. Any idea of how i can implement this? thanks, aravindArticle: 124297
>Hi, im implementing a 16bit bus along the lines of AMBA APB for some >of my peripherals like IDE ATA controller, LCD dsplay controller, ftdi >usb interface etc. But i found that xilinx spartan devices have no >internal tristate buffers. >I have a dozen or more peripherals to connect. Any idea of how i can >implement this? > >thanks, >aravind Use multiplexers. Internal tristate buses are deprecated in ASIC designs, and - most wisely, IMHO - not possible in FPGA designs.Article: 124298
John_H <newsgroup@johnhandwork.com> wrote: > "Uwe Bonnes" <bon@hertz.ikp.physik.tu-darmstadt.de> wrote in message > news:fcmptp$71e$1@lnx107.hrz.tu-darmstadt.de... > > John_H <newsgroup@johnhandwork.com> wrote: > > ... > >> For my own senseless curiosity, would you mind mentioning the > >> application? > >> I'm wondering what new designs require the way-over-the-hill 5V standard. > >> The continuing requirements for 5V interfaces baffle me. > > > > For example to interface the Parallelport to a 1.8/2.5/3.3V Jtag Chain in > > a > > Byteblaster/Parallel Cable III way... > <snip> > The parallel port is the only thing that initially came to mind for me. I > understand there are still those who want that connection, but is this all > of the 5V applications anymore or is the original poster looking for > something else? If you use the AVR line of microcontrollers, most parts only guarantee to run at full speed at 5 Volt. Furthermore AVR Pins are not 5 Volt tolerant when running with 3.3 Volt. Interfacing different voltages and partial power down is always a big concern in my designs. A 1.8/.../5 Volt CPLD would come handy... -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 124299
RCIngham wrote: > >Hi, im implementing a 16bit bus along the lines of AMBA APB for some > >of my peripherals like IDE ATA controller, LCD dsplay controller, ftdi > >usb interface etc. But i found that xilinx spartan devices have no > >internal tristate buffers. > >I have a dozen or more peripherals to connect. Any idea of how i can > >implement this? > > > >thanks, > >aravind > > Use multiplexers. Internal tristate buses are deprecated in ASIC designs, > and - most wisely, IMHO - not possible in FPGA designs. Possible - Yes. But big and slow therefore depreciated. You can code tristate buses and most tolls will emulate them with multiplexers. Regards, Maki From laurent.pinchart@skynet.be Tue Sep 18 01:55:06 2007 Path: newsdbm02.news.prodigy.net!newsdst02.news.prodigy.net!prodigy.com!newscon02.news.prodigy.net!prodigy.net!news.glorb.com!newsfeed.news2me.com!news.skynet.be!195.238.0.222.MISMATCH!newsspl501.isp.belgacom.be!tjb!not-for-mail Message-Id: <46ef926a$0$13853$ba620e4c@news.skynet.be> From: Laurent Pinchart <laurent.pinchart@skynet.be> Subject: Re: Camera Link i/f spec - signal requirements on FVAl/LVAL/DVAL Newsgroups: comp.arch.fpga Date: Tue, 18 Sep 2007 10:55:06 +0200 References: <1190081546.393471.278960@d55g2000hsg.googlegroups.com> User-Agent: KNode/0.10.4 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7Bit Lines: 22 Organization: -= Belgacom Usenet Service =- NNTP-Posting-Host: fbfda5b4.news.skynet.be X-Trace: 1190105706 news.skynet.be 13853 194.78.198.49:52597 X-Complaints-To: usenet-abuse@skynet.be Xref: prodigy.net comp.arch.fpga:136235 X-Received-Date: Tue, 18 Sep 2007 04:55:27 EDT (newsdbm02.news.prodigy.net) fastgreen2000@yahoo.com wrote: > Hi - Can someone point me to where FVAL, LVAL, DVAL relationship > requirements are? > I look at the i/f spec on alacron.com, but it doesn't list any. > > I'm looking for something like > After FVAL goes valid, LVAL should go valid within one line time, > after LVAL goes valid, DVAL should go valid withone one pixel time, > etc. Have you read the camera link specs ? If I remember correctly (I haven't used camera link for years), there are many possible FVAL/LVAL/DVAL modes. FVAL/LVAL can be edge or level sensitive. Most camera link devices are configurable to accommodate several modes of operation. The real fun begins when you find out that your camera and your frame grabber don't support a single common mode :-) Best regards, Laurent Pinchart
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