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RCIngham wrote: > DRAM is tricky because of the multiplexed row/column addresses, and the > need to consider device refresh. > > DDR is tricky because of the need to output and acquire data on both edges > of the clock. > > Use old-fashioned SRAM if at all possible. Unless you are an 'intellectual > masochist' with a lot of spare time... I wish someone would build some sort of inexpensive transactional DRAM controller: send the full 32/36/40/48bits address along with transaction control bits (transaction ID, priority, etc.) and the chip would return the data as soon as it can. With a small built-in cache, the chip could defer writes and re-arrange reads/writes for improved throughput. There is not much info about AMD's G3MX and Intel's AMB2... but given that both aim (among other things) at untying memory technology from CPU/chipset specifications, I am guessing both take care of most memory-type-specific details and some performance tweaks. DRAM is indeed tricky and exploiting the neat performance tricks it offers (like pipelining and access re-ordering) costs quite a bit of logic. From an FPGA point of view, it would be nice to either dump this off-chip or have a single advanced DDR1/2/3 memory controller with quad transaction ports built-in to provide low-latency, high-bandwidth (about 2GB/s per port peak in each direction) DRAM sharing between PPC405_0/1 and user logic - PPC405_0/1 could use one port each, leaving two ports for user logic and the only fabric used, aside from DRAM IOBs and routing, would be the PLB_DRAM and User_DRAM bridges. If an embedded application has no user logic accessing the DRAM, the PPCs could use separate PLB_DRAM bridges for IPLB and DPLB while DSP-like applications that do not use PPCs much could let the PPCs share a single port and use the three others (or all four if the PPCs run off BRAMs and do not need to access DRAM) to feed user logic. Well, the integrated DRAM controller is one "commodity" item that is likely to remain on my wishlist for eternity since FPGA makers are unlikely to risk offering a one-size-fits-all memory controller after most of their clients have spent so much time/money whipping up their own fabric-based implementations.Article: 123376
On 25 Aug, 21:07, tersono <ethel.thef...@ntlworld.com> wrote: > I've realised there are many things I don't know about the synthesis > process under Xilinx XST. > > The top level of code is associated with a .ucf file, which defines > pinout and timing constraints. > > There's a wizard for timing constraints. It writes into the .ucf file. > > What about sub-modules? The synthesis properties can be defined > differently for each sub-module with an xcf file. > > You can opt to use .xcf files under synthesis/properties/use synthesis > constraint file > > Is the timing constraint syntax the same in .xcf as in .ucf? > > ##### "Daddy, where do baby .xcf files come from?" ###### > > How do I enter a .xcf file? There's no obvious way to do it from the > wizard; it writes .ucf files. > > As there seems to be no wizard, must I write constraints into .xcf > files manually? > > Must I use a text editor and set the file type to .xcf? > > When I synthesise the top level, the sub-modules will be synthesised > according to the constraints in their .xcf files. > > Is that correct? > > I've looked at the XST User guide, but I'm still puzzled. > > All comments gratefully received. > > -- > Mit der Dummheit k=E4mpfen G=F6tter selbst vergebens. You may get some help from my blog: http://www.fpgafromscratch.com (part 12) SvenArticle: 123377
Hi friends i have a question regarding ISE Webpack (7.1 to 9.1 versions): Is it possible to override the value of a VHDL generic (e.g. for the top-level module under synthesis)??? Does there exist such option that can be be applied either interactive or from command-line (or both?) This would be a very useful feature and other synthesis tools (for ASICs) do have such option. Thank you in advance Nikolaos KavvadiasArticle: 123378
Hi all Is there a way to keep the settings (specifically the format of signals, and the widht of the name and value column) between runs of the simulator? I find it quite tedious to keep selecting binary for one of my channels, and decimal for one of the others every time I run it again. Thanks for any help. Bart van DeenenArticle: 123379
On Sat, 25 Aug 2007 14:30:33 -0700, svenand <svenand@comhem.se> wrote: <snip> >> >> ##### "Daddy, where do baby .xcf files come from?" ###### >> >> How do I enter a .xcf file? There's no obvious way to do it from the >> wizard; it writes .ucf files. >> <snip> > >You may get some help from my blog: http://www.fpgafromscratch.com >(part 12) > >Sven Many thanks; I've bookmarked the first page of the series. -- Mit der Dummheit kämpfen Götter selbst vergebens.Article: 123380
On Aug 26, 4:00 am, b...@vandeenensupport-com.invalid (Bart van Deenen) wrote: > Hi all > > Is there a way to keep the settings (specifically the format of signals, > and the widht of the name and value column) between runs of thesimulator? > I find it quite tedious to keep selecting binary for one of my channels, > and decimal for one of the others every time I run it again. > > Thanks for any help. > > Bart van Deenen Hi Bart, ISE Simulator should save all the information about your signals from run to run by default. Especially to do with the signals and their individual settings. This is a new capability in ISE 9.1i, so if you are using any older version of the simulator, please upgrade to ISE 9.2i, which is the latest version where any issues with this is fixed. There are some limitations and that has to do with keeping your markers and so on saved, although the fix for this is coming soon. Thanks DuthArticle: 123381
Downloaded ISE 9.2i day before yesterday. Installed t9_2_02i_lin update
and am just going through the counter example in the "ISE 9.1i Quick Start
Tutorial" that is in .../doc/usenglish/books/docs/qst/qst.pdf
Everything works until I try to enter the timing constraints. Double-
clicking "Create Timing Constraints" runs the implement_design function
which ends with the error: Process "Translate" failed.
This seems similar to a posting by Matthias Alles about "xst fails..."
and I did a process_cleanup_files as suggested in that thread.
My output is given below.
Any ideas how to get past this?
thanks
Bob Smith
Reading design: counter.prj
=========================================================================
* HDL Compilation *
=========================================================================
Compiling vhdl file "/Xilinx/bob/tutorial/counter.vhd" in Library work.
Entity <counter> compiled.
Entity <counter> (Architecture <Behavioral>) compiled.
=========================================================================
* Design Hierarchy Analysis *
=========================================================================
Analyzing hierarchy for entity <counter> in library <work> (architecture <Behavioral>).
=========================================================================
* HDL Analysis *
=========================================================================
Analyzing Entity <counter> in library <work> (Architecture <Behavioral>).
Entity <counter> analyzed. Unit <counter> generated.
=========================================================================
* HDL Synthesis *
=========================================================================
Performing bidirectional port resolution...
Synthesizing Unit <counter>.
Related source file is "/Xilinx/bob/tutorial/counter.vhd".
Found 4-bit updown counter for signal <count_int>.
Summary:
inferred 1 Counter(s).
Unit <counter> synthesized.
WARNING:Xst:2734 - Property "use_dsp48" is not applicable for this technology.
=========================================================================
HDL Synthesis Report
Macro Statistics
# Counters : 1
4-bit updown counter : 1
=========================================================================
=========================================================================
* Advanced HDL Synthesis *
=========================================================================
=========================================================================
Advanced HDL Synthesis Report
Macro Statistics
# Counters : 1
4-bit updown counter : 1
=========================================================================
=========================================================================
* Low Level Synthesis *
=========================================================================
Optimizing unit <counter> ...
implementation constraint: INIT=r : count_int_3
implementation constraint: INIT=r : count_int_2
implementation constraint: INIT=r : count_int_1
implementation constraint: INIT=r : count_int_0
=========================================================================
* Partition Report *
=========================================================================
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
WARNING:ProjectMgmt - "/Xilinx/bob/tutorial/counter.ngc" line 0 duplicate design unit:
'Module|counter'
Process "Synthesize" completed successfully
NotUpToDate:generated file list is cmd
ngdbuild -ise "/Xilinx/bob/tutorial/tutorial.ise" -intstyle ise -dd _ngo -i -p xa9500xl
"counter.ngc" counter.ngd is cmd
Command Line: ngdbuild -ise /Xilinx/bob/tutorial/tutorial.ise -intstyle ise -dd
_ngo -i -p xa9500xl counter.ngc counter.ngd
Reading NGO file "/Xilinx/bob/tutorial/counter.ngc" ...
Checking timing specifications ...
Checking Partitions ...
Checking expanded design ...
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
NGDBUILD Design Results Summary:
Number of errors: 0
Number of warnings: 0
Writing NGD file "counter.ngd" ...
Writing NGDBUILD log file "counter.bld"...
NGDBUILD done.
Process "Translate" failed
Article: 123382HI all, I am trying to download Partial bit streams created by Planahead , through ICAP port.The Xilinx board i am using is XUP (xc 2vp 30). I download bitstreams into DDR ,then i am trying to transfer the bitstreams through ICAP to FPGA. All this procedure is taken care of by a program in Power PC. I am using Set Configuration function to do this job. 1. So when i try doing this the program is not completely get written and gets hanged in between. But when i generated raw bit files (using - b option in bitgen) i am able to transfer the whole content , but after downloading, the system is not functioning as expected ( no change in the display). The other thing is that the size of original .bit file is 158kB, and .rbt file is 1356kB - so what makes the .rbt fle so big. 2. I tried downloading .bin file (generated using - g binary : yes option in bitgen) again the whole data is not getting transfered but gets stuck up in between. but the size of this file is only 157kB with header removed. So could please someone help me out with this problem. ajith.Article: 123383
Gabor wrote: > Of course "read the magazine in its entirety" means the on-line > digital > version, not a downloadable pdf. I suspect that is the case so that Xilinx have a means to monitor its readership and perhaps even determine which articles are most widely read?!? Unfortunately the trend appears to be heading towards online "smart" readers/browsers with "fancy" fade-in pop-up menus and custom UI which I - like the OP - find bloody annoying! Give me a plain PDF - which I can read offline and print whichever pages I want for that matter - any day... Last time I came across a HTML document spread across some 40 pages... I 'printed' it to a PDF printer and concatenated all the pages into a nice, neat single PDF file. Infinitely more useful to me in that form. Regards, -- Mark McDougall, Engineer Virtual Logic Pty Ltd, <http://www.vl.com.au> 21-25 King St, Rockdale, 2216 Ph: +612-9599-3255 Fax: +612-9599-3266Article: 123384
On Fri, 24 Aug 2007 14:07:58 -0500, Jon Elson wrote: > > > > >Rutger Stoots wrote: >> I developped the project in 9.2, but the same source compiles in 8.1 as >> well. >> >> The problem is when I compile the source in a 9.2 project and generate a >> "bit"-file, I can't upload (JTAG) it to the board with Impact (yes, I do >> have the latest service packs). If I use the same source in a 8.1 project it >> compiles and uploads smoothly. >> >> Still, I want to use the latest software (e.g. there are better >> optimizations). I have the feeling that some obscure option of Impact or >> Bitgen is different from 9.2 compared to 8.1. >Can you grab a bit file from the 8.1 and try to load it with the 9.2 >Impact? If that fails, it shows the problem is in 9.2's Impact loader. >If it works, then try to load the 9.2 bit file with 8.1 If that fails, >then it shows that the bit file is not created properly, and must be >failing CRC checking on the FPGA. This should narrow the search for the >problem quite a bit. > >Jon > This may not be a convincing test. We have had problems loading bit files across impact versions. We have a bit file built with 9.1 and we have tried loading this under impact 8.2 and 9.2 and both give the same errors. (looking this up on the web shows an incompatable file.) Loading the file using 9.1 on the same machine works. (We have multiple ISE versions avalable on the machine, the bit files are generated elsewhere and downloaded.) Regards, BartArticle: 123385
On Aug 25, 3:00 pm, Sean Durkin <news_ju...@durkin.de> wrote: > Sylvain Munaut <Some...@SomeDomain.com> wrote: > > Hi, > > > I've been working on Virtex 4 with a DDR2 controller for about 1 year > > now and it works fine. The controller is based on MiG generated > > controller that we modified. The changes were some little bug fixes > > and changes in the user interface. > > This controller uses the ISERDES / OSERDES so that at the end, the > > physical interface of DDR2 is 8 bits at 250 MHz and the user interface > > internally is 32 bits at 125 MHz. > > Did you use the same speed in your previous design or ist it slower > now than it was before? Or is the routing maybe different (shorter traces)? It's the same speed as on the V4. I tried 250 MHz and 200 MHz. (DDR2 clock). The board are completely different and I don't know much except they matched the trace length ... (For others infos I have the schema but not the pcb design files). But I used that controller without much trouble on 2 v4 board. And here I just tried two V5 board without success ... > I have a DDR2-design on a Virtex4 as well, running at 125MHz, and the > calibration doesn't work there because the maximum delay the IDELAY can > do is 5ns. I don't remember the exact details, but I think during > calibration they delay the DQS until they detect 2 edges to measure the > cycle time and match it to the FPGA-internal clock, and then set the > delay for the data pins accordingly, so there is a phase difference of > 90 degrees. > > In my case the delaying for the strobes didn't work, the calibration > would just never find the second edge because it could not delay by more > than 5 ns. If you have very short traces between FPGA and DRAM giving > you a delay of maybe 200ps, you have to delay the strobe for another > 3.2ns just to find the first edge, and then another 4ns (if you're > running at 125MHz) to find the second edge, which is a total of 7.2ns, > which the IDLEAY can't give you. So in my case the calibration just > would run to the maximum and then give up. > > I turned it off and fixed the delays manually to get ariound this. When looking with chipscope what it captures, I can't see a signle read success ... SylvainArticle: 123386
In Virtex-5 the BUFIO delay is larger which alters the initial position of the DQ relative to the DQS. The existing Virtex-4 SERDES DDR2 algorithm (XAPP721/723) won't handle this. What's the need for the half frequency design in Virtex-5? Could you use the full frequency design with a shim to conver the data to half speed? In response to the issue with the calibration algorithm running out of taps, the current algorithm can detect the single edge situation at lower frequencies and move the taps away from the edge appropriately to achieve reliable operation. "Sean Durkin" <news_jun07@durkin.de> wrote in message news:5janerF3t7c60U1@mid.individual.net... > Sylvain Munaut <SomeOne@SomeDomain.com> wrote: >> Hi, >> >> I've been working on Virtex 4 with a DDR2 controller for about 1 year >> now and it works fine. The controller is based on MiG generated >> controller that we modified. The changes were some little bug fixes >> and changes in the user interface. >> This controller uses the ISERDES / OSERDES so that at the end, the >> physical interface of DDR2 is 8 bits at 250 MHz and the user interface >> internally is 32 bits at 125 MHz. > Did you use the same speed in your previous design or ist it slower > now than it was before? Or is the routing maybe different (shorter > traces)? > > I have a DDR2-design on a Virtex4 as well, running at 125MHz, and the > calibration doesn't work there because the maximum delay the IDELAY can > do is 5ns. I don't remember the exact details, but I think during > calibration they delay the DQS until they detect 2 edges to measure the > cycle time and match it to the FPGA-internal clock, and then set the > delay for the data pins accordingly, so there is a phase difference of > 90 degrees. > > In my case the delaying for the strobes didn't work, the calibration > would just never find the second edge because it could not delay by more > than 5 ns. If you have very short traces between FPGA and DRAM giving > you a delay of maybe 200ps, you have to delay the strobe for another > 3.2ns just to find the first edge, and then another 4ns (if you're > running at 125MHz) to find the second edge, which is a total of 7.2ns, > which the IDLEAY can't give you. So in my case the calibration just > would run to the maximum and then give up. > > I turned it off and fixed the delays manually to get ariound this. > > HTH, > Sean > > -- > My email address is only valid until the end of the month. > Try figuring out what the address is going to be after that...Article: 123387
Duth <premduth@gmail.com> wrote: > On Aug 26, 4:00 am, b...@vandeenensupport-com.invalid (Bart van > Deenen) wrote: > > Is there a way to keep the settings (specifically the format of signals, > > and the widht of the name and value column) between runs of thesimulator? > > I find it quite tedious to keep selecting binary for one of my channels, > > and decimal for one of the others every time I run it again. > ISE Simulator should save all the information about your signals from > run to run by default. Especially to do with the signals and their > individual settings. This is a new capability in ISE 9.1i, so if you > are using any older version of the simulator, please upgrade to ISE > 9.2i, which is the latest version where any issues with this is fixed. > There are some limitations and that has to do with keeping your > markers and so on saved, although the fix for this is coming soon. I have 9.2.0i running on Linux. When I start the simulation again, it does keep the traces, and the number format on the trace display, but not on the value column. I only now realize that there seems to be a bug in the value column display; it will always initially show values in hex (or binary), even though the corresponding trace shows decimal values (for instance). When you then select "decimal" with the contextual menu, the value column field will also show decimal. The column widths for the names and values are not saved between runs. Thanks for your help. Bart van DeenenArticle: 123388
Hi, Thanks for the info, at least that gives some leads. On Aug 27, 9:19 am, "John Schmitz" <john.schm...@noemail-xilinx.com> wrote: > In Virtex-5 the BUFIO delay is larger which alters the initial position of > the DQ relative to the DQS. The existing Virtex-4 SERDES DDR2 algorithm > (XAPP721/723) won't handle this. How much larger ? How could that be adapted ? Wouldn't changing the default value of the delay to the trick ? > What's the need for the half frequency design in Virtex-5? Could you use > the full frequency design with a shim to conver the data to half speed? The thing is that we customized this controller to fit our needs and we'd rather stick to it. It also has a much easier time meeting timing that the V5 controller because a lot of the logic runs at half the frequency. SylvainArticle: 123389
Hello, does anybody know a synthesizable VME-Bus Core. A few years ago there was a core outside there from silicore with wishbone interface. Is anything similar out there? Regards ChristianArticle: 123390
A nice collection of VLSI interview questions can be found at http://digitalelectronics.blogspot.com/ Also contributors are welcome.Article: 123391
OK Jon, I compiled my sources with 8.1 and 9.2 and got "bitfile81.bit" and "bitfile92.bit". With Impact 8.1 both files are uploaded perfectly and both just do what they should. With Impact 9.2, none of them can be uploaded (Program Failed). So indeed, it seems the Impact 9.2 loader is the problem, not the Xilinx 9.2 compiler. This is the 8.1 log: ------------------- Command: Program -p 0 -defaultVersion 0 // *** BATCH CMD : Program -p 1 -defaultVersion 0 PROGRESS_START - Starting Operation. Chain TCK freq = 0. Validating chain... Boundary-scan chain validated successfully. '1':Programming device... done. '1': Reading status register contents... [ 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 1 1 0 1 1 0 0 ] [ 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 1 1 0 1 1 0 0 ] CRC error : 0 RESERVED : 0 DCM locked : 1 DCI Matched : 1 legacy input error : 0 status of GTS_CFG_B : 1 status of GWE : 1 status of GHIGH : 1 value of MODE pin M0 : 0 value of MODE pin M1 : 0 value of MODE pin M2 : 0 value of CFG_RDY (INIT_B) : 1 DONEIN input from DONE pin : 1 ID_ERROR : 0 RESERVED : 0 RESERVED : 0 INFO:iMPACT:2219 - Status register values: INFO:iMPACT - 0011 0111 0001 1000 0000 0000 0000 0000 INFO:iMPACT:579 - '1': Completed downloading bit file to device. INFO:iMPACT:580 - '1':Checking done pin ....done. '1': Programmed successfully. PROGRESS_END - End Operation. Elapsed time = 6 sec. This is the 9.2 log: ------------------- // *** BATCH CMD : Program -p 1 -defaultVersion 0 Maximum TCK operating frequency for this device chain: 0. Validating chain... Boundary-scan chain validated successfully. '1': Programming device... PROGRESS_START - Starting Operation. done. '1': Reading status register contents... CRC error : 0 RESERVED : 0 DCM locked : 1 DCI Matched : 1 legacy input error : 0 status of GTS_CFG_B : 0 status of GWE : 0 status of GHIGH : 1 value of MODE pin M0 : 0 value of MODE pin M1 : 0 value of MODE pin M2 : 0 value of CFG_RDY (INIT_B) : 1 DONEIN input from DONE pin : 0 ID_ERROR : 0 RESERVED : 0 RESERVED : 0 INFO:iMPACT:2219 - Status register values: INFO:iMPACT - 0011 0001 0001 0000 0000 0000 0000 0000 INFO:iMPACT:579 - '1': Completed downloading bit file to device. INFO:iMPACT - '1': Checking done pin....done. '1': Programming terminated. DONE did not go high. PROGRESS_END - End Operation. Elapsed time = 5 sec. There are differences, I can see that, but what's going on? Checking help files and so on doesn't make me happy either. I simply have no idea where to look. RutgerArticle: 123392
morphiend wrote:
> On Aug 24, 6:52 am, Bert <trala...@joepie.nl> wrote:
>> svenand wrote:
>> > On Aug 23, 11:32 am, bert <trala...@joepie.nl> wrote:
>> >> Hi,
>> >> Does anybody have any luck with running the Xilinx usb-cable driver on
>> >> a Linux 64 system? I'm having severe problems with this. I have done
>> >> the steps below but have run out of ideas.
>> >> 1. system is latest opensuse 10.2 with kernel 2.6.18.8-0.5 The xilinx
>> >> usb cable is detected as:
>> >> $lsusb
>> >> Bus 005 Device 001: ID 0000:0000
>> >> Bus 001 Device 001: ID 0000:0000
>> >> Bus 002 Device 001: ID 0000:0000
>> >> Bus 007 Device 001: ID 0000:0000
>> >> Bus 006 Device 001: ID 0000:0000
>> >> Bus 004 Device 001: ID 0000:0000
>> >> Bus 003 Device 003: ID 0bda:8187 Realtek Semiconductor Corp.
>> >> Bus 003 Device 002: ID 03fd:0008 Xilinx, Inc.
>> >> Bus 003 Device 001: ID 0000:0000
>>
>> >> I tried the udev driver, compiled as 32 bits but when preloaded I get
>> >> ERROR: ld.so: object './libusb-driver.so' from LD_PRELOAD cannot be
>> >> preloaded: ignored.
>> >> Compiled as 64 bits gives the same problem.
>> >> The contents of /etc/udev/rules.d/xusbdfwu.rules is:
>> >> SYSFS{idVendor}=="03fd", SYSFS{idProduct}=="0008", NAME="windrvr6"
>> >> BUS=="usb", ACTION=="add", SYSFS{idVendor}=="03fd",
>> >> SYSFS{idProduct}=="0007", RUN+="/sbin/fxload -v -t
>> >> fx2 -I /usr/share/xusbdfwu.hex -D $TEMPNODE"
>> >> BUS=="usb", ACTION=="add", SYSFS{idVendor}=="03fd",
>> >> SYSFS{idProduct}=="0009", RUN+="/sbin/fxload -v -t
>> >> fx2 -I /usr/share/xusbdfwu.hex -D $TEMPNODE"
>> >> BUS=="usb", ACTION=="add", SYSFS{idVendor}=="03fd",
>> >> SYSFS{idProduct}=="000b", RUN+="/sbin/fxload -v -t
>> >> fx2 -I /usr/share/xusbdfwu.hex -D $TEMPNODE"
>> >> BUS=="usb", ACTION=="add", SYSFS{idVendor}=="03fd",
>> >> SYSFS{idProduct}=="000d", RUN+="/sbin/fxload -v -t
>> >> fx2 -I /usr/share/xusbdfwu.hex -D $TEMPNODE"
>> >> BUS=="usb", ACTION=="add", SYSFS{idVendor}=="03fd",
>> >> SYSFS{idProduct}=="000f", RUN+="/sbin/fxload -v -t
>> >> fx2 -I /usr/share/xusbdfwu.hex -D $TEMPNODE"
>> >> ACTION=="add", BUS=="usb", SYSFS{idVendor}=="03fd", MODE="666"
>>
>> >> And I think this is correct.
>> >> f I manually run
>> >> sbin/fxload with the options above and -D /proc/bus/usb/003/002
>> >> I can see that the cable is addressed on the spartan 3A board, but
>> >> afterwards a lsusb shows:
>> >> Device 001: ID 0000:0000
>> >> Bus 001 Device 001: ID 0000:0000
>> >> Bus 002 Device 001: ID 0000:0000
>> >> Bus 007 Device 001: ID 0000:0000
>> >> Bus 006 Device 001: ID 0000:0000
>> >> Bus 004 Device 001: ID 0000:0000
>> >> Bus 003 Device 005: ID 03fd:0008 Xilinx, Inc.
>> >> Bus 003 Device 003: ID 0bda:8187 Realtek Semiconductor Corp.
>> >> Bus 003 Device 001: ID 0000:0000
>>
>> >> Any ideas? Anybody have any luck with modifying the makefile of
>> >> windrvr64 driver to get a decent 2.6.18 kerneldriver or any clue on
>> >> the LD_PRELOAD problem?
>> >> Taco
>>
>> > Have you tried the libusb-driver developed by Michael Gernoth. Read my
>> > blog to find out more.
>> >http://svenand.blogdrive.com/archive/55.html
>>
>> > Sven
>>
>> thanks, but I exactly did this xx times. I've this driver, but it doesn't
>> want to be preloaded somehow. The 64 bits neither. I've now only once
>> succeeded in loading the driver and the cable is recognized, but
>> programming failed. after quitting impact I get again the same problems
>> and a careful repetition of all actions gives the same result. Because
>> the cable is showing with correct ID in lsusb listings, I suppose that
>> the udev stuff is executed (I presume the name Xilinx is somewhere in
>> these hex files). I'm afraid this is (again) a kernel issue with the
>> opensuse 64 bit handling. Trying to do it with a different 32 bit PC...
>> Asking xilinx for a working kernel driver will not help I presume.
>> Taco
>
> Xilinx mentioned a few months ago that they were going to support an/
> the open-source driver w/ their tools and it was in fact being shipped
> to certain beta users. The link to the exact post is on the libusb-
> driver website under the link "XILINX listened". I bet if you asked
> you may be able to get the driver for beta testing in your
> environment.
>
> -- Mike
Just for logging reasons some notes to the problem above.
I solved the problem.
1. Opensuse 10.2 needs to have kernel 2.6.18.8-0.5
2. The device is recognized as before, but is able to lock up unexpectedly
because some semaphore is not released. The only way to recover from this
is executing
echo -e 'cleancablelock\nexit'|impact -batch
which shows the release of the semaphores. After doing this it's possible to
start impact and the whole jtag chain is recognized.
3. I still see messages like
ERROR: ld.so: /xilinx-usb-driver/libusb-driver.so' from LD_PRELOAD cannot be
preloaded: ignored
but it still works. and the preload is necessary to have this fake windrvr6
driver installed.
4. library libusb-driver.so of course compiled for 32 bit when working on a
64 bits machine, but that was already reported in several threads.
taco
Article: 123393On 26 ago, 23:07, Bob Smith <use...@linuxtoys.org> wrote: > Downloaded ISE 9.2i day before yesterday. Installed t9_2_02i_lin update > and am just going through the counter example in the "ISE 9.1i Quick Start > Tutorial" that is in .../doc/usenglish/books/docs/qst/qst.pdf > > Everything works until I try to enter the timing constraints. Double- > clicking "Create Timing Constraints" runs the implement_design function > which ends with the error: Process "Translate" failed. > > This seems similar to a posting by Matthias Alles about "xst fails..." > and I did a process_cleanup_files as suggested in that thread. > > My output is given below. > > Any ideas how to get past this? > > thanks > Bob Smith > > Reading design: counter.prj > > ========================================================================= > * HDL Compilation * > ========================================================================= > Compiling vhdl file "/Xilinx/bob/tutorial/counter.vhd" in Library work. > Entity <counter> compiled. > Entity <counter> (Architecture <Behavioral>) compiled. > > ========================================================================= > * Design Hierarchy Analysis * > ========================================================================= > Analyzing hierarchy for entity <counter> in library <work> (architecture <Behavioral>). > > ========================================================================= > * HDL Analysis * > ========================================================================= > Analyzing Entity <counter> in library <work> (Architecture <Behavioral>). > Entity <counter> analyzed. Unit <counter> generated. > > ========================================================================= > * HDL Synthesis * > ========================================================================= > > Performing bidirectional port resolution... > > Synthesizing Unit <counter>. > Related source file is "/Xilinx/bob/tutorial/counter.vhd". > Found 4-bit updown counter for signal <count_int>. > Summary: > inferred 1 Counter(s). > Unit <counter> synthesized. > > WARNING:Xst:2734 - Property "use_dsp48" is not applicable for this technology. > > ========================================================================= > HDL Synthesis Report > > Macro Statistics > # Counters : 1 > 4-bit updown counter : 1 > > ========================================================================= > > ========================================================================= > * Advanced HDL Synthesis * > ========================================================================= > > ========================================================================= > Advanced HDL Synthesis Report > > Macro Statistics > # Counters : 1 > 4-bit updown counter : 1 > > ========================================================================= > > ========================================================================= > * Low Level Synthesis * > ========================================================================= > > Optimizing unit <counter> ... > implementation constraint: INIT=r : count_int_3 > implementation constraint: INIT=r : count_int_2 > implementation constraint: INIT=r : count_int_1 > implementation constraint: INIT=r : count_int_0 > > ========================================================================= > * Partition Report * > ========================================================================= > > Partition Implementation Status > ------------------------------- > > No Partitions were found in this design. > > ------------------------------- > WARNING:ProjectMgmt - "/Xilinx/bob/tutorial/counter.ngc" line 0 duplicate design unit: > 'Module|counter' > > Process "Synthesize" completed successfully > NotUpToDate:generated file list is cmd > ngdbuild -ise "/Xilinx/bob/tutorial/tutorial.ise" -intstyle ise -dd _ngo -i -p xa9500xl > "counter.ngc" counter.ngd is cmd > > Command Line: ngdbuild -ise /Xilinx/bob/tutorial/tutorial.ise -intstyle ise -dd > _ngo -i -p xa9500xl counter.ngc counter.ngd > > Reading NGO file "/Xilinx/bob/tutorial/counter.ngc" ... > > Checking timing specifications ... > Checking Partitions ... > Checking expanded design ... > > Partition Implementation Status > ------------------------------- > > No Partitions were found in this design. > > ------------------------------- > > NGDBUILD Design Results Summary: > Number of errors: 0 > Number of warnings: 0 > > Writing NGD file "counter.ngd" ... > > Writing NGDBUILD log file "counter.bld"... > > NGDBUILD done. > > Process "Translate" failed Read the line: WARNING:Xst:2734 - Property "use_dsp48" is not applicable for this technology.Article: 123394
Hi everyone I am working on some FPGA project and I need to define one port as bidirectional. This is my VHDL code ------------------------------------------------------------------------------------------------------------------- Library Ieee; Use ieee.std_logic_1164.all; Use Ieee.std_logic_arith.all; Use ieee.std_logic_unsigned.all; Library work; -------------------------------------------------------------------------------- entity io_test_contr is port( con : in std_logic; en_count : out std_logic; bidi : inout std_logic; test : out std_logic ); end io_test_contr; -------------------------------------------------------------------------------- architecture io_test_contr_behav of io_test_contr is signal temp : std_logic; begin process(con, bidi) begin if con='1' then bidi<='1'; en_count<='0'; else bidi<='Z'; if bidi='0' then en_count<='0'; else en_count<='1'; end if; end if; test<='Z'; end process; end architecture; I have compiled and programed my fpga and I am not totaly clear about somethig. When I use bidirectional pin as input it should be in high inpedanse mode, isn't it. But, when I measure the volatage on that pin (with multimeter) I am getting 5V. I don't know from where comes this 5V. I am very confused. Thanks for any kind of help ZoranArticle: 123395
Hi,
I rarely use null statement in my designs.
I check the definition of null statement from book "HDL Chip Design"
written by Douglas J. Smith. It says that "Performs no action. Has no
other effect other than to pass execution on to the next sequential
statement."
I have two questions:
1. Based on my experiences with VHDL, the following 3 designs should
be the same.
State_A is a state machine signal.
A1 : process(RESET, CLK)
begin
if(RESET = '1') then
State_A <= State_0_S;
elsif(CLK'event and CLK = '1') then
case State_A is
when State_0_S =>
if(A = '1') then
State_A <= State_1_S;
else
State_A <= State_0_S;
end if;
...
...
end case;
end if;
end process;
A2 : process(RESET, CLK)
begin
if(RESET = '1') then
State_A <= State_0_S;
elsif(CLK'event and CLK = '1') then
case State_A is
when State_0_S =>
if(A = '1') then
State_A <= State_1_S;
else
null;
end if;
...
...
end case;
end if;
end process;
A3 : process(RESET, CLK)
begin
if(RESET = '1') then
State_A <= State_0_S;
elsif(CLK'event and CLK = '1') then
case State_A is
when State_0_S =>
if(A = '1') then
State_A <= State_1_S;
end if;
...
...
end case;
end if;
end process;
2. Where can I download the latest version of VHDL language definition
(83, 90 2000)?
Any comments are welcome.
Thank you.
Weng
Article: 123396
"Zorjak" <Zorjak@gmail.com> wrote in message
news:1188229899.731509.223520@d55g2000hsg.googlegroups.com...
>
> I have compiled and programed my fpga and I am not totaly clear about
> somethig. When I use bidirectional pin as input it should be in high
> inpedanse mode, isn't it. But, when I measure the volatage on that pin
> (with multimeter) I am getting 5V. I don't know from where comes this
> 5V. I am very confused.
Try grounding this pin through a let's say 5K resistor and see if it will
still be at 5V.
Your synthesizer might not be recognizing a bidirectional signal properly
because you mixed it up with other stuff in the same process. In my
experience it is better to code such things separately following templates
precisely:
<output> <= <input> when <enable> ='0' else 'Z';
OR if you prefer using processes:
process (<enable>, <input>)
begin
if (<enable>='0') then
<output> <= <input>;
else
<output> <= 'Z';
end if;
end process;
If you are using Xilinx open your design in FPGA Editior and see what has
actually been synthesized...
/Mikhail
Article: 123397
Weng Tianxiang wrote:
> I rarely use null statement in my designs.
They sometimes make a nice placeholder for a comment:
...
else
null; -- future: enable explosive bolts here.
end if;
> I have two questions:
> 1. Based on my experiences with VHDL, the following 3 designs should
> be the same.
Yes. What's the question?
> 2. Where can I download the latest version of VHDL language definition
> (83, 90 2000)?
http://www.ieee.org/web/standards/home/index.html
-- Mike Treseler
Article: 123398Lattice is holding a webcast this Wednesday, August 29th, "Tips to Avoid Simultaneous Switching Output (SSO) Noise Problems." The presenters will be Troy Scott, from our software marketing group and Bertrand Leigh, from our applications engineering group. If you're interested, the event takes place live at 11am Pacific, 18:00 GMT. In addition, you will be able to view this webcast archive on-demand, at your convenience, within 24 hours after the live event takes place. You can register by clicking: http://www.latticesemi.com/corporate/webcasts/tipstoavoidsimultaneoussw/index.cfm Bart Borosky, LatticeArticle: 123399
On Aug 27, 10:37 am, Mike Treseler <mike_trese...@comcast.net> wrote: > Weng Tianxiang wrote: > > I rarely use null statement in my designs. > > They sometimes make a nice placeholder for a comment: > > ... > else > null; -- future: enable explosive bolts here. > end if; > > > I have two questions: > > 1. Based on my experiences with VHDL, the following 3 designs should > > be the same. > > Yes. What's the question? > > > 2. Where can I download the latest version of VHDL language definition > > (83, 90 2000)? > > http://www.ieee.org/web/standards/home/index.html > > -- Mike Treseler Hi Mike, Thank you. It seems to me that I should buy a VHDL standard book (I've never have it). 93 or 2000 or 2002? Any suggestions? Weng
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