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I don't know if this helps but I used Simgen to generate the bmm file for MicroBlaze. See my blog: http://svenand.blogdrive.com/archive/68.html SvenArticle: 122876
On 9 Aug., 02:03, Clement <cjose...@gmail.com> wrote: > Hi all: > > I am trying to reconstruct a periodic exponential signal curve. The > signal is in the order of 10-20mV. The total length of this curve is > 100ns. Even though the total length is 100ns, the peak bandwidth of > the signal maybe in the order of 100MHz. I thought about getting only > one data point for each period and delay the sampling instance and > collect further points (similar to time-interleaved sampling). I have > a programmable delay line, which can produce delays in the multiples > of 200ps. The goal is to reconstruct the signal curve, no matter how > slow the reconstruction is. You do not need a delay line. Just chose the period of your signal and your sampling frequency appropriately. For example if you sample with a 101ns period you get 1GHz equivalent time sampling because you hit your signal at relative position t, t +1ns, t+2ns, ... Kolja SulimmaArticle: 122877
In news:1186646265.701788.284950@q3g2000prf.googlegroups.com timestamped Thu, 09 Aug 2007 07:57:45 -0000, fpgabuilder <fpgabuilder-groups@yahoo.com> posted: |----------------------------------------------------------------------| |"I have - | | | |MY_FPGA <--parallel bus--> DEVICE | | | |I want to make it so that the DEVICE operates only if MY_FPGA is | |connected to it. I need to make this connection secure enough to pass| |Military Export controls. [..]" | |----------------------------------------------------------------------| No thing can exist such that it is secure.Article: 122878
You are confused with the design flow in ISE. HDL gets turned into a netlist using XST. Once you have a netlist you can't synthesize it again. It's better to set the top level to HDL and instantiate your core/netlist in the HDL code if you want to test it.Article: 122879
In news:1186594403.794741.205010@x40g2000prg.googlegroups.com timestamped Wed, 08 Aug 2007 17:33:23 -0000, kempaj@yahoo.com posted: |----------------------------------------------------------------------------| |"[..] | | | |There is a great deal of functionality that a modern web based forum | |can provide that leaves usenet in the dust anyways. For example, being | |able to freely host design files showing an example, screen shot of a | |problem, etc.; things usenet will ultimately die off to. [..] | | | |Jesse Kempa | |Altera" | |----------------------------------------------------------------------------| It is possible to attach screenshots to newsgroup posts. Regards, Colin Paul GlosterArticle: 122880
> Has anybody tried the new version of the Multi Port Memory Controller ? The new version is about the same as the fist one. The MPMC2 is a very powerful architecture available for a couple of years. The problem is that it supports only DDR or DDR2 and is NOT just a few clicks to get it running. GuruArticle: 122881
On Aug 8, 7:12 pm, ferorcue <le_m...@hotmail.com> wrote: > Hello, I have designed a IP Slave connected to the PLB bus. > My IP Slave to the PLB is a Bus bridge which connect the PLB to > another Bus and a Coprocessor connected to this other Bus. My second > bus allow transfer of 64 bits and there is a DMA conected to this bus. > I want to write to data of 64 bits to the addres 0x2000 and 0x2001, > the addres of the DMA. If I write this data the DMA start to work and > copy from a memory to a Bram conected to the plb in the memory addres > FF000000 > > I need to transfer these data: > addr= 0x00002000 data=0x00000000FF000000 // source (bram) in the > second bus and Destination (bram in the plb) > addr= 0x00002001 data=0x0000000100000005 //start data and Frame > relay ( a burst of 5 double words stored previously in the bram of the > second bus) > > I want to do it from the PowerPC, that means I have to create a C > program to do it. The drivers created for Xilinxs Platform Studio make > transaction of 32 bits. They make also transaction of a Struct of 64 > bits, with lower and Upper part. This transaction takes place in two > operations. First copy to addr 0x00002000 the data 0x00000000 00000000 > and with a BE byte enable to choose only the first 32 bits and write > to the address 0x2004 of the data 0x FF000000 FF000000. with byte > enable. But this is not the operation that I need to run the DMA. > > Have someone any idea? > > I saw this information in this forum, that was written in 2006, I > would like to know if one year later have someone a solution. Thank > you > > Question: > I have a piece of IP that acts as a slave on the PLB. I would like > writes to this IP to be 64bits, while reads from it are OK at 32bits. > The sample driver that was generated by the IP wizard gives functions > for reads/writes or 32 bits as expected (by mapping them to > XIo_In/Out32). Do I need to do writes in two transfers? If not, how > do I write 64bits? I've looked over the PPC 405 Block Reference > Guide > and it seems that it should be possible to read/write 64 bits all at > once just by virtue of having that wide of a bus coming in and out of > the block. The cacheline transfers are discussed in that document as > possibly being doublewords. I am a bit confused by all of this (if > that > wasn't clear already). I would probably be able to find my answer > after a good deal of time/pain, but hopefully someone out there can > clarify things a little for me. Just knowing if it was possible or > not > for a user program to do the 64bit write would help me move forward. > I'd appreciate any clarification and/or pointers to relevant > documentation. I can provide more info about my design or my > confusion > if it is useful. > Answer: > The fundamental limitation here is that the PowerPC-405 is a 32-bit > core. So > there are no instructions to load/store 64 bits of data at a time as > an > atomic unit. So from the processor core's perspective, you have to do > two > 32-bit stores. (The XIo_In and XIo_Out functions are basically just a > wrapper around load/store instructions, but with an added "eieio" to > make > sure the operations don't get re-ordered by the hardware.) > As you say, the PLB is in fact capable of doing multi-word transfers, > and is > wide enough to do 64-bit transfers in a single data beat. However, > aside > from enabling this functionality in the first place, the prWocessor > has no > control over whether this actually occurs. > Without having done any experiments, my gut feeling is that using two > calls > to XIo_Out() back to back will not result in a 64-bit transfer, > because of > these "eieio"s. Your best bet is probably to try something like: > typedef unsigned long long bits64; > volatile bits64 *my_reg = (volatile bits64 *)(REG_ADDRESS); > *my_reg = some_value; > ...and then watch the bus and see what happens. > Hope that helps, or least makes sense... :) > > typedef unsigned long long My_Xuint64 ; > I tried with this, but the result is the same. > volatile My_Xuint64 *my_reg = (volatile My_Xuint64 *) > (XPAR_P2O_0_BASEADDR); > *my_reg = 0x0000000100000002; > > I get a warning which says that the value is too big for a "long" > type, but I defined it like a long long. I do not. I am also confused > like the other guy. Alan is right: 64 bit transactions are out of the question. Remodify your DMA to integrate 32/64 MUX. Your idea might work in MPMC2 architecture on 64bit NPI port. GuruArticle: 122882
On Thu, 09 Aug 2007 10:11:27 -0000, "jacobusn@xilinx.com" <naude.jaco@gmail.com> wrote: >You are confused with the design flow in ISE. > >HDL gets turned into a netlist using XST. Once you have a netlist you >can't synthesize it again. It's better to set the top level to HDL and >instantiate your core/netlist in the HDL code if you want to test it. You can also set a "black-box" attribute to the instance of the core in the top-level design. Then XST will not worry about it. The back end tools (Translate/Map/PAR) need to be able to find the NGC file; either in the project directory or via a search path. - BrianArticle: 122883
On Aug 9, 12:07 pm, Colin Paul Gloster <Colin_Paul_Glos...@ACM.org> wrote: > Innews:1186646265.701788.284950@q3g2000prf.googlegroups.com > timestamped Thu, 09 Aug 2007 07:57:45 -0000, > fpgabuilder <fpgabuilder-gro...@yahoo.com> posted: > |----------------------------------------------------------------------| > |"I have - | > | | > |MY_FPGA <--parallel bus--> DEVICE | > | | > |I want to make it so that the DEVICE operates only if MY_FPGA is | > |connected to it. I need to make this connection secure enough to pass| > |Military Export controls. [..]" | > |----------------------------------------------------------------------| > > No thing can exist such that it is secure. It depends of the DEVICE ... But if it has some secure memory (i.e. protected against attacks), you could store a key in it. Then, don't take any key, but a key derivated from a PUF from MY_FPGA. So that the key isn't present in the FPGA bitstream itself. That will make the key unique per board ... SylvainArticle: 122884
On 9 Aug., 02:04, Alan Nishioka <a...@nishioka.com> wrote: > As the answer you provided in your post says, you can't generate a 64 > bit access from the 32 bit powerpc core. > > The data cache or the instruction cache can but you can't. Yep. Even the "lmw" and "stmw" instructions use seperate 32-bit accesses. Kolja SulimmaArticle: 122885
svenand <svenand@comhem.se> wrote: > See my blog: http://svenand.blogdrive.com/archive/68.html Hi Sven thanks for the great series. Unfortunately I only have the ISE environment, and I don't (think I) have the simgen tool. What surprises me most is the error message that the code segment occupies from 0x0 to 0x9ff, whereas the mem file is really only 1024 lines of data, each being 5 nibbles, line# 1 @00000000 2 00000 3 2E004 4 2C080 ... 1025 340FD That is funny, the 0xA00 is the number of bytes in the 1024 lines of 20 bits. So it doesn't realize those things are 18 bit words! I hope someone comes up with the answer. Thanks for thinking with me. BartArticle: 122886
On Aug 9, 6:37 am, "Sylvain Munaut <Some...@SomeDomain.com>" <246...@gmail.com> wrote: > On Aug 9, 12:07 pm, Colin Paul Gloster <Colin_Paul_Glos...@ACM.org> > wrote: > > > Innews:1186646265.701788.284950@q3g2000prf.googlegroups.com > > timestamped Thu, 09 Aug 2007 07:57:45 -0000, > > fpgabuilder <fpgabuilder-gro...@yahoo.com> posted: > > |----------------------------------------------------------------------| > > |"I have - | > > | | > > |MY_FPGA <--parallel bus--> DEVICE | > > | | > > |I want to make it so that the DEVICE operates only if MY_FPGA is | > > |connected to it. I need to make this connection secure enough to pass| > > |Military Export controls. [..]" | > > |----------------------------------------------------------------------| > > > No thing can exist such that it is secure. > > It depends of the DEVICE ... > But if it has some secure memory (i.e. protected against attacks), you > could store a key in it. Then, don't take any key, but a key derivated > from a PUF from MY_FPGA. So that the key isn't present in the FPGA > bitstream itself. > > That will make the key unique per board ... > > Sylvain Thanks Sylvain. Actually, the FPGA bit-stream is protected by AES. But my problem is that I want to make the system such that the DEVICE would recognize that MY_FPGA is connected to it. The problems I face are - 1. Someone can snoop the wires and replicate the same key as MY_FPGA writes to the DEVICE. 2. DEVICE is an asic. I do not know what challenges are in putting a non-volatile secured memory into a standard CMOS asic. -sanjayArticle: 122887
I got it!!!!
xilinx answer database nr 21460 helped me. The correct bmm file is
ADDRESS_SPACE ram RAMB18 INDEX_ADDRESSING [0x00000000:0x000003FF]
BUS_BLOCK
top/ram/program_rom/ram_1024_x_18_1 [17:0] LOC = X0Y0;
END_BUS_BLOCK;
END_ADDRESS_SPACE;
It's probably the INDEX_ADDRESSING tag, but I don't really care, I'm in
business now. I'll figure out the fine details later.
I'm a really experienced programmer and electronics designer, but this
journey into fpga land is steep!!! I love it :-)
Bart
Article: 122888Hello all, I'm working on a FPGA design that runs in board with a Virtex-II that doesn't have any reset signal. I have some doubts about this. On one side, It is supposed that everthing in the FPGA is clear after power up by GSR (please advise me if I'm confused). In this sense, I have read a paper wrote by Ken Chapman in TechXclusives that says that global reset is not needed in FPGAs. On the other side, "Virtex-II Platform FPGA User Guide" says that GSR doesn't affect to SelectRAMs and shift registers and I have some doubts about DCMs as they should have an asynchronous reset. So my questions are: 1. Can I use GSR as asynchronous global reset (including DCM)? If not, suggestions are welcome. 2. Is it better that I leave DCM RST to 0? Regards, Daniel GutierrezArticle: 122889
On Aug 9, 4:08 am, "comp.arch.fpga" <ksuli...@googlemail.com> wrote: > On 9 Aug., 02:03, Clement <cjose...@gmail.com> wrote: > > > Hi all: > > > I am trying to reconstruct a periodic exponential signal curve. The > > signal is in the order of 10-20mV. The total length of this curve is > > 100ns. Even though the total length is 100ns, the peak bandwidth of > > the signal maybe in the order of 100MHz. I thought about getting only > > one data point for each period and delay the sampling instance and > > collect further points (similar to time-interleaved sampling). I have > > a programmable delay line, which can produce delays in the multiples > > of 200ps. The goal is to reconstruct the signal curve, no matter how > > slow the reconstruction is. > > You do not need a delay line. Just chose the period of your signal and > your sampling frequency appropriately. > For example if you sample with a 101ns period you get 1GHz equivalent > time sampling because you hit your signal at relative position t, t > +1ns, t+2ns, ... > > Kolja Sulimma The reason for my chosing the delay line was to use the same clock pulse which is used to generate the source (producing the periodic exponential signal). But I think your suggestion looks good. I can as well use two independent clocks. Is there any place where I can buy two clocks integrated in one package, which start pulsing at the same instant but with slightly different periods (for example, 100ns and 101ns)?? Is there any other considerations to be taken care of?? Any suggestion on ADC or FPGA board selection?? Your help is greatly appreciated. Thanks, JoeArticle: 122890
Daniel, Lots of questions here, let me see if I can help. -snip- > On one side, It is supposed that everything in the FPGA is clear after > power up by GSR (please advise me if I'm confused). Not exactly true. GSR (global set, reset) places a value in each and every CLB DFF based on the programming of the bitstream. If you implemented a flip flop, and you had it starting out as a '1', then asserting GSR puts all of the flip flops into the state you told it to start at. In this sense, I > have read a paper wrote by Ken Chapman in TechXclusives that says that > global reset is not needed in FPGAs. That is true, but read on.... > On the other side, "Virtex-II Platform FPGA User Guide" says that GSR > doesn't affect to SelectRAMs and shift registers and I have some > doubts about DCMs as they should have an asynchronous reset. That is correct: GSR ONLY affects CLB DFF state. So if it only affects DFF's, then it does not affect anything else. That is everything else. > So my questions are: > 1. Can I use GSR as asynchronous global reset (including DCM)? No, GSR only affects DFF state. There are applications notes which detail the use of a SRL16 to reset the DCM after startup. http://www.xilinx.com/xlnx/xil_ans_display.jsp?iCountryID=1&iLanguageID=1&getPagePath=18181&BV_SessionID=@@@@1702440645.1186674189@@@@&BV_EngineID=cccfaddljeikmilcefeceihdffhdfjf.0 or http://tinyurl.com/2g5uc5 details the solution, as well as cascading rules. Just because the reset for the DCM is 'asynchronous', does not imply you can not use a signal synchronous with CLKIN! That works just as well, also! AustinArticle: 122891
On Aug 9, 8:47 am, austin <aus...@xilinx.com> wrote: > Daniel, > > Lots of questions here, let me see if I can help. > > -snip- > > > On one side, It is supposed that everything in the FPGA is clear after > > power up by GSR (please advise me if I'm confused). > > Not exactly true. GSR (global set, reset) places a value in each and > every CLB DFF based on the programming of the bitstream. If you > implemented a flip flop, and you had it starting out as a '1', then > asserting GSR puts all of the flip flops into the state you told it to > start at. > > In this sense, I > > > have read a paper wrote by Ken Chapman in TechXclusives that says that > > global reset is not needed in FPGAs. > > That is true, but read on.... > > > On the other side, "Virtex-II Platform FPGA User Guide" says that GSR > > doesn't affect to SelectRAMs and shift registers and I have some > > doubts about DCMs as they should have an asynchronous reset. > > That is correct: GSR ONLY affects CLB DFF state. > > So if it only affects DFF's, then it does not affect anything else. > That is everything else. > > > So my questions are: > > 1. Can I use GSR as asynchronous global reset (including DCM)? > > No, GSR only affects DFF state. There are applications notes which > detail the use of a SRL16 to reset the DCM after startup. > > http://www.xilinx.com/xlnx/xil_ans_display.jsp?iCountryID=1&iLanguage... > orhttp://tinyurl.com/2g5uc5 > > details the solution, as well as cascading rules. Just because the > reset for the DCM is 'asynchronous', does not imply you can not use a > signal synchronous with CLKIN! That works just as well, also! > > Austin In my designs, the input clock has been present before configuration completes, so I have never bothered to reset DCMs. If it's necessary, I believe you can set the STARTUP_WAIT attribute on your DCM and then set a bitgen option called LCK_cycle so that startup is delayed until the DCM is locked. Details in your Xilinx user guide and software manuals. BarryArticle: 122892
On Aug 8, 10:54 am, austin <aus...@xilinx.com> wrote: > Perhaps, > > But, if the policy is that no Xilinx employee should be communicating in > any pubic forum without permission and review, why bother? Freudian slip there on the type of forum that the Xilinx employees need permission for.....but a funny one none the less. > > Creating a non-public forum may have benefit. > > Austin It's probably best left to the lawyers, but I don't think Xilinx ownership of the forum which they then invite non-Xilinx employees to join would constitute a 'non-public forum' without those non-X people signing a non-disclosure agreement. Bottom line is that I think the X forum is still most likely a 'public forum' and the X employees probably should still treat it as such from the standpoint of possible dismissal from the company. KJArticle: 122893
Colin Paul Gloster wrote:
> It is possible to attach screenshots to newsgroup posts.
However, non-text attachments are filtered
from usenet exchanges. An http reference to
a graphics file works because it is a text
pointer.
-- Mike Treseler
Article: 122894On Aug 9, 9:34 am, KJ <Kevin.Jenni...@Unisys.com> wrote: >> > It's probably best left to the lawyers, but I don't think Xilinx > ownership of the forum which they then invite non-Xilinx employees to > join would constitute a 'non-public forum' without those non-X people > signing a non-disclosure agreement. Bottom line is that I think the X > forum is still most likely a 'public forum' and the X employees > probably should still treat it as such from the standpoint of possible > dismissal from the company. > KJ I have posted several thousand times in this newsgroup; I have never asked Xilinx management or lawyers for permission; I have never been reprimanded either. It all boils down to having a sense of responsibility plus some common sense. "The first thing we do, let's kill all the lawyers". - (The Bard, Henry VI, Act IV, Scene II). Peter AlfkeArticle: 122895
Hi all, I'm doing a project with a Xilinx University Project Virtex-II Pro board. For this I'm using the compact flash card-reader interfaced with a microblaze instantiated on the FPGA. I'm using EDK 9.1.02i and I'm using the xilfatfs library to interface with the flash reader. This library provides a header sysace_stdio.h which replicates much of the standard C file-handling functionality using functions like sysace_fopen(), sysace_fread() and so on. However I was looking for a way to check for end-of-file (similar to the standard C feof() function) and could not find any, beyond the vague assertion that sysace_fread() returns 0 on error; however, this error is not necessarily end-of-file. The documentation[1] mentions nothing of setting errno or otherwise reporting the nature of the error. Is there any way to check definitively whether you have reached the end of a file using xilfatfs? Is there another way of interfacing my C program with the compact flash reader than xilfatfs? Many thanks, Phil [1] Documentation here: http://www.xilinx.com/ise/embedded/edk91i_docs/xilfatfs_v1_00_a.pdfArticle: 122896
Andreas Schwarz wrote: > Has anyone found a workaround to use fixed_pkg with ISE? I haven't even tried since the author of the package reported: "After fixing everything, it gave me the error: INTERNAL_ERROR:Xst:cmain.c:3111:1.8.6.1 - To resolve this error, please consult the Answers Database and other online resources at http://support.xilinx.com This is a "use at your own risk" one I guess. I would recommend Synplicity, which seems to work much better."Article: 122897
KJ, The Xilinx Forum is a different animal: there are procedures, and people specifically tasked with monitoring it, editing it, and in fact "controlling" it. If my job description states I am required to maintain and post on a forum, then I expect I am trained in the policies, and am then able to do my job. AustinArticle: 122898
On Aug 9, 5:39 pm, Joe <cjose...@gmail.com> wrote: > But I think your suggestion looks good. I can as well use two > independent clocks. Is there any place where I can buy two clocks > integrated in one package, which start pulsing at the same instant but > with slightly different periods (for example, 100ns and 101ns)?? You do not need to start them at the same instant. You get a periodic image of a periodic signal. If you care about the phase alignment at all you can probably figure it out from the data anyway. If you know the frequency of your signal you can even measure the exact frequency of your sampling crystal from the data. You can use pretty much any ADC if you add a fast sample and hold circuit in front. But there also are ADCs that have a bandwidth well above their sampling frequency. Kolja SulimmaArticle: 122899
On Aug 9, 4:37 pm, fpgabuilder <fpgabuilder-gro...@yahoo.com> wrote: > 1. Someone can snoop the wires and replicate the same key as MY_FPGA > writes to the DEVICE. google "challenge response". > 2. DEVICE is an asic. I do not know what challenges are in putting a > non-volatile secured memory into a standard CMOS asic. You probably need to use battery backed up storage or PROM, depending on your requirements. But the bottom line is: There is no way you can create anything secure as an amateur. Systems created by professionals in many cases are broken in a while, so do not even dream of creating a secure device yourself. At least ask a student that specializes in the area. Most people underestimate how smart the attacs on such devices can be. For example look up "differential power analysis" for a way to get keys out of smart cards. Kolja Sulimma
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Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z