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> The device doesn't have to be fast, 8 Mhz for a simple design would be > OK. I need about 40 I/O. You probably won't find such a PLD. Maybe you can implement your solution in software. 8 MHz is quite slow and there are lots of microcontrollers with integrated memory for you to look at. Regards, MarcArticle: 122551
> In the second example, a host C program would write 3 coefficients and > 2 pointers into the SDRAM into the fifo. The custom ip would > effectively > multiply and accumulate the coefficients against the input buffer. > It would write the sum back out to the output buffer. It seems you're looking for IP that does automatic SDRAM read/write access. Some custom ip in fact implements memory access. More often however, the memory access part is separated from the rest of a custom ip. That's what DMA controllers are for. The DMA (direct memory access) controller reads data from memory to an I/O register, where your multiply and accumulate ip accepts it. The DMA controller can also read the result from an I/O register and write it back to memory. Xilinx certainly has DMA controller examples for the FSL bus. Maybe they have even some arithmetic ip core that approximates what you're looking for. Using two such pieces should get you almost home.. Regards, MarcArticle: 122552
"Roger" <enquiries@rwconcepts.co.uk> wrote in message news:46af017d$0$1597$ed2619ec@ptn-nntp-reader02.plus.net... > I'm looking to update a couple of products from VIIPro to V5 devices. Is > there some very rough comparison of the relative logic capabilities of the > 2 FPGA ranges somewhere? TIA, > > Rog. Hi Roger, Have you considered taking the designs you have for your existing products and recompiling them into V5? Then you'll know. HTH., Syms.Article: 122553
Philipp Klaus Krause <pkk@spth.de> writes: > I'm looking a PLD with 5V TTL-compatible I/O that has ~2Mb of integrated > memory that can be used as ROM and ~64Kb of integrated memory that can > be used as EEPROM. The Altera Max-II has 8Kb FLASH memory if that can be of any help: http://altera.com/products/devices/cpld/max2/features/flash/mx2-flash_memory.html Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 122554
On 31 Jul., 11:59, jetm...@hotmail.com wrote: > > In the second example, a host C program would write 3 coefficients and > > 2 pointers into the SDRAM into the fifo. The custom ip would > > effectively > > multiply and accumulate the coefficients against the input buffer. > > It would write the sum back out to the output buffer. > > It seems you're looking for IP that does automatic SDRAM read/write > access. Some custom ip in fact implements memory access. More often > however, the memory access part is separated from the rest of a custom > ip. That's what DMA controllers are for. > > The DMA (direct memory access) controller reads data from memory to an > I/O register, where your multiply and accumulate ip accepts it. The > DMA controller can also read the result from an I/O register and write > it back to memory. > > Xilinx certainly has DMA controller examples for the FSL bus. Maybe > they have even some arithmetic ip core that approximates what you're > looking for. Using two such pieces should get you almost home.. > > Regards, > Marc actually NO - DMA can not be used with FSL bus, as FSL bus is not accessible from the any memory busses in the EDK system. FSL bus is only accessible directly by the CPU using special microblaze instructions, so the transfer to-from FSL must be done by microblaze (not DMA engine) MCH/XCL are "memory busses" based on FSL, but they are mostly used for cache, of course it is possible to design your FSL/MCH ip and connect it to MCH_SDRAM, in that case this FSL IP would have shared access to system SDRAM AnttiArticle: 122555
On 31 Jul., 11:19, Philipp Klaus Krause <p...@spth.de> wrote: > Philipp Klaus Krause schrieb: > > > I'm looking a PLD with 5V TTL-compatible I/O that has ~2Mb of integrated > > memory that can be used as ROM and ~64Kb of integrated memory that can > > be used as EEPROM. > > > Initially I considered using a parallel EPROM, serial EEPROM together > > with lots of TTL, but soon I realized that the EPROM, EEPROM together > > with a 22V10 GAL and a 74573 register would be a simpler solution. > > A few days ago I noticed how cheap CPLDs are today and that one, > > together with a 3.3V voltage regulator could replace the GAL and register. > > > Now I ask myself if there is some PLD that could replace the EEPROM or > > EPROM, too. > > > Philipp > > The device doesn't have to be fast, 8 Mhz for a simple design would be > OK. I need about 40 I/O. > > Philipp the only devices with onchip user flash are Actel Fusion and Lattice XP2 but they are not 5V tolerant. there is and will not be any single chip solution that is 5V tolerant meets your needs. hm, ST has some products based on waferscale stuff, they all include some flash and smallish PLD, but I guess they will not directly match your needs either AnttiArticle: 122556
Antti schrieb: > hm, ST has some products based on waferscale stuff, they all include > some flash and smallish PLD, but I guess they will not directly match > your needs either ST's PSD would do feature-wise, but they seem to be rather expensive. The cheapest I found at digikey is at ~7€, current solution would be ~3€ (XC9536XL: 0.8 €, 2Mb EPROM: 1€, voltage regulator: 0.6€, EEPROM: 0.3€) (all proces per piece when ordering 100). PhilippArticle: 122557
Hi, > the solution is the one suggested by Marc. > Also using Microblaze processor is it possible to define a long long > variable (which is the uint64_t type suggested by Eric). Marc is right but you should use the solution suggested by Eric because that one uses data types established by the C99 standard which makes your code more portable. FranzArticle: 122558
Philipp Klaus Krause wrote: > Philipp Klaus Krause schrieb: > >>I'm looking a PLD with 5V TTL-compatible I/O that has ~2Mb of integrated >>memory that can be used as ROM and ~64Kb of integrated memory that can >>be used as EEPROM. >> >>Initially I considered using a parallel EPROM, serial EEPROM together >>with lots of TTL, but soon I realized that the EPROM, EEPROM together >>with a 22V10 GAL and a 74573 register would be a simpler solution. >>A few days ago I noticed how cheap CPLDs are today and that one, >>together with a 3.3V voltage regulator could replace the GAL and register. Correct. 22V10 + '573 => 32 macrocell CPLD. >> >>Now I ask myself if there is some PLD that could replace the EEPROM or >>EPROM, too. Yes, but not to 2Mb of memory. > The device doesn't have to be fast, 8 Mhz for a simple design would be > OK. I need about 40 I/O. What does this connect to ? - ie where does this ROM code go ? Is there a processor in the system, reading this, or something else ? -jgArticle: 122559
Jim Granville schrieb: >> The device doesn't have to be fast, 8 Mhz for a simple design would be >> OK. I need about 40 I/O. > > What does this connect to ? - ie where does this ROM code go ? > Is there a processor in the system, reading this, or something else ? It goes into a Z80-based system from the 80s. The system has a cartridge port, where D0...D7 (data), A0...A14 (addres bus, A15 missing), E8...EE (chip enable). Back in the 80s a cartridge would contain one to four 64 KBit EPROMS containing a program. Each enable line would be used as a chip enable. I've written a few programs for the system. So far each did fit into 32KB, so I used a 256 KBit EPROM together with a 74LS21 (to connect the four chip enable lines to the EPROM's output and chip enable) for my cartridges. Now I'd like to write a program that uses more ROM and I'd like to be able to save some data. I think dividing the address space into lower 24KB (directly mapped as before) middle 4KB (bank-switched), upper 4KB (to locate some control registers to switch the middle 4KB and control the I²C line to the EEPROM) would make sense. PhilippArticle: 122560
Hi every one,
I had a problem this morning in a functionnal simulation that I finally
traced to the unisim library.
Basically, internally they do :
prcs_clk: process (clk)
begin
if (clk'event) then
clk_wire <= clk;
end if;
end process;
Then, they use clk_wire in their processes and co, to sample the data
that I generated using clk.
I can understand that it fails ... Because clk_wire will toggle 1 delta
after clk and so then the "rising_edges(clk_wire)" will be evaluated,
the value of my FF clocked on clk will already have switched ...
Now, to my _BIG_ surprise, doing
clk_wire <= clk; -- (no process, just an asignement ... )
ALSO fails ... with the same problem. I personnly think it should not,
because an assignement should be like an alias, I don't do
any operation on it so there is no point in making it
"toggle" one delta later ...
I've done a little testbench ( see http://pastebin.com/m133bbae0 , or also
at the end of this post) and that leads to surprising results ...
Any one can enlighten me on _why_ this happens ?
Sylvain
--------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
entity xlx_bug_test is
end xlx_bug_test;
architecture xbt_a of xlx_bug_test is
signal cnt : std_logic_vector(7 downto 0) := x"00";
signal data_me : std_logic_vector(7 downto 0);
signal addr_xlx : std_logic_vector(7 downto 0);
signal sample_data_me1 : std_logic_vector(7 downto 0);
signal sample_addr_me1 : std_logic_vector(7 downto 0);
signal sample_data_me2 : std_logic_vector(7 downto 0);
signal sample_addr_me2 : std_logic_vector(7 downto 0);
signal sample_data_xlx : std_logic_vector(7 downto 0);
signal sample_addr_xlx : std_logic_vector(7 downto 0);
signal clk : std_logic := '0';
signal clk_2_me : std_logic := '0';
signal clk_2_xlx : std_logic;
begin
clk <= not clk after 10 ns;
-- Create a simple counter
---------------------------
process (clk)
begin
if rising_edge(clk) then
cnt <= cnt + 1;
end if;
end process;
-- Sample it two times
------------------------
-- Once 'normally' and say it's the data
process (clk)
begin
if rising_edge(clk) then
data_me <= cnt;
end if;
end process;
-- Once using FD instances and call it address
fdgen: for i in 7 downto 0 generate
fd_i: FD port map (
D => cnt(i),
Q => addr_xlx(i),
C => clk
);
end generate;
-- Assign a clock signal without changing it
---------------------------------------------
-- One way to do it ...
clk_2_me <= clk;
-- The Xilinx (tm) way ...
-- ( $XILINX/vhdl/src/unisims/unisim_VITAL.vhd : 145946 in the RAMB16 model)
prcs_clk: process (clk)
begin
if (clk'event) then
clk_2_xlx <= clk;
end if;
end process;
-- Sampling the data
----------------------
process (clk)
begin
if rising_edge(clk) then
sample_addr_me1 <= addr_xlx;
sample_data_me1 <= data_me;
end if;
end process;
process (clk_2_me)
begin
if rising_edge(clk_2_me) then
sample_addr_me2 <= addr_xlx;
sample_data_me2 <= data_me;
end if;
end process;
process (clk_2_xlx)
begin
if rising_edge(clk_2_xlx) then
sample_addr_xlx <= addr_xlx;
sample_data_xlx <= data_me;
end if;
end process;
end xbt_a;
Article: 122561In news:7dabthsxtl.fsf@www.gratismegler.no timestamped 27 Jul 2007 16:52:54 +0200, Petter Gustad <newsmailcomp6@gustad.com> posted: |---------------------------------------------------------------------| |" Akhil <akhileshpatil@gmail.com> writes: | | | |> I just overheard about a kind of standard lib component F/F, which | |> are used to "smash" X-values at the module level boundary. | | | |X's are your friend. Filter them away and you filter away your bugs. | | | |The place where you want to filter aways X's is when crossing clock | |domains. Here you would like to propagate 0 or 1 to mimic | |metastability flops." | |---------------------------------------------------------------------| Why not use Std_ULogic instead? Why not eradicate every X? Regards, Colin Paul GlosterArticle: 122562
On Jul 31, 7:25 am, Sylvain Munaut <tnt-at-246tNt- dot-...@youknowwhattodo.com> wrote: > Hi every one, > > I had a problem this morning in a functionnal simulation that I finally > traced to the unisim library. > > Basically, internally they do : > > prcs_clk: process (clk) > begin > if (clk'event) then > clk_wire <= clk; > end if; > end process; > > Then, they use clk_wire in their processes and co, to sample the data > that I generated using clk. > I can understand that it fails ... Because clk_wire will toggle 1 delta > after clk and so then the "rising_edges(clk_wire)" will be evaluated, > the value of my FF clocked on clk will already have switched ... > > Now, to my _BIG_ surprise, doing > > clk_wire <= clk; -- (no process, just an asignement ... ) > > ALSO fails ... with the same problem. I personnly think it should not, > because an assignement should be like an alias, I don't do > any operation on it so there is no point in making it > "toggle" one delta later ... > > I've done a little testbench ( seehttp://pastebin.com/m133bbae0, or also > at the end of this post) and that leads to surprising results ... > > Any one can enlighten me on _why_ this happens ? > > Sylvain > > -------------------------------------- > > library ieee; > use ieee.std_logic_1164.all; > use ieee.std_logic_arith.all; > use ieee.std_logic_unsigned.all; > > library unisim; > use unisim.vcomponents.all; > > entity xlx_bug_test is > end xlx_bug_test; > > architecture xbt_a of xlx_bug_test is > > signal cnt : std_logic_vector(7 downto 0) := x"00"; > > signal data_me : std_logic_vector(7 downto 0); > signal addr_xlx : std_logic_vector(7 downto 0); > > signal sample_data_me1 : std_logic_vector(7 downto 0); > signal sample_addr_me1 : std_logic_vector(7 downto 0); > signal sample_data_me2 : std_logic_vector(7 downto 0); > signal sample_addr_me2 : std_logic_vector(7 downto 0); > signal sample_data_xlx : std_logic_vector(7 downto 0); > signal sample_addr_xlx : std_logic_vector(7 downto 0); > > signal clk : std_logic := '0'; > > signal clk_2_me : std_logic := '0'; > signal clk_2_xlx : std_logic; > > begin > > clk <= not clk after 10 ns; > > -- Create a simple counter > --------------------------- > > process (clk) > begin > if rising_edge(clk) then > cnt <= cnt + 1; > end if; > end process; > > -- Sample it two times > ------------------------ > > -- Once 'normally' and say it's the data > process (clk) > begin > if rising_edge(clk) then > data_me <= cnt; > end if; > end process; > > -- Once using FD instances and call it address > fdgen: for i in 7 downto 0 generate > fd_i: FD port map ( > D => cnt(i), > Q => addr_xlx(i), > C => clk > ); > end generate; > > -- Assign a clock signal without changing it > --------------------------------------------- > > -- One way to do it ... > clk_2_me <= clk; > -- The Xilinx (tm) way ... > -- ( $XILINX/vhdl/src/unisims/unisim_VITAL.vhd : 145946 in the RAMB16 model) > prcs_clk: process (clk) > begin > if (clk'event) then > clk_2_xlx <= clk; > end if; > end process; > > -- Sampling the data > ---------------------- > > process (clk) > begin > if rising_edge(clk) then > sample_addr_me1 <= addr_xlx; > sample_data_me1 <= data_me; > end if; > end process; > > process (clk_2_me) > begin > if rising_edge(clk_2_me) then > sample_addr_me2 <= addr_xlx; > sample_data_me2 <= data_me; > end if; > end process; > > process (clk_2_xlx) > begin > if rising_edge(clk_2_xlx) then > sample_addr_xlx <= addr_xlx; > sample_data_xlx <= data_me; > end if; > end process; > > end xbt_a; A concurrent assignment statement (unlike a port assignment), is not like an alias. Concurrent assignment statements are implied processes with a sensitivity list made up of all signals on the RHS of the assignment. So, they would incur a delta delay for the assignment as well. AndyArticle: 122563
Andy wrote:
> On Jul 31, 7:25 am, Sylvain Munaut <tnt-at-246tNt-
> dot-...@youknowwhattodo.com> wrote:
>
>> I had a problem this morning in a functionnal simulation that I finally
>> traced to the unisim library.
>>
>> Basically, internally they do :
>>
>> prcs_clk: process (clk)
>> begin
>> if (clk'event) then
>> clk_wire <= clk;
>> end if;
>> end process;
>>
>> Then, they use clk_wire in their processes and co, to sample the data
>> that I generated using clk.
>> I can understand that it fails ... Because clk_wire will toggle 1 delta
>> after clk and so then the "rising_edges(clk_wire)" will be evaluated,
>> the value of my FF clocked on clk will already have switched ...
>>
>> Now, to my _BIG_ surprise, doing
>>
>> clk_wire <= clk; -- (no process, just an asignement ... )
>>
>> ALSO fails ... with the same problem. I personnly think it should not,
>> because an assignement should be like an alias, I don't do
>> any operation on it so there is no point in making it
>> "toggle" one delta later ...
>>
>> I've done a little testbench ( seehttp://pastebin.com/m133bbae0, or also
>> at the end of this post) and that leads to surprising results ...
>>
>> Any one can enlighten me on _why_ this happens ?
>>
>> Sylvain
>
> A concurrent assignment statement (unlike a port assignment), is not
> like an alias. Concurrent assignment statements are implied processes
> with a sensitivity list made up of all signals on the RHS of the
> assignment. So, they would incur a delta delay for the assignment as
> well.
well, that sucks ...
For normal signals that doesn't matter much but for clock I'd like a
way to force a "zero delta assigment".
Basically at several place I have a "GENERIC" that tells me either to
be synchronous or not. If it's true, all of my block will run at clk_1
and instanciate a synchronous fifo. When it's false, part of the process
are clocked on clk_2 and I instanciate a async FIFO.
Something like :
---- CUT ----
port (
...
...
clk_1 : in std_logic;
clk_1 : in std_logic;
...
);
...
signal clk_i : std_logic;
sync: if SYNC generate
-- Assign clock
clk_i <= clk_1;
-- Synchronous FIFO instance
-- ... (using clk_1 only)
end generate
async: if SYNC generate
-- Assign clock
clk_i <= clk_2;
-- ASynchronous FIFO instance
-- ... (using clk_1 on writeclk and clk_2 on readclk )
end generate
-- Sub Block (either clocked on
my_subblock_i: subblock
port map (
-- The fifo signals
-- ....
clk => clk_i;
...
);
---- END OF CUT ----
But then clk_i is 1 delta too late ... that sucks.
Sylvain
Article: 122564During my work with the XUP development board another problem occured when I tried to use the on-board DDR-SDRAM. A data stream is written into the RAM using the PLB bus and burst mode (16 x 64 bit). When I read the data from the RAM using the Power PC after some time an error occurs. It looks like one 64 bit word has not been written into the RAM (or it has been overwritten - I am not sure about this). When I use the Block RAM of the Virtex-II Pro instead everything is fine. I do not change anything but the address. Same protocol is used for both RAMs. My problem is that I do not have a simulation model for the DDR RAM. It is a Kingston KVR266X64C25/256. All I can do during simulation is to look what the PLB DDR controller is writing to the output pins. And the simulation does not show any wrong behavior at this point. I can not perform any read accesses since there is no RAM model atttached. So currently for tests the only way is to use the real board but here I can not see, what is happening. Does anybody know, where I can get a simulation model for this RAM? I have searched the Kingston page. I have sent them an E-Mail (still waiting for response). I have tried Google but I could not find anything. Same here. Thanks in advance Sebastian GollerArticle: 122565
On Jul 30, 10:36 am, Adam Megacz <meg...@cs.berkeley.edu> wrote: > Just to clear up any confusion here, I am not using the devel trunk. I just found out about your work by your post on geda-user and am interested to know what the "current projects" are you mentioned in the FCCM paper. Are there any slipway parts left? If not I'll be making two, (or more) for geda-user folk, done with gEDA tools and put up on one of my sites and/or yours. WIX looks good too! John Griessen EcosensoryArticle: 122566
Hi All, Please allow me to shamelessly plug my blog. It is relatively new (2-3 months old) and just passed the 5000 views mark. I am blogging about a lot of topics that might interest people here. visit me at: http://asicdigitaldesign.wordpress.com Thanks, NirArticle: 122567
davem wrote: > On 26 Jul, 15:37, Chris Carlen <crcarleRemoveT...@BOGUSsandia.gov> > wrote: >>mk wrote: >> >you should see a window >> >which has SST in its title with a '+' to the left of SST string. >> >>I don't see this! > > My version of GtkWave (3.81) doesn't show the Signal Search Tree (SST) > window by default either. You can bring it up by selecting Signal > Search Tree from the Search menu. Or you can use the shortcut Shift- > Alt-T. Jeez. That's about the one button in the whole program I hadn't pushed. Now I can see waves. Thanks! -- Good day! ________________________________________ Christopher R. Carlen Principal Laser&Electronics Technologist Sandia National Laboratories CA USA crcarleRemoveThis@BOGUSsandia.gov NOTE, delete texts: "RemoveThis" and "BOGUS" from email address to reply.Article: 122568
I just noticed I didn't even mention what Xilinx had to do with that ;) In the BRAM simulation model, they do such a clock assignement : clk_wire <= CLKA; And they do it also for addra, addrb, wea and web. So these also receive a 1 delta delay ... So that makes the read work (kinda, because EN, SSR adn REGCE are not delayed by 1 delta). But the write happen 1 cycle too early. And since some signal receive a delay and some other not, ... that makes the whole thing weird. SylvainArticle: 122569
Sylvain Munaut wrote:
> For normal signals that doesn't matter much but for clock I'd like a
> way to force a "zero delta assigment".
Then don't declare the signal clk_wire.
Just use clk everywhere.
-- Mike Treseler
Article: 122570On Tue, 31 Jul 2007 06:34:54 -0700, sego wrote: > During my work with the XUP development board another problem occured > when I tried to use the on-board DDR-SDRAM. A data stream is written > into the RAM using the PLB bus and burst mode (16 x 64 bit). When I read > the data from the RAM using the Power PC after some time an error > occurs. It looks like one 64 bit word has not been written into the RAM > (or it has been overwritten - I am not sure about this). When I use the > Block RAM of the Virtex-II Pro instead everything is fine. I do not > change anything but the address. Same protocol is used for both RAMs. > > My problem is that I do not have a simulation model for the DDR RAM. It > is a Kingston KVR266X64C25/256. All I can do during simulation is to > look what the PLB DDR controller is writing to the output pins. And the > simulation does not show any wrong behavior at this point. I can not > perform any read accesses since there is no RAM model atttached. So > currently for tests the only way is to use the real board but here I can > not see, what is happening. > Does anybody know, where I can get a simulation model for this RAM? I > have searched the Kingston page. I have sent them an E-Mail (still > waiting for response). I have tried Google but I could not find > anything. Same here. > Thanks in advance > > Sebastian Goller Kingston makes DIMMs not RAMs. You can find RAM models on Micron's website.Article: 122571
Gang I purchased the MicroBlaze Spartan 3E Development Kit. It comes with a copy of the the EDK 8.1 and uses ISE 8.1 Webpack. I would like to load the EDK 9.1 and ISE 9.1 Webpack on my machine. I am running Windows XP with SP2, 2gb of RAM and have 200gb of free hard disk space. 1. Can the version 8 executables coexist with the version 9 executes? 2. Do I have to purchase the 9.1 EDK? BobArticle: 122572
Mike Treseler wrote:
> Sylvain Munaut wrote:
>
>> For normal signals that doesn't matter much but for clock I'd like a
>> way to force a "zero delta assigment".
>
> Then don't declare the signal clk_wire.
> Just use clk everywhere.
>
> -- Mike Treseler
Yes, but I can't do that in every case :
- In one case, this is _inside_ the Xilinx Unisim library ...
- In another case, I want to be able to select one clock or another
depending on a GENERIC.
- Finally in another case I want to export an interface (in a port),
where the sub block exports the clk. like :
port (
video_out_data : out std_logic_vector(24 downto 0);
video_out_en : out std_logic;
video_out_clk : out std_logic;
);
For this case, I can probably solve the issue by making video_out_data and video_out_en first in some internal signals, then assign them to the output port.
For the other cases, that's a whole lot harder ... And I don't find this behavior correct, because it's pretty far from what the real hw do ... IMHO direct assigments (without operation) should be handled as having no delta delay. And maybe force a way to have one (like after 1 delta).
Or _at_least_ offer some way to force a zero delta assignement ....
like clk_1 <0= clk;
...
If you have a solution for my two other use cases, please, tell me ;)
Sylvain
Article: 122573On 31 Jul., 17:07, bob.zi...@gmail.com wrote: > Gang > > I purchased the MicroBlaze Spartan 3E Development Kit. It comes with a > copy of the the EDK 8.1 and > uses ISE 8.1 Webpack. > > I would like to load the EDK 9.1 and ISE 9.1 Webpack on my machine. I > am running Windows XP with SP2, 2gb of RAM and have 200gb of free hard > disk space. > > 1. Can the version 8 executables coexist with the version 9 executes? > 2. Do I have to purchase the 9.1 EDK? > > Bob 1) YES 2) YES AnttiArticle: 122574
On Tue, 31 Jul 2007 16:38:13 +0200, Sylvain Munaut <tnt-at-246tNt-dot-com@youknowwhattodo.com> wrote: >In the BRAM simulation model, they do such a clock assignement : > > clk_wire <= CLKA; > >And they do it also for addra, addrb, wea and web. So these also >receive a 1 delta delay ... > >So that makes the read work (kinda, because EN, SSR adn REGCE are not delayed by 1 delta). >But the write happen 1 cycle too early. >And since some signal receive a delay and some other not, ... that makes the whole thing weird. It's a standard source of unexpected behaviour in zero-delay VHDL models, and one of the very few reasons why I sometimes prefer Verilog for behavioural modelling - you can do zero-delay combinational signal assignment in Verilog. I don't understand what's going on in your Xilinx models. I can't believe they put out code that doesn't work with zero delays. You can be fairly sure it will work correctly when all the non-zero (post place-and-route) delays are backannotated into it. If you're desperate, introduce a tiny non-zero delay in all input signals except the clock, by copying them with a delay: port_signal <= input_signal after 1 ns; But that sucks, doesn't it? -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.
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