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> Not sure I understand your question here. When using the CORDIC as a > sine/cosine generator, you set the scale by the constant you put on the I > input. The CORDIC simply rotates the input vector by the specified > angle. It has a gain of 1.64675. You can get the unscaled sine/cosine by > using 1/1.64675 as the input value, or you can change that to get a > different scaling. Hy Ray, you know with the CORDIC it is possible to start with sinx = 0 and cosx = 1 and at the end simply divide for 1.64675 this in the case that I've at least 13 cordic iterations, this is the solution I don't want to use 'cause I use a bit for +1 and -1 that maybe are used really rarely or nothing. I prefer to start with sinx = 0 and cosx = 1.6475 but in this case the problem is that this is not power of 2 and so I've really much rounding error that propagate. > Instead of trying to visualize it in radians, consider it in fractional > revolutions. The accumulator value is then the fractional part of a > revolution. If you have bits in the accumulator above those whch you take > out as your phase angle, these would represent integer revolutions. what do you mean with fractional revolution, may you better explain it, if possible with a practical example. Thanks ... AntonioArticle: 33876
Hi, After extending the write cycle operation to keep address and data stable when the WE signal gos intactive, the design finally works OK at 9MHz, above, we get 100% which makes me think it a timing problem rather than a PCB layout issue. Steven Steven Derrien wrote: > > Hi, > > We are curently trying to port the XR16/Xsoc project (www.fpgacpu.org) > to a VHDL targeted to the BurchEd Spartan II board > (http://www.burched.com) > > We plan to make our work freely available, but are currently stuck on > a problem. The design is a 16 CPU-SOC which interfaced to a parallel > port. > > We have somes on-chip blockrams which serves as ROM, and off-chip > asynchronous > SRAM whiwh serves as main memory. Our problem is that we get frequent > errors when accessing the off-chip SRAM banks. Generally a single bit > wrong in a 16 bit data word every 200-300 access. > > All simulation (RTL,gate-level,post place and route) went fine. > Right now, our system is clocked at 1Mhz far below its maximum > frequency. > Besides, the SRAM Write Enable command output signal is registered > (although not in a IOB register) to avoid glitches which could cause > wrong write operations. >Article: 33877
Hi Yoram, Mostly unbiassed help is followed by my company ad below :).... There's a list of suppliers of FPGA demo / eval / design boards at http://www.xilinx.com/xlnx/xil_prodcat_product.jsp?title=protoboards_protobo ards_page I would also like to second some links that Dave Van den Bout has already mentioned in this thread: http://www.optimagic.com/boards.html http://www.google.com The lists are often out-of-date very quickly, so using google to search for your requirements may be most effective. A PCI unit that I have used and liked: http://www.insight-electronics.com/solutions/kits/xilinx/spartan-iipci.html My company ad here :)... Burch Electronic Designs sells the B3-SPARTAN2+ kit: - 200,000 gates (XC2S200 device) - works with the free Xilinx WebPACK design software - price: < US$120 ! Great for some serious prototyping, or for education. http://www.burched.com.au/bedspartan2.html for full specs and secure online shop. International orders are very welcome. Best regards Tony Burch Burch Electronic Designs http://www.burched.com.au/ "Yoram Rovner" <yoram@puc.cl> wrote in message news:62ef4351.0108061133.cab3562@posting.google.com... > Hello: > > I need an advice on which fpga board buy. Somebody could tell me which > one has best software, documentation support, etc. > > Thanks > > > Yoram Rovner > yoram@puc.clArticle: 33878
The CIC usually doesn't make sense for such low decimation ratios because you still need to follow it with a compensation and cutoff filter. In the case of your polyphase filter, you'll want to use a polyphase resampler, which is to say it would have 3,4 or 6 branches, each of which decimates by your denominator of the resample ratio. That way, all the filters are running a the decimated rate. Antonio wrote: > I agree on these arguments but my problem is always how to design the > cascade of Polyphase and CIC , now I say a stupid thing, for example > (remember that the interpolation rates I need are 3 , 4, and 6) I can > have a fixed interpolation of 24 with the Polyphase and then decimate > 8 or 6 or 4 with the CIC , but this don't seems to me a good solution > how to have three different polyphase filters or also one with > variable coefficients, do you agree on this ??? > > Bye & Thanks ... > > Antonio D'Ottavio -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.comArticle: 33879
Antonio wrote: > > Not sure I understand your question here. When using the CORDIC as a > > sine/cosine generator, you set the scale by the constant you put on the I > > input. The CORDIC simply rotates the input vector by the specified > > angle. It has a gain of 1.64675. You can get the unscaled sine/cosine by > > using 1/1.64675 as the input value, or you can change that to get a > > different scaling. > > Hy Ray, > you know with the CORDIC it is possible to start with sinx = 0 and > cosx = 1 and at the end simply divide for 1.64675 this in the case > that I've at least 13 cordic iterations, this is the solution I don't > want to use 'cause I use a bit for +1 and -1 that maybe are used > really rarely or nothing. I prefer to start with sinx = 0 and cosx = > 1.6475 but in this case the problem is that this is not power of 2 and > so I've really much rounding error that propagate. You'll get a quantization error in the cordic rotator regardless of whether you use a power of 2 or 1.646 on the cosine input. You can minimize the error by carrying a few extra bits below your intended output LSB internally. For example, if you want a 12 bit output, you might make the rotator 16 bits wide and then take out the 12 MSBs. The truncation error is bounded by roughly log2(iterations)*LSB weight. You'd get a similar truncation error in your post multiply if you do the gain correction afterwards. > > > > Instead of trying to visualize it in radians, consider it in fractional > > revolutions. The accumulator value is then the fractional part of a > > revolution. If you have bits in the accumulator above those whch you take > > out as your phase angle, these would represent integer revolutions. > > what do you mean with fractional revolution, may you better explain > it, if possible with a practical example. The bit weights are such that the msb has a weight of pi, so for example, for a 4 bit field: 0000 = 0 0100 = pi/2 1000 = pi 1100 = 3pi/2 Then if your accumulator increment value is say, 5 you advance the phase angle by 5/16s of a revolution per clock, which is to say 5*pi/8. > > > Thanks ... > > Antonio -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.comArticle: 33880
"Steven Derrien" <sderrien@irisa.fr> wrote in message news:3B6FE4DE.3BAB7CE8@irisa.fr... > After extending the write cycle operation to keep address and > data stable when the WE signal gos intactive, the design finally > works OK at 9MHz, above, we get 100% which makes me think it a timing > problem rather than a PCB layout issue. [Copied to fpga-cpu@yahoogroups.com] You certainly must hold address and data stable while WE/ is deasserted! Here's some background on how XSOC does this, and on the XSOC async SRAM controller in general :- In the original XSOC/xr16 project (www.fpgacpu.org/xsoc/), as described in the article series (www.fpgacpu/xsoc/cc.html and www.fpgacpu.org/papers/xsoc-series-drafts.pdf), we introduce a little complexity in order to run the processor at 1X the XESS XS40 proto board clock rather than 1/2X. The early XESS XS40s (up to and including version 1.2) had a fixed oscillator at 12 MHz. (Newer revisions have a programmable oscillator, up to 100 MHz. More on this below.) One goal was to run the processor at 12 MHz rather than 6 MHz. However, the CPU needs a new 16-bit instruction (two bytes) every cycle, and the XS40 had only a single byte-wide async SRAM. And another goal was to correctly run XSOC/xr16 with a slow (1 Hz) or stopped clock. Therefore, on read cycles, it reads two bytes per cycle. The design synchronously clocks A[N:1] in IOB FFs, but derives A[0] from CLK, and latches D[7:0] in on both rising and falling CLK edges. On write cycles, the design is optimized but still conservative, deriving all write control signal transitions from clock *edges*. A byte write takes 3 clock edges, (2 cycles), and a (two-byte) word write requires 6 edges (3 cycles). With async SRAMs, if you carefully read the data sheets, it is imperative that each write 1. asserts address (and perhaps data), waits (for address to settle) 2. asserts /WE and data, waits (for data to settle) 3. deasserts /WE, while holding address and data asserted and stable As previously discussed here (see http://www.fpga-faq.com/archives/threads_1998_04.html#10076), successfully doing a write in two clock edges is fraught with races and perils. And for the really curious, I have attached an old discussion of this issue, to the end of this message. The memory controller, briefly described in part three of the XSOC articles (see the timing diagram on p.19 and the schematic on p. 24, of www.fpgacpu.org/papers/xsoc-series-drafts.pdf), does this while deriving A[0], /WE, and /OE, with care to be guaranteed glitch-free, from state-machine clocked both on rising and falling edges of CLK. Article #3: "It follows that we need one-half clock to settle the write address, one-half clock to assert /WE, and one-half clock to deassert it." It is easy to see how this detail might have been lost in a rewrite. Now then, later XS40 boards (ver 1.3 and later) have programmable oscillators, and it is now possible to run the clock up at approximately the read latency of the async SRAM. For example, run the clock at 33 MHz, reading a byte every 30 ns, and insert a pipeline stall (wait state) on each 16-bit instruction fetch, effectively running the processor (out of byte-wide external RAM) at 16.7 MHz. To that end, and to add 32-bit long word read/write support, I redesigned MEMCTRL to be a simpler state machine, and now all A[], particularly A[1:0], are clocked on CLK rising edge IOB FFs, although I still use a small pos + neg edge clocked state machine to generate /WE. In this design, byte writes still take three edges (two cycles) and word writes six edges (now four cycles), (and longword writes, eight). [[Otherwise, in a strictly positive edge clocked state machine, byte writes would take three clocks, and word writes six, (and longword writes, 12).]] Sorry, this MEMCTRL revision has not been released. Jan Gray, Gray Research LLC [Disclaimer: these are my opinions -- do you own due diligence.] ------------------------------ Attachment: early XSOC async SRAM write design discussion (view with fixed-pitch font for best results). -----Original Message----- From: JG Sent: Sunday, January 03, 1999 11:34 PM Subject: RE: writing to static RAM > [Someone relates their negative experiences of writing to async SRAM using two clock edges.] Thanks for your comments. I agree. I have reviewed the data sheets of about six different async SRAMs and they all say the same things: 1. address must be valid before WE/ or CE/ is asserted (I'll just say WE/ throughout). 2. data must be valid a certain setup-time before WE/ is deasserted. 3. 0-ns hold times on addr and data after WE/ is deasserted. 4. WE/ must be deasserted for a minimum of 0 ns, but it must be deasserted. Considering my constraints, e.g. 5. address is not available until store instruction's EX stage ENDS. 6. must achieve a fully synchronous, static-ready design. 7. unwilling to do any async delay element tricks, like funny routings of clocks or enables in order to delay WE/ relative to valid addr or to advance deasserting WE/ relative to deasserting valid addr/data. 8. constrained by existing board -- e.g. might be nice if CE/ was driven by external CLK/ but it's not. I see little choice but do a straightforward simple design, e.g. 3 half-cycles to write a byte: 1. assert address, data-in, deassert OE/ 2. assert WE/ for one-half cycle 3. continue to assert address, data-in, deassert OE/ Thus a byte store will require three cycles and a word store will require four. External SRAM word store: Cycle EX(sw) W1 W2 W3 EX' CLK ----____----____----____----____----____ CE/ ________________________________________ A[14:1] <PC....><store.address.........><PC'...> A0 ____----____________------------____---- D[7:0] <I0><I1><store.msb.><store.lsb.><I2><I3> DT ------------____________________-------- OE/ ________------------------------________ WE/ ------------____--------____------------ Notes: 1. The PC and PC' bus transactions are instruction fetches. 2. DT is the external SRAM data-out pins' active-low output enable. DT is held asserted until half-way through W1 to minimize bus contention between the SRAM outputs turning off and the FPGA data outputs turning on. I'd similarly like to deassert DT half-way through W3 but can't because it could deassert data-out before the RAM captures it on the deassertion of WE/. External SRAM byte store: Cycle EX(sb) W1 W2 EX' CLK ----____----____----____----____ CE/ ________________________________ A[14:1] <PC....><store.address.><PC'...> A0 ____----<==============>____---- D[7:0] <I0><I1><store.byte....><I2><I3> DT ------------________------------ OE/ ________----------------________ WE/ ------------____---------------- Notes: 1. In this case we do deassert DT half-way through W2 so the data bus is 3-stated for 1/2 cycle and there is no possible bus contention as W2 ends/EX' begins. That's the plan! Jan.Article: 33883
Could someone please post the URL for Xilinx's free 314-page design and sythesis guide? Thanks.Article: 33884
Hi. I need to interface a XILINX XC95 (using 3.3 volts I/O) CPLD to a PC parallell port. At how high frequency can I expect to transfer data reliabily, and how should the interface to the CPLD be constructed (using 2 or maybe 3.5 meter printer cable)? (I guess some simple RC net to eliminate reflections?) The circuit is intended for a hobby project, and the reason for interfacing the parallell port to a CPLD is to achieve higher rate when pumping serial data through the JTAG port of a SA-1100 CPU. The reason I am not using a FPGA to do the whole thing much better is price and availability (can anyone tell me where to buy a cheap spartanXL in sweden? btw, is this chipset supported by the jtag programmer for xc95, and by webpack?) / Daniel Nilsson, M.Sc.EE studentArticle: 33885
> Also, how long should a piece of string be. Hopefully longer than the cave you are in. :-) -- Standard Disclaimer : 97% speculation 2% bad grammar 1% facts. "Pre-historic Cpu's" http://www.jetnet.ab.ca/users/bfranchuk Now with schematics.Article: 33886
On 7 Aug 2001 04:24:16 -0700, jhmorris47@hotmail.com (Jason) wrote: >What is the best reconfigurable PCI processor board to use as a >computation accelerator? > >Jason Morris Also, how long should a piece of string be. Philip Freidin FliptronicsArticle: 33887
Ahhh, I've been thinking about this. The best design tool-chain is one that has tools that: 1) Don't force you into a GUI 2) Come with complete and useful documentation to explain the various interesting options and switches 3) Don't force you to use a GUI to generate constraints 4) Don't force you to use a GUI to see if you've met timing constraints 5) TELL YOU IF YOU'VE MET TIMING CONSTRAINTS (all of 'em) -- Lattice, are you listening? 6) DON'T FORCE YOU TO USE A CERTAIN ARBITRARY DIRECTORY STRUCTURE. We have reasons for setting up our directory trees the way we do. 7) Must run on any variant of Unix I want -- Solaris and Linux, for starters. And the Unix version must be the same as the Windows version -- none of this, "the unix version will be available next quarter, but the Windows version is available now..." crap. Why Unix? Um, if you have to ask... -andy Jaime Andres Aranguren Cardona wrote: > > Hi, everybody. > > Want to generate opinions, from diverse kind of professionals, about > the Design Tools used for FPGA/CPLD/ASIC designs. > > What is the industry-standard method for design? Is it text based > VHDL/Verilog entry, text based test benches generation and graphical > simulation? Or do professionals prefer alternate ways, such Finite > State Machines (graphical entry), Block Diagrams, Truth Tables and/or > Schematics? > > And what can be considered more "universal" and "standard", between > tools like Xilinx's Foundation and Mentor Graphics' Renoir, ModelSim > and Leonardo Spectrum? > > I expect to generate an instructive discussion topic, invlolving > people from industry and academic spheres. > > Best regards, > > Jaime Andres Aranguren Cardona > jaime.aranguren@ieee.org > jaime.aranguren@computer.orgArticle: 33888
I built the cable with 2 HC125 chips. It works with XC95108-s, 5V supply. The only thing I actually tested was chip identification, I didn't want to mess up these chips. Now I'm trying to use the same cable with Spartan-2 2S200-PQ208 and WebPack JTAG programmer 3.3WP8, and I can't get even the device ID out of it. I tested all 8 combinations of M0...M2 even if spec says 10x should do it. I tried both 5V and 3.3V supply for the cable, HC125 chips work from 2 to 6V and JTAG pins should be 5V-tolerant. The only ID I got out of the chip was 11111111... What other pins could be involved? Could chip be fried? What could be minimum amount of wires going to the chip so I can get JTAG ID response? TIAArticle: 33889
do you offer a job in germany? in those areas??? (sorry my german is very poor) "Kevin Neilson" <kevin_neilson@removethis-yahoo.com> wrote in message news:DlJb7.2677$nb4.179600@newsread1.prod.itd.earthlink.net... > Wo suchen Sie Job-- in Deutschland oder USA? In Amerika es ist jetzt > schwer. Vielleicht suche ich Job in D-land. > > "Buckin" <ipm_grp@freenet.de> wrote in message > news:9kn1mo$5g5d3$1@ID-63439.news.dfncis.de... > > > > Ich bin Hardwareentwickler und suche nach einer Stelle. > > > > Vielleicht kann jemand mir zeigen. > > > > Wo sind im Internet Job WWW für ASIC, FPGA, VHDL. > > > > -- > > Andrew Buckin > > ipm_grp@yahoo.com > > AndrewBuckin@aol.com > > http://www.geocities.com/ipm_grp/ > > > > > > > >Article: 33890
Try www.alibris.com I have found Mick/Brick, Bell/Mudge/McNamara, and others via this site. But they don't have Mead/Conway. Any ideas on that one? "Dave Feustel" <dfeustel1@home.com> wrote in message news:1vFb7.223152$mG4.102162733@news1.mntp1.il.home.com... > Does anyone have a copy of the book listed below that they > > would be willing to sell? > > > > VLSI Chip Design with the Hardware Description Language VERILOG: An Introduction Based on > a Large RISC Processor Design > By Golze, Ulrich (other contributor) > Published by Springer-Verlag New York, Incorporated (February 1996) > ISBN: 3540600329 Number of pages: 358 > Binding: > Weight: 1.57 lbs. Dimensions: 9.53 in. by 6.39 in. by 1.19 in. > > > >Article: 33891
Hi All, I have a design which the Webpack software gives me an error, which requires me to assign a specific input to a GCLK pin. I have reasons why but to be concise, I want to assign it to a normal I/O. How can I force the software to allow it to be routed to the I/O pin I have specified in the UCF file. In the past I have used, assign myroute = dummy ? mypin : 1'bz; where myroute goes to the internal logic from mypin but there must be an easier way. Cheers DaveArticle: 33892
Mark Borgerson <mark@oes.to> wrote in message news:<3B6B17B2.65EC9F15@oes.to>...
> I'm considering one of the smaller CoolRunner CPLDs to replace
> glue logic and a bidirectional buffer in a low-power data logger
> design. Can I easily implement the equivalent of a 74LPT245
> in this device? I looked in the free schematic tool, and the
> '245 was not one of the TTL chips available for inclusion. Is
> this because the chip cannot easily emulate the part? Or do
> I simply have to build it from back-to-back sets of tri-state
> buffers with an invert on one set of output enables?
>
> Secondary question: Now that I've got data sheets and
> software, where do I find development hardware and/or a
> programmer? Eventually, I'll set up for in-system programmming,
> so a JTAG programmer that can be plugged onto my boards
> would be handy.
>
>
> Mark Borgerson
Mark,
I'm a newbie too, but am interested in Coolrunner, having just written an
introductory text book ('Combinational and Sequential Logic') using XPLA
software and Coolrunner target hardware.
Anyway, I think it's much easier to use an HDL to describe your circuit rather
than schematic. The following (written in ABEL) seems to work, using the (free)
Xilnix Webpack development system.
MODULE lpt245
A7..A0 PIN;
B7..B0 PIN;
A = [A7..A0];
B = [B7..B0];
dir PIN;
n_oe PIN;
EQUATIONS
when dir then A = B;
else B = A;
A.oe = dir & !n_oe;
B.oe = !dir & !n_oe;
test_vectors([dir,n_oe,A]->[B]);
[0,0,^b10101010]->[^b10101010];
[0,1,^b10101010]->[.Z.];
test_vectors([dir,n_oe,B]->[A]);
[1,0,^b01010101]->[^b01010101];
[1,1,^b10101010]->[.Z.];
END
If you have Webpack you should find a JTAG programmer within it. Cable is easy
to make up just four resistors needed. Details in book!
Article: 33894For the app notes on using HDLs w/ Xilinx check out: http://support.xilinx.com/apps/hdl.htm My gues is the guide you're looking for is the 'Synthesis and Simulation Design Guide' which can be downloaded from this page (and some examples as well). Regards, Tim Jaynes CAE Dave Feustel wrote: > Could someone please post the URL for Xilinx's free 314-page design and sythesis guide? > > Thanks.Article: 33895
For the app notes on using HDLs w/ Xilinx check out: http://support.xilinx.com/apps/hdl.htm My guess is the guide you're looking for is the 'Synthesis and Simulation Design Guide' which can be downloaded from this page (and some examples as well). Regards, Tim Jaynes CAE Dave Feustel wrote: > Could someone please post the URL for Xilinx's free 314-page design and sythesis guide? > > Thanks.Article: 33896
--------------A0C91423C489C11EC31DBA7F Content-Type: text/plain; charset=us-ascii; x-mac-type="54455854"; x-mac-creator="4D4F5353" Content-Transfer-Encoding: 7bit download it from http://support.xilinx.com/support/sw_manuals/2_1i/download/gensim.pdf Peter Alfke, Xilinx Applications Dave Feustel wrote: > Could someone please post the URL for Xilinx's free 314-page design and sythesis guide? > > Thanks. --------------A0C91423C489C11EC31DBA7F Content-Type: text/html; charset=us-ascii Content-Transfer-Encoding: 7bit <!doctype html public "-//w3c//dtd html 4.0 transitional//en"> <html> download it from <p><u><A HREF="http://support.xilinx.com/support/sw_manuals/2_1i/download/gensim.pdf">http://support.xilinx.com/support/sw_manuals/2_1i/download/gensim.pdf</A></u> <p>Peter Alfke, Xilinx Applications <p>Dave Feustel wrote: <blockquote TYPE=CITE>Could someone please post the URL for Xilinx's free 314-page design and sythesis guide? <p>Thanks.</blockquote> </html> --------------A0C91423C489C11EC31DBA7F--Article: 33897
--------------45103A94AB492D6A4F3FA070 Content-Type: text/plain; charset=us-ascii; x-mac-type="54455854"; x-mac-creator="4D4F5353" Content-Transfer-Encoding: 7bit download it from http://support.xilinx.com/support/sw_manuals/2_1i/download/gensim.pdf or http://www.xilinx.com/support/sw_manuals/2_1i/download/xsisyn.pdf Peter Alfke, Xilinx Applications Dave Feustel wrote: > Could someone please post the URL for Xilinx's free 314-page design and sythesis guide? > > Thanks. --------------45103A94AB492D6A4F3FA070 Content-Type: text/html; charset=us-ascii Content-Transfer-Encoding: 7bit <!doctype html public "-//w3c//dtd html 4.0 transitional//en"> <html> download it from <p><a href="http://support.xilinx.com/support/sw_manuals/2_1i/download/gensim.pdf">http://support.xilinx.com/support/sw_manuals/2_1i/download/gensim.pdf</a><a href="http://support.xilinx.com/support/sw_manuals/2_1i/download/gensim.pdf"></a> <p><a href="http://support.xilinx.com/support/sw_manuals/2_1i/download/gensim.pdf">or</a><a href="http://support.xilinx.com/support/sw_manuals/2_1i/download/gensim.pdf"></a> <p><a href="http://support.xilinx.com/support/sw_manuals/2_1i/download/gensim.pdf">http://www.xilinx.com/support/sw_manuals/2_1i/download/xsisyn.pdf</a> <p>Peter Alfke, Xilinx Applications <p>Dave Feustel wrote: <blockquote TYPE=CITE>Could someone please post the URL for Xilinx's free 314-page design and sythesis guide? <p>Thanks.</blockquote> </html> --------------45103A94AB492D6A4F3FA070--Article: 33898
Sadly, No Joy. "Tim" <tim@rockylogic.com.nospam.com> wrote in message news:997213083.16623.0.nnrp-08.9e9832fa@news.demon.co.uk... > Try www.alibris.com > > I have found Mick/Brick, Bell/Mudge/McNamara, and others via this site. > > But they don't have Mead/Conway. Any ideas on that one? > > > "Dave Feustel" <dfeustel1@home.com> wrote in message > news:1vFb7.223152$mG4.102162733@news1.mntp1.il.home.com... > > Does anyone have a copy of the book listed below that they > > > > would be willing to sell? > > > > > > > > VLSI Chip Design with the Hardware Description Language VERILOG: An > Introduction Based on > > a Large RISC Processor Design > > By Golze, Ulrich (other contributor) > > Published by Springer-Verlag New York, Incorporated (February 1996) > > ISBN: 3540600329 Number of pages: 358 > > Binding: > > Weight: 1.57 lbs. Dimensions: 9.53 in. by 6.39 in. by 1.19 in. > > > > > > > > > >Article: 33899
Thanks Peter! I'm finally, with help from Tony at Burched and a few others, within sight of downloading and testing my first FPGA. FPGA development is a *lot* more complicated than any software development I've ever done! But learning how to do it's going to be worth the effort "Peter Alfke" <peter.alfke@xilinx.com> wrote in message news:3B707711.30083FB4@xilinx.com... download it from http://support.xilinx.com/support/sw_manuals/2_1i/download/gensim.pdf Peter Alfke, Xilinx Applications Dave Feustel wrote: Could someone please post the URL for Xilinx's free 314-page design and sythesis guide? Thanks.
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