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Yoram, > I need an advice on which fpga board buy. Somebody could tell > me which one has best software, documentation support, etc. we just introduced our new FPGA development board. It provides a 200k gate Spartan-II FPGA, Flash PROM for configuration, some buttons & lights, and a very flexible expansion concept. Please refer to http://www.trenz-electronic.de/news/newsen.htm for a complete product specification. If you have further questions, please do not hesitate to contact me. Best regards Felix _____ Dipl.-Ing. Felix Bertram Trenz Electronic Duenner Kirchweg 77 D - 32257 Buende Tel.: +49 (0) 5223 4939755 Fax.: +49 (0) 5223 48945 Mailto:f.bertram@trenz-electronic.de http://www.trenz-electronic.deArticle: 33926
"Andy Peters > Ahhh, I've been thinking about this. > > The best design tool-chain is one that has tools that: > > 1) Don't force you into a GUI > 2) Come with complete and useful documentation to explain the various > interesting options and switches > 3) Don't force you to use a GUI to generate constraints > 4) Don't force you to use a GUI to see if you've met timing constraints > 5) TELL YOU IF YOU'VE MET TIMING CONSTRAINTS (all of 'em) -- Lattice, > are you listening? > 6) DON'T FORCE YOU TO USE A CERTAIN ARBITRARY DIRECTORY STRUCTURE. We > have reasons for setting up our directory trees the way we do. > 7) Must run on any variant of Unix I want -- Solaris and Linux, for > starters. And the Unix version must be the same as the Windows version > -- none of this, "the unix version will be available next quarter, but > the Windows version is available now..." crap. Why Unix? Um, if you > have to ask... > 7A) And the Unix version should not cost 4x the price of the Windows one. With the advent of Linux there is NO EXCUSE WHATSOEVER for this marketing rip-off to continue. ModelSim/Mentor please note - if you want me to pay for the extra speed/functionality of the SE edition o.k. but don't force me to spend the dosh just to get Linux.Article: 33927
Could it be using the LUT just for routing? "Pascal Merkel" <pascal.merkel@stud.uni-karlsruhe.de> wrote in message news:3B682B4C.C799FCDE@stud.uni-karlsruhe.de... > HI all, > > I have a design which consists of a data-path and a controller. Some > controller signals drive two components of the data-path. During > synthesis (Synopsys Design Comp.) such signals are divided in two > seperate signals whereby always one of the both gets two inverters. > During Mapping with XactM3.1 one of these inverters is removed because > of being redundant. The other is mapped into a LUT, but this LUT don't > invert, that's clear. But why all this is done? Does such a LUT act as a > buffer or is it unnecessary? > > PascalArticle: 33928
I think you just need a PCI card that is hardcoded to respond to I/O address 80...it shouldn't matter if it's the card is PCI or ISA... Basically, this card doesn't go through any PCI config stuff...nor does it respond to IDSEL... Just a guess ;-) "Entwicklung" <entw@madex.com> wrote in message news:3B711BD4.D0A8F7E3@madex.com... > Hi All, > i'm looking for a Description how i can build a Display Card for showing > the Postcode from Bios on the PCI Bus. > The Card must look for an I/O Write Access on Adress 80H and then > display's the data on 2 7seg Display's as HEX. > Thank You for any Idea. > > -- > MfG > W. Philippi > Madex Electronic Components GmbH > >Article: 33929
I *really* gave up designing my own hardware when SMD devices started showing up on PCBs. I can barely distinguish the separate wires coming off the chip. Soldering them myself is impossible. "Andy Peters <andy [@] exponentmedia com >" <".> wrote in message news:MCec7.378$Fc7.25894@newsread2.prod.itd.earthlink.net... > Dave Feustel wrote: > > > > Thanks Peter! > > > > I'm finally, with help from Tony at Burched and a few others, within sight of downloading > > and testing my first FPGA. FPGA development is a *lot* more complicated > > than any software development I've ever done! > > > > But learning how to do it's going to be worth the effort > > You can make it even more complicated by designing the board the FPGA > solders onto! > > -andyArticle: 33930
What do val/starter boards with the A7 chip on them cost?
"Steven K. Knapp" <sknapp@triscend.com> wrote in message
news:d2f86928.0108080942.63f3b64b@posting.google.com...
> To the "diffused processor" camp, be sure to look at the Triscend
> Configurable System-on-Chip (CSoC) devices, which unlike the others
> mentioned, are actually shipping today.
>
> Triscend E5 CSoC (Embedded Applications)
> ========================================
> Accelerated 8051 8-bit microcontroller, 2-channel DMA, 8K to 64K
> on-chip RAM, 3K to 40K gates of programmable logic.
> http://www.triscend.com/products/indexe5.html
>
> Triscend A7 CSoC (Embedded Processing Applications)
> ===================================================
> ARM7TDMI 32-bit RISC CPU, 4-channel DMA, Flash and SDRAM controller,
> 8K cache, 16K on-chip RAM, 5K to 40K gates of programmable logic.
> http://www.triscend.com/products/indexa7.html
>
> "rodger" <rodger@bit.bucket> wrote in message
news:<aQac7.133$T3.191081984@news.frii.net>...
> > Have you taken a look at Xilinx' new MicroBlaze processor?
> >
> > http://www.xilinx.com/ipcenter/processor_central/microblaze.htm
> >
> > The other possibilities are the diffused processors such as
> > the PowerPC in Xilinx and ARM9 in Altera.
> >
> > http://www.xilinx.com/xlnx/xil_prodcat_landingpage.jsp?title=Processor+Centr
> > al
> >
> > "Jason Stratos Papadopoulos" <jasonp@y.glue.umd.edu> wrote in message
> > news:9jnstk$4lo$1@hecate.umd.edu...
> > > From: Jason Stratos Papadopoulos <jasonp@y.glue.umd.edu>
> > > Subject: prospects for a tiny FPGA supercomputer?
> > > Newsgroups: comp.arch.fpga
> > > Organization:
> > > Summary:
> > > Keywords:
> > > User-Agent: tin/1.4.2-20000205 ("Possession") (UNIX) (SunOS/5.7 (sun4u))
> > >
> > > Hello. Please pardon the following stack of ignorant questions from a
> > > software weenie. I know a little about hardware and a little more about
> > > computer architecture (picked up on the job).
> > >
> > > I was amazed when I found out about these guys, who apparently built
> > > their own little (integer only) vector processor which they intended
> > > to use for fixed point neural net training.
> > >
> > > http://www.icsi.berkeley.edu/real/spert/t0-intro.html
> > >
> > > This is a chip with a simple processor core, and 16 enormous vector
> > > registers (32 x 32-bit words each). The vector registers fed 8 words
> > > at a time to one of two clusters of 8 pipelined functional units each,
> > > and the chip had eight 16-bit integer multipliers. The PhD students on
> > > this project got HP to implement it in about 750,000 gates (1995
> > > technology), and it beat the pants off the expensive workstations of the
> > > day at the specialized tasks the chip was designed for.
> > >
> > > I was wondering if it would be possible to pack a 64-bit version of this
> > > kind of vector processor into latter-day programmable logic; specifically
> > > something with a group of 64-bit ALUs that could do adds, subtracts and
> > > 64 x 64 bit pipelined integer multiplies as fast as possible. A beast like
> > > this would be very useful for the very large integer convolutions I
> > > continually find myself doing, and for which conventional general-purpose
> > > processors are way too slow for my taste.
> > >
> > > If by some chance this is feasible, I've further deluded myself into
> > > believing that with enough patience I can actually design such a thing in
> > > my spare time and on a modest budget (say, a few thousand dollars), and
> > > maybe put it onto a PCB with some fast SRAM memory. Presto, a pygmy super-
> > > computer.
> > >
> > > Am I completely nuts here? Are there low-cost tools that can do a
> > > synthesis and/or place and route for what even to me sounds like a pretty
> > > ambitious design? What about tutorials on Verilog/VHDL? Finally, are there
> > > IP cores for little processors like an ARM7 or older MIPS that would fit
> > > into a big FPGA? What about processor cores that have a big blob of
> > > programmable logic on-chip and tons of I/O?
> > >
> > > Thanks in advance for any help (or talking me out of this),
> > > jasonp
> > >
> > > PS: Hi Keith!
Article: 33931The lut wouldn't be inserted for routing by the synthesis. That happens in PAR. The synthesis may be using it to duplicate a signal to reduce loading. Check your fanout limit. It could also be there for connectivity if the output feeds carry chain primitives. Austin Franklin wrote: > Could it be using the LUT just for routing? > > "Pascal Merkel" <pascal.merkel@stud.uni-karlsruhe.de> wrote in message > news:3B682B4C.C799FCDE@stud.uni-karlsruhe.de... > > HI all, > > > > I have a design which consists of a data-path and a controller. Some > > controller signals drive two components of the data-path. During > > synthesis (Synopsys Design Comp.) such signals are divided in two > > seperate signals whereby always one of the both gets two inverters. > > During Mapping with XactM3.1 one of these inverters is removed because > > of being redundant. The other is mapped into a LUT, but this LUT don't > > invert, that's clear. But why all this is done? Does such a LUT act as a > > buffer or is it unnecessary? > > > > Pascal -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.comArticle: 33932
... > There are simple drivers around which allow the access to > specified I/O locations, eliminating the SW Trap. > (I think one is called DIRECTIO). ... There's another driver, which is free from SSTNET. It's called DriverLINX Port I/O Driver. It works with Win 95, 98, 2000, ME and NT. Look under Windows 95/NT Port I/O Driver, at http://www.sstnet.com/DownLoad/dnload.htm?ID=997315163940 > Falser Klaus > R&D Electronics Department > Company : Durst Phototechnik AG > Vittorio Veneto Str. 59 > I-39042 Brixen > Voice : +0472/810235 > : +0472/810111 > FAX : +0472/830980 > Email : kfalser@IHATESPAMdurst.it Best regards Tony Burch http://www.BurchED.com.au Lowest cost, easy-to-use FPGA prototyping kits!Article: 33933
Howdy, I am wondering if it is possible to generate constants with a function. What I basically want to do is generate a bunch of fixed bit masks. They are all different, but it was easy to write a function to generate them. However, I am not sure how to indicate to a synthesis tool (currently Foundation Express, but probably soon Synplicity) that it should hardcode the result of function, rather than implement the algorithm used to generate it. The alternative of entering the values by hand into a constant works, but there are 256 of them. Any other suggestions for something like this? -- My real email is akamail.com@dclark (or something like that).Article: 33934
The OS:es it will be used with are WIN98 & Linux... will there be problems using I/O drivers if I use a mode other than the "ordinary" (data-lines for data and standard protocol) of the parallell-port? "Tony Burch" <tony@BurchED.com.au> skrev i meddelandet news:3b71d592$1@news1.idx.com.au... > ... > > There are simple drivers around which allow the access to > > specified I/O locations, eliminating the SW Trap. > > (I think one is called DIRECTIO). > ... > There's another driver, which is free from SSTNET. It's > called DriverLINX Port I/O Driver. It works with > Win 95, 98, 2000, ME and NT. Look under > Windows 95/NT Port I/O Driver, at > http://www.sstnet.com/DownLoad/dnload.htm?ID=997315163940 > > > Falser Klaus > > R&D Electronics Department > > Company : Durst Phototechnik AG > > Vittorio Veneto Str. 59 > > I-39042 Brixen > > Voice : +0472/810235 > > : +0472/810111 > > FAX : +0472/830980 > > Email : kfalser@IHATESPAMdurst.it > > Best regards > Tony Burch > http://www.BurchED.com.au > Lowest cost, easy-to-use > FPGA prototyping kits! > > >Article: 33935
There are currently two A7 development boards in production.
The Triscend A7 Starter Kit has a list price of US$3,995 and includes
the Triscend FastChip software, a WindRiver visionPROBE II JTAG
debuggger/emulator, the A7 development board with an A7 and SDRAM. As
with most development kits, you can sweet talk your local salesperson
into evaluating one if the opportunity is right.
http://www.triscend.com/products/Textdeva7.html#A7StartKit
Embedded Performance also offers their DEV-A7 board which comes with
32MB of SDRAM and 8 MB of Flash and a 10Base-T Ethernet connection.
The DEV-A7 board has a list price of US$1,995.
http://www.embeddedperformance.com/products/arm/hardware/dev-a7_board.shtml
For the E5 family, there are a variety of boards, priced anywhere from
US$170 up to $795.
myCSoC Kit ($170)
http://www.xess.com/prod022.php3
iKit2000 ($695)
http://www.ikit2000.com
Triscend E5 Starter Kit ($795)
http://www.triscend.com/products/indexdeve5.html
http://www.triscend.com/products/indexdevelopmentboard.html
"Dave Feustel" <dfeustel1@home.com> wrote in message news:<4ijc7.228343$mG4.105081018@news1.mntp1.il.home.com>...
> What do val/starter boards with the A7 chip on them cost?
>
> "Steven K. Knapp" <sknapp@triscend.com> wrote in message
> news:d2f86928.0108080942.63f3b64b@posting.google.com...
> > To the "diffused processor" camp, be sure to look at the Triscend
> > Configurable System-on-Chip (CSoC) devices, which unlike the others
> > mentioned, are actually shipping today.
> >
> > Triscend E5 CSoC (Embedded Applications)
> > ========================================
> > Accelerated 8051 8-bit microcontroller, 2-channel DMA, 8K to 64K
> > on-chip RAM, 3K to 40K gates of programmable logic.
> > http://www.triscend.com/products/indexe5.html
> >
> > Triscend A7 CSoC (Embedded Processing Applications)
> > ===================================================
> > ARM7TDMI 32-bit RISC CPU, 4-channel DMA, Flash and SDRAM controller,
> > 8K cache, 16K on-chip RAM, 5K to 40K gates of programmable logic.
> > http://www.triscend.com/products/indexa7.html
> >
> > "rodger" <rodger@bit.bucket> wrote in message
> news:<aQac7.133$T3.191081984@news.frii.net>...
> > > Have you taken a look at Xilinx' new MicroBlaze processor?
> > >
> > > http://www.xilinx.com/ipcenter/processor_central/microblaze.htm
> > >
> > > The other possibilities are the diffused processors such as
> > > the PowerPC in Xilinx and ARM9 in Altera.
> > >
> > > http://www.xilinx.com/xlnx/xil_prodcat_landingpage.jsp?title=Processor+Centr
> > > al
> > >
> > > "Jason Stratos Papadopoulos" <jasonp@y.glue.umd.edu> wrote in message
> > > news:9jnstk$4lo$1@hecate.umd.edu...
> > > > From: Jason Stratos Papadopoulos <jasonp@y.glue.umd.edu>
> > > > Subject: prospects for a tiny FPGA supercomputer?
> > > > Newsgroups: comp.arch.fpga
> > > > Organization:
> > > > Summary:
> > > > Keywords:
> > > > User-Agent: tin/1.4.2-20000205 ("Possession") (UNIX) (SunOS/5.7 (sun4u))
> > > >
> > > > Hello. Please pardon the following stack of ignorant questions from a
> > > > software weenie. I know a little about hardware and a little more about
> > > > computer architecture (picked up on the job).
> > > >
> > > > I was amazed when I found out about these guys, who apparently built
> > > > their own little (integer only) vector processor which they intended
> > > > to use for fixed point neural net training.
> > > >
> > > > http://www.icsi.berkeley.edu/real/spert/t0-intro.html
> > > >
> > > > This is a chip with a simple processor core, and 16 enormous vector
> > > > registers (32 x 32-bit words each). The vector registers fed 8 words
> > > > at a time to one of two clusters of 8 pipelined functional units each,
> > > > and the chip had eight 16-bit integer multipliers. The PhD students on
> > > > this project got HP to implement it in about 750,000 gates (1995
> > > > technology), and it beat the pants off the expensive workstations of the
> > > > day at the specialized tasks the chip was designed for.
> > > >
> > > > I was wondering if it would be possible to pack a 64-bit version of this
> > > > kind of vector processor into latter-day programmable logic; specifically
> > > > something with a group of 64-bit ALUs that could do adds, subtracts and
> > > > 64 x 64 bit pipelined integer multiplies as fast as possible. A beast like
> > > > this would be very useful for the very large integer convolutions I
> > > > continually find myself doing, and for which conventional general-purpose
> > > > processors are way too slow for my taste.
> > > >
> > > > If by some chance this is feasible, I've further deluded myself into
> > > > believing that with enough patience I can actually design such a thing in
> > > > my spare time and on a modest budget (say, a few thousand dollars), and
> > > > maybe put it onto a PCB with some fast SRAM memory. Presto, a pygmy super-
> > > > computer.
> > > >
> > > > Am I completely nuts here? Are there low-cost tools that can do a
> > > > synthesis and/or place and route for what even to me sounds like a pretty
> > > > ambitious design? What about tutorials on Verilog/VHDL? Finally, are there
> > > > IP cores for little processors like an ARM7 or older MIPS that would fit
> > > > into a big FPGA? What about processor cores that have a big blob of
> > > > programmable logic on-chip and tons of I/O?
> > > >
> > > > Thanks in advance for any help (or talking me out of this),
> > > > jasonp
> > > >
> > > > PS: Hi Keith!
Article: 33936
I think you are looking for these products.
https://www.jameco.com/cgi-bin/ncommerce3/ProductDisplay?prmenbr=91&prrfnbr=3539&cgrfnbr=827&ctgys=504;542;827;
https://www.jameco.com/cgi-bin/ncommerce3/ProductDisplay?prmenbr=91&prrfnbr=3816&cgrfnbr=827&ctgys=504;542;827;
I don't know who made these products, but if you look around, someone
else might carry the same product for less (usually Jameco prices are
not that cheap, and are often inflated).
Note that I am not paid by Jameco to put up those two links.
If you insist on building a PCI card that displays the
postcodes, I think it will cost much more than those two cards I
mentioned above, and it will take lots of time to develop it.
I think you are the same person who posted the same question on July
26th, 2001 (Title: PCI-Interface), and some people mentioned that you
should use a PCI-to-Local Bus Bridge from PLX.
Although I haven't read the datasheet of those PLX bridge chips, my
guess is that I doubt that the PLX made bridge chip will allow the
user to hardwire the I/O port to 80H.
So, you may have to use some kind of a CPLD or an FPGA to implement
this PCI postcode card where you have more design freedom.
You also mentioned that the board has to work instantly when powered
up, so I guess an SRAM-based FPGAs will not do the job (otherwise,
$145 Insight Electronics Spartan II PCI development board
(http://www.insight-electronics.com/solutions/kits/xilinx/spartan-iipci.html)
with a custom made daughter card that has the Hex LED should do the
job).
So, you will likely have to use an antifuse FPGA (Actel and
Quicklogic) or an electrically erasable CPLD (Altera, Lattice, Xilinx,
and Cypress).
A CPLD will likely be cheaper than antifuse FPGA in terms of cost
since a CPLD can be modified it many times whereas an antifuse FPGA
can be programmed once.
Among the CPLDs, I personally don't recommend Cypress CPLD because
their software is junk compared to free tools from Xilinx.
I bought Cypress Warp 2 development kit back in 1999 for $250
(development board + Warp 2 software + printed manuals), but after I
started using Xilinx's free WebPack ISE tools, I now realize that I
just wasted my memory on Cypress' stuff that I will never use.
I will say that go with a vendor that offers free tools because even
if you don't like the tools, you don't lose anything (like I did with
Cypress Warp 2), but I do also realize that the CPLD you are going to
use has to fit your PCI interface, and has to be able to meet PCI's
electrical requirements.
After you decide the device you are going to use, the first
thing you should do is to order a copy of the PCI Local Bus
Specification Revision 2.2 from PCISIG (http://www.pcisig.com).
The specification + overseas shipping should cost you something around
$50.
If you are totally clueless about PCI, you may want to order PCI
System Architecture 4th Edition by Tom Shanley and Don Anderson (ISBN:
0-201-30974-2) which costs $39.95, and is written for beginners.
Although some people like this book, I personally don't like PCI
Hardware & Software (ISBN: 092939259-0) by Ed Solari and George Willse
which costs around $100 because the book is hard to understand (too
much detail) and figures in the book look really terrible compared to
PCI specification or PCI System Architecture.
I will say that PCI specification is a lot easier to read and
understand than PCI Hardware & Software.
I guess the hard part of developing a PCI interface will be
how to develop an FSM (Finite State Machine).
Appendix B of the PCI specification shows you an example of an FSM,
but it is probably better to modify it because I personally don't like
the way it is organized.
One thing that has to be met is how to fix the I/O address to
80H.
According to Appendix G of the PCI specification, only a legacy device
(VGA compatible card, IDE card, etc.) can fix its memory and I/O
location to certain address to maintain compatibility with PC
software.
So, taking advantage of this exception of the specification, since the
PCI postcode card is a legacy device, you can use I/O address 80H
(actually 00000080H) without implementing BARs (Base Address
Registers, Configuration Register 10H through 24H) which usually have
to be programmable.
When designing the PCI FSM, you will use FRAME# = L, IRDY# = H,
C/BE#[3::1] = 001B (ignore C/BE#[0] which tell you if the cycle is
read (0) or write (1)), and AD[31::0] = 00000080H as the condition to
transition from idle cycle to the cycle where DEVSEL# gets asserted.
Although I will assume that the I/O port 80H is write only, even if
the someone tries to read from the PCI postcode card, you should still
respond to that cycle (don't let the master do a Master-Abort
Termination), and return the content of the current postcode or 0FFH.
Even though it might seem like implementing Configuration
Cycle is not needed, it is a requirement according to the PCI standard
to implement it.
However, because it is a legacy device, you don't have to implement
BAR (Base Address Register, Configuration Register 10H through 24H).
Most Configuration Registers can be hardwired to zero (except some of
them like Vendor ID, Device ID, Class Code, etc.).
Although all PCI devices are suppose to implement a parity
checker, I don't think it is that important to implement it, so you
can omit that, but you are still required to implement a parity
generator for read cycle.
Regards,
Kevin Brace (don't respond to me directly, respond within the
newsgroup)
Entwicklung <entw@madex.com> wrote in message news:<3B711BD4.D0A8F7E3@madex.com>...
> Hi All,
> i'm looking for a Description how i can build a Display Card for showing
> the Postcode from Bios on the PCI Bus.
> The Card must look for an I/O Write Access on Adress 80H and then
> display's the data on 2 7seg Display's as HEX.
> Thank You for any Idea.
Article: 33937<!doctype html public "-//w3c//dtd html 4.0 transitional//en"> <html> Dear recruiting team, <p>- you are looking for a highly-motivated digital <br> design/systems/CAD engineer? <br>- you need an engineer who is fascinated of computer <br> technology, especially parallel/vector architectures, <br> System-On-a-Chip and high-speed datacommunications? <br>- you ask for an employee who's motivation to study <br> electrical engineering was generated by Seymour Cray <br> and his machines? <br>- you are searching for a creative mind combined with <br> strong problem solving capabilities? <br>- you want a new member for your team, who is committed <br> to excellence and success? <br>- you desire an open-minded person who is programmed to <br> reach the goal, increasing your efficiency and <br> pushing the limits? <br>Try this..... <p>=> <A HREF="http://www.asic.cc">http://www.asic.cc</A> <p>Best regards, <p>Andreas Schmidt <p>P.S.: Everything is possible, if you really want it...</html>Article: 33938
If they are constant (ie not dependent on a signal) then they should get
hardcoded as a constant. Another alternative to writing a function would be
to use a generate statement and assign a local constant a computed value
based on the for...generate index. I do this frequently for generating RLOCs
for placing xilinx primitives.
FOO:for i in 1 to 20 generate
constant bar:std_logic_vector(9 downto
0):=std_logic_vector(to_unsigned(i*i,10));
constant rloc_string:string:="R" & itoa(9-i/2) & "C0.S1";
attribute RLOC of U1:label is rloc_string;
begin
U1:...
Duane Clark wrote:
> Howdy,
>
> I am wondering if it is possible to generate constants with a function.
> What I basically want to do is generate a bunch of fixed bit masks. They
> are all different, but it was easy to write a function to generate them.
> However, I am not sure how to indicate to a synthesis tool (currently
> Foundation Express, but probably soon Synplicity) that it should
> hardcode the result of function, rather than implement the algorithm
> used to generate it.
>
> The alternative of entering the values by hand into a constant works,
> but there are 256 of them. Any other suggestions for something like this?
>
> --
> My real email is akamail.com@dclark (or something like that).
--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
Article: 33939I believe he said "during mapping" not during synthesis. I assumed by that he meant it was post-route that he observed that happen...since I can't imagine anyone taking the time to look manually through the text output of the other tools...but who knows. "Ray Andraka" <ray@andraka.com> wrote in message news:3B71C73B.AB1B1365@andraka.com... > The lut wouldn't be inserted for routing by the synthesis. That happens in > PAR. The synthesis may be using it to duplicate a signal to reduce loading. > Check your fanout limit. It could also be there for connectivity if the > output feeds carry chain primitives. > > Austin Franklin wrote: > > > Could it be using the LUT just for routing? > > > > "Pascal Merkel" <pascal.merkel@stud.uni-karlsruhe.de> wrote in message > > news:3B682B4C.C799FCDE@stud.uni-karlsruhe.de... > > > HI all, > > > > > > I have a design which consists of a data-path and a controller. Some > > > controller signals drive two components of the data-path. During > > > synthesis (Synopsys Design Comp.) such signals are divided in two > > > seperate signals whereby always one of the both gets two inverters. > > > During Mapping with XactM3.1 one of these inverters is removed because > > > of being redundant. The other is mapped into a LUT, but this LUT don't > > > invert, that's clear. But why all this is done? Does such a LUT act as a > > > buffer or is it unnecessary? > > > > > > Pascal > > -- > -Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com > >Article: 33940
Ray Andraka <ray@andraka.com> wrote in message news:<3B6FF9B2.78B90B90@andraka.com>... > You'll get a quantization error in the cordic rotator regardless of whether you > use a power of 2 or 1.646 on the cosine input. You can minimize the error by > carrying a few extra bits below your intended output LSB internally. For > example, if you want a 12 bit output, you might make the rotator 16 bits wide > and then take out the 12 MSBs. The truncation error is bounded by roughly > log2(iterations)*LSB weight. You'd get a similar truncation error in your post > multiply if you do the gain correction afterwards. So definitively you suggest me to start with cosx = 1/1.64675 and to use 12 bit for fractional part and one bit for the sign, and no bits for the integer part, to earn a bit in this point is not so important for your perspective ?? > > > Instead of trying to visualize it in radians, consider it in fractional > > > revolutions. The accumulator value is then the fractional part of a > > > revolution. If you have bits in the accumulator above those whch you take > > > out as your phase angle, these would represent integer revolutions. > > > > what do you mean with fractional revolution, may you better explain > > it, if possible with a practical example. > > The bit weights are such that the msb has a weight of pi, so for example, for a > 4 bit field: > 0000 = 0 > 0100 = pi/2 > 1000 = pi > 1100 = 3pi/2 > > Then if your accumulator increment value is say, 5 you advance the phase angle > by 5/16s of a revolution per clock, which is to say 5*pi/8. I'm now using the following Matlab code to produce the word I've to put in the frequency word of the accumulator : clear all ; close all ; clc ; f_clk = 165e6 ; f_out = 40e6 ; n_bit_acc = 32 ; n_bit_cordic = 12 ; fw = round( (f_out * 2^n_bit_acc) / f_clk ) fw_hex = dec2hex(fw) fw_bin = dec2bin(fw) I obtain this frequency word fw_hex = 3E0F83E1 fw_bin = 111110000011111000001111100001 Is this right ?? Do you think it wil give me problem with the spurs ??? Thanks ... Antonio D'OttavioArticle: 33941
Duane Clark a écrit : > > Howdy, > > I am wondering if it is possible to generate constants with a function. > What I basically want to do is generate a bunch of fixed bit masks. They > are all different, but it was easy to write a function to generate them. > However, I am not sure how to indicate to a synthesis tool (currently > Foundation Express, but probably soon Synplicity) that it should > hardcode the result of function, rather than implement the algorithm > used to generate it. > > The alternative of entering the values by hand into a constant works, > but there are 256 of them. Any other suggestions for something like this? > On a VHDL point of view you can initialize constants with functions. Very complex functions if needed (including reading files, etc): constant K: VERY_LONG_TAB := INIT(COSINE(5.4), "foo.dat", "11001"); On a synthesis point of view it depends on your tools... I don't know about Foundation Express or Synplicity but if they accept this, don't worry: they will hardcode the constants. The VHDL analyzer (front end of real synthesis) will compute the constants and pass their values, not their formula to the synthesizer. Regards, -- Renaud Pacalet, ENST / COMELEC, 46 rue Barrault 75634 Paris Cedex 13 Tel. : 01 45 81 78 08 | Fax : 01 45 80 40 36 | Mel : pacalet@enst.fr ###### Fight Spam! Join EuroCAUCE: http://www.euro.cauce.org/ ######Article: 33942
Hy Ray,
I tried your code but Aldec Active-HDL and Xilinx told me that this
sum could not be performed on this operands, I tried to discover the
problem but I've not found it .
reg_theta<= feedback + increment;
In any case coming back to my question , when you have a timing
problem with your project, you only work on the VHDL or also use
floorplanner and FPGA editor, I would want to understand if it's the
case to well understand how them work or the advantage of to know it
is really little.
Oh, I never told before, excuse me all for my bad english .
Thanks ..
Antonio D'Ottavio
Article: 33943Really often when I try to map my project on Xilinx , the mapper show me the following warning : " All of the external outputs in this design are using slew rate limited output drivers. The delay on speed critical outputs can be dramatically reduced by designating them as fast outputs in the schematic ??? " How I can do this, I mean designate output as fast output ?? This could speed up all my project ?? Thanks you all ... Antonio D'OttavioArticle: 33944
On 8 Aug 2001 23:49:04 -0700, dottavio@ised.it (Antonio) wrote: >Really often when I try to map my project on Xilinx , the mapper show >me the following warning : > >" All of the external outputs in this design are using slew rate >limited output drivers. The delay on speed critical outputs can be >dramatically reduced by designating them as fast outputs in the >schematic ??? " > > >How I can do this, I mean designate output as fast output ?? This >could speed up all my project ?? This will only speed up the I/O. It won't make any difference to the internal speed of your design, assuming that you are using the flip flops in the IOBs. (Have you done this? Your design won't work unless you do.) What is the setup and hold time for the data at the input of your DAC? What is the clock skew between the FPGA and the DAC? Are you using a DLL? What logic levels does the DAC expect? It may not be possible to get it to work at all at 165MHz with an XCV1000-4. Regards, Allan.Article: 33945
Hi,
I am trying to install 2.1i Foundation Series (Student Version) in Win2K, but I think I got a problem of administrative privileges. I have followed the procedure in answer database #11010 to solve some probelms. However, when I started to run the implementation, a message box prompted to indicate that "revengine" was failed to update the system registry, then the Flow Engine was terminated with fatal error. Two error message were showed as follow:
1. The instruction at "0x00371999" referenced memory at "0x000f062b". The memory could not be "read".
2. The instruction at "0x77fc90cd" reference memory at "0x000f0103". The memory could not be "written".
Moreover, that is the log file content:
------------------------------------------------------------------------------------------------
map -p xcv600e-8-hq240 -o map.ncd test.ngd test.pcf<br>
map: version C.22<br>
Copyright (c) 1995-1999 Xilinx, Inc. All rights reserved.<br>
Using target part 'v600ehq240-8'.<br>
Reading NGD file "test.ngd"...<br>
Processing FMAPs...<br>
Removing unused or disabled logic...<br>
Running cover...<br>
Writing file map.ngm...<br>
Running directed packing...<br>
Running delay-based packing...<br>
Running related packing...<br>
Writing design file "map.ncd"...<br>
Design Summary:<br>
Number of errors: 0<br>
Number of warnings: 1<br>
Number of Slices: 53 out of 6,912 1%<br>
Slice Flip Flops: 33<br>
4 input LUTs: 56<br>
Number of Slices containing<br>
unrelated logic: 0 out of 53 0%<br>
Number of bonded IOBs: 65 out of 154 42%<br>
Number of GCLKs: 1 out of 4 25%<br>
Number of GCLKIOBs: 1 out of 4 25%<br>
Total equivalent gate count for design: 777<br>
Additional JTAG gate count for IOBs: 3,168<br>
FATAL_ERROR:NgdHelpers:basmpreport.c:104:1.1.2.2 - Not able to add errors to file 'map.mrp'. Process will terminate. To resolve this error, please consult the Answers Database at http://support.xilinx.com
PROGRAM ABNORMALLY TERMINATED
--------------------------------------------------------------------------------------------------
Is that the problem of administrative privileges? If yes, what are the other registry keys that I need to set as full control? If not, what is the problem going on? Thank you very much!
Best regards,
Harry
Article: 33946Hello all, I need to fulfil the following requirements and I would appreciate any help in deciding whether the use of an FPGA will be feasable. I have 40 sensors whose outputs are pulses but with a slow repitition rate. Each 4 (four) of these pulses i.e. from four different sensors, are related to a specific event. What I need is to capture accurately the time difference between the arrival of these pulses in each group. I am thinking of using a very fast free running reference counter and latches. I will let the pulses act as a strobe to capture the output values of the counter. By comparing the values in the latches I can calculate the time difference between the arrival of the pulses. By my calculation, I need at least a 24 bit counter and thus 24 bit latches. Also, I will need a precise 10Mhz clock. Thus I will require 40 (forty) 24 bit latches, and a free running 24 bit binary counter. I wil need to be able to read all the output of the latches. Also, 40 different inputs should be available. The question is: Is there a single FPGA or CPLD that has the capability to implement the above? If no, how many will I need and which types and makes? Also, will it be easy to connect the FPGA to a PC bus and control it? I will also probably need a link to hardware interrupts to notify the PC of the availability of data to be read from the latches. Any help or better ideas to implement the above will be greatly appreciated. Thank You AliArticle: 33948
Hi there, I've got a problem while trying to implement a fft16 (V1.0.3) generated by the Xilinx Core Generator into Renoir (FPGA Advantage 4.0) by Mentor. Using the generated .vho file I made an in-line component configuration and when I try to generate HDL the following error appears: --- "my_fft_core_rtl.vhd",line 42: Error, unit 'xilinxcorelib.vfft16_comp' was not found or has errors (possibly in a dependency). --- But the libraries xilinxcorelib, unisim and simprim are compiled correctly (without errors) by modelsim and mapped into renoir. Maybe someone has an idea and can help me to solve this problem ??Article: 33949
Ali wrote: > > Hello all, > > I need to fulfil the following requirements and I would appreciate any > help in deciding whether the use of an FPGA will be feasable. > > I have 40 sensors whose outputs are pulses but with a slow repitition > rate. > Each 4 (four) of these pulses i.e. from four different sensors, are > related to a specific event. What I need is to capture accurately the > time difference between the arrival of these pulses in each group. > > I am thinking of using a very fast free running reference counter and > latches. I will let the pulses act as a strobe to capture the output > values of the counter. By comparing the values in the latches I can > calculate the time difference between the arrival of the pulses. > > By my calculation, I need at least a 24 bit counter and thus 24 bit > latches. Also, I will need a precise 10Mhz clock. > > Thus I will require 40 (forty) 24 bit latches, and a free running 24 > bit binary counter. I wil need to be able to read all the output of > the latches. Also, 40 different inputs should be available. > > The question is: Is there a single FPGA or CPLD that has the > capability to implement the above? If no, how many will I need and > which types and makes? You certainly fit such a design in almost any low-cost FPGA such as Xilinx xv4000/Spartan or Altera APEX. > > Also, will it be easy to connect the FPGA to a PC bus and control it? > I will also probably need a link to hardware interrupts to notify the > PC of the availability of data to be read from the latches. If you're looking toward buying a FPGA board, several models offer either a PCI bus interface or (for the smaller boards) a parralel port interface. You will have to make your choice depending on your required bandwith (PCI can offer 20Mbyte/sec without too much efforts) while a parallel port interface will not go above 1Mbit/sec (at best). Steven > Any help or better ideas to implement the above will be greatly > appreciated. > > Thank You > > Ali
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