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Thanks, i forget there was a 'numeric_std' library with useful things
in it like 'resize'. I tested this version, and it seems to work:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sat_add is
generic(width:natural:=4);
port(
a,b: in signed(width-1 downto 0);
s: out signed(width-1 downto 0)
);
end sat_add;
architecture rtl of sat_add is
signal aext:signed(width downto 0);
signal bext:signed(width downto 0);
signal lcl_sum:signed(width downto 0);
begin
aext<=resize(a,width+1);
bext<=resize(b,width+1);
lcl_sum<=aext+bext;
s<=lcl_sum(width-1 downto 0)
when
lcl_sum(width)=lcl_sum(width-1)
else
(lcl_sum(width),others=>not lcl_sum(width));
end rtl;
i learnt quite a bit just from this simple example:)
Ray Andraka wrote:
>
> For a saturating adder, sign extend the inputs by one bit more than you need for
> your output, then if the top two output bits don't match you substitute the
> overflow value. The Xilinx 4K was neat because with the carry chain in front of
> the logic, you could include the mux in the adder logic to get the whole thing in
> 1 lut per bit. Here is an RTL version that avoids having to construct the whole
> thing. I just typed this out, and it has not been tested so use at your own
> risk. Incidently, there are times when a structural construction is
> advantageous: it allows you to put placement in your code, and can also be used
> to enforce a specific structure. The synthesis tools do fine with basic adders,
> subtractors and counters. They can be more troublesome when you try to add
> functions (for example an adder/subtractor with one input gated), in that the
> synthesis may not turn out the optimal solution.
>
> library ieee;
> use ieee.std_logic_1164.all;
> use ieee.numeric_std.all;
>
> entity sat_add is
> port(
> a: in std_logic_vector;
> b: in std_logic_vector;
> s: out std_logic_vector);
>
> constant width:natural:=s'length;
> end sat_add;
>
> architecture rtl of sat_add is
> signal aext:signed(width downto 0);
> signal bext:signed(width downto 0);
> signal lcl_sum:std_logic_vector(width downto 0);
> signal limit:std_logic_vector(width-1 downto 0);
> begin
> aext<= resize(signed(a),width+1);
> bext<=resize(signed(b),width+1);
> lcl_sum<= std_logic_vector(aext+bext);
> limit<= (others=> lcl_sum(width);
> s<= lcl_sum(width-1 downto 0) when lcl_sum(width)=lcl_sum_width-1 else limit;
>
> end rtl;
>
> Russell Shaw wrote:
>
> > But how do you do a normal add while getting access to the right
> > carry bits?
> >
> > John_H wrote:
> > >
> > > You're trying to do all the work for the synthesizer by telling it how to
> > > perform addition.
> > > Let the synthesizer to the addition - you just concentrate on the saturable
> > > aspect.
> > > Leonardo spectrum should get all the carry chains together fine because it
> > > know how to utilize them to add.
> > >
> > > Russell Shaw wrote:
> > >
> > > > Hi all,
> > > >
> > > > I made this saturable adder from converting AHDL code in a previous
> > > > message.
> > > >
> > > > It adds signed HEX numbers together, but doesn't roll-over if there's
> > > > an overflow.
> > > >
> > > > I'm using leonardo-spectrum to generate an edif netlist, which is
> > > > compiled by altera maxplus2.
> > > >
> > > > Where and how, if any, can i add technology-dependent optimizations
> > > > such as carry chains etc?
> > > >
> > > > Also, are there such things as VHDL debuggers where you can single-
> > > > step thru the code and see what all the signals and variables are
> > > > doing?
> > > >
> > > > LIBRARY ieee;
> > > > USE ieee.std_logic_1164.all;
> > > >
> > > > PACKAGE types IS
> > > > subtype word is std_ulogic_vector(3 downto 0);
> > > > END types;
> > > >
> > > > LIBRARY ieee;
> > > > USE ieee.std_logic_1164.all;
> > > > use work.types.all;
> > > >
> > > > ENTITY saturable_adder IS
> > > > port(
> > > > a,b: in word;
> > > > s: out word
> > > > );
> > > > END adder;
> > > >
> > > > LIBRARY ieee;
> > > > USE ieee.std_logic_1164.all;
> > > > use work.types.all;
> > > >
> > > > ARCHITECTURE total OF saturable_adder IS
> > > > BEGIN
> > > > behav: PROCESS (a,b) is
> > > > variable sum: word;
> > > > variable carry_in,carry_out: std_ulogic;
> > > > constant msb:integer:=word'left;
> > > >
> > > > BEGIN
> > > > carry_in:='0';
> > > > for ndx in 0 to (word'left-1) loop
> > > > sum(ndx):=a(ndx) xor b(ndx) xor carry_in;
> > > > carry_out:=(a(ndx) and b(ndx)) or (a(ndx) and carry_in) or (b(ndx)
> > > > and carry_in);
> > > > carry_in:=carry_out;
> > > > end loop;
> > > > sum(msb):=a(msb) xor b(msb) xor carry_in;
> > > > if( (a(msb) and b(msb) and not carry_in)='1' )
> > > > then
> > > > sum:=(others=>'0');
> > > > sum(msb):='1';
> > > > elsif( (not a(msb) and not b(msb) and carry_in)='1' )
> > > > then
> > > > sum:=(others=>'1');
> > > > sum(msb):='0';
> > > > end if;
> > > > s<=sum;
> > > > END PROCESS behav;
> > > > END total;
> > > >
> >
> --
> -Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930 Fax 401/884-7950
> email ray@andraka.com
> http://www.andraka.com
--
___ ___
/ /\ / /\
/ /__\ Russell Shaw, B.Eng, M.Eng(Research) / /\/\
/__/ / Victoria, Australia, Down-Under /__/\/\/
\ \ / http://home.iprimus.com.au/rjshaw \ \/\/
\__\/ \__\/
Article: 33626I'm looking for a prototyping board containing 3 (or more) XC2V6000 FPGAs. Thanks, Rotem.Article: 33627
I am adding some code to a verilog design for debug and I need to access signals in a remote portion of the design. I have been told that there is a way to do this in the form of "top_level.mid_level.low_level.signal_name" where the level names are module instance names. This works ok in simulation, but I can't get it to work in synthesis. We are using Synplify. Is this not supported by this tool? Is this not supported by any synthesis tool? If this is supported for synthesis, any idea what I am doing wrong? Also is there a way to use a symbol for the top level part of the name since we have a top level test bench in the case of simulation and the top level module name has a unique instance name. Could I use a define such as `TOP_LEVEL.mid_level... where TOP_LEVEL is a defined symbol? Maybe that is what is wrong. In my code I am using the top level module name since there is no instance name. Is there something I am missing about the top level name? How does the synthesizer know which module is the top level? -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 33628
I tried somthing like that but with independent read and write
address. Latching the address with the clock and reading data
without clock. BUT Leonardo synthesized unlatched read address
and latched data out. It's the same function but with a very different
timing.
I think if you want to use the special functions (like embedded ram)
in a FPGA you have to code some vendor specific code.
Martin
--
Whant to see the evolution of a Java processor?
http://www.jopdesign.com
"Mike Treseler" <mike.treseler@flukenetworks.com> schrieb im Newsbeitrag
news:3B671696.B462BDDD@flukenetworks.com...
> Something like code below should work for leo.
> --Mike Treseler
>
> --------------------------------------------------------------------------
-----
> -- Exemplar Infers lpm_ram_dq synchronous ram from this code
> -- No exemplar libraries required, generic size
> -- M. Treseler 6-13-2001
> --------------------------------------------------------------------------
-----
> library ieee;
> use ieee.std_logic_1164.all;
> use ieee.numeric_std.all;
>
> entity sync_ram is
> generic (width : natural := 16;
> add_length : natural := 3
> );
>
> port ( clk : in std_logic;
> data : in std_logic_vector(width-1 downto 0);
> address : in std_logic_vector(add_length-1 downto 0);
> we : in std_logic;
> q : out std_logic_vector(width-1 downto 0)
> );
> end sync_ram;
>
> architecture synth of sync_ram is
> constant mem_size : natural := 2**add_length;
> type mem_type is array (mem_size-1 downto 0) of
> std_logic_vector (width-1 downto 0);
> signal mem : mem_type;
> signal address_q : std_logic_vector (add_length-1 downto 0);
> begin
>
> ram_write : process (clk)
> begin
> if clk'event and clk = '1' then
> always_adr_sync : address_q <= address;
>
> maybe_write : if we = '1' then
> mem(to_integer(unsigned(address))) <= data;
> end if;
> end if;
> end process ram_write;
>
> always_ram_read:
> q <= mem(to_integer(unsigned(address_q)));
> end architecture synth;
Article: 33629Ray Andraka wrote: > Paul Smart wrote: > > > Hi Ray, > > > > In principle, I agree with much of what you have said. > > > > On Tue, 31 Jul 2001 01:47:49 GMT, Ray Andraka <ray@andraka.com> wrote: > > > > > > > >It is behavioral in the sense that you can't go back and run that vhdl > > >through the tools to regenerate the design (wrong library). It doesn't > > >map directly back into the unisim primitives. > > > > > > > > Is there any way to take a modified verilog simulation file and put it > > back through to create a modified design? > > not any easy paths that I am aware of. You can remap the simprims into > unisims, but it is a very painful process. Probably less work starting on a > fresh design. I think its actually impossible to do this since there is a lot of information loss in the process of creating a Xilinx post-route sim netlist. e.g. all the various 2-way muxes, MUXF5, MUXF6, MUXCY, get turned into a single simprim X_MUX2. At least this is true for the flattened output from NGD2VER that I use. The ``re-create hierarchy'' mode might be better but a lot of that is still flattened. Parenthetically I've always wondered why Xilinx don't follow standard ASIC practice here and use the same lib for the design's EDIF netlist and the port-route sim one ? My - guessed - answer is that post-route sim is done much less frequently for FPGAs so the effort is not worth it, the unisims lib is far bigger than simprims.Article: 33630
On Wed, 01 Aug 2001 02:41:56 -0400, Rick Collins <spamgoeshere4@yahoo.com> wrote: >I am adding some code to a verilog design for debug and I need to access >signals in a remote portion of the design. I have been told that there >is a way to do this in the form of >"top_level.mid_level.low_level.signal_name" where the level names are >module instance names. This works ok in simulation, but I can't get it >to work in synthesis. We are using Synplify. Is this not supported by >this tool? Is this not supported by any synthesis tool? > >If this is supported for synthesis, any idea what I am doing wrong? Also >is there a way to use a symbol for the top level part of the name since >we have a top level test bench in the case of simulation and the top >level module name has a unique instance name. Could I use a define such >as `TOP_LEVEL.mid_level... where TOP_LEVEL is a defined symbol? > >Maybe that is what is wrong. In my code I am using the top level module >name since there is no instance name. Is there something I am missing >about the top level name? How does the synthesizer know which module is >the top level? Synplify doesn't support hierarchical names for synthesis. They have a feature in the Pro version where you can generate a top level port for any signal in the hierarchy but it can't select which instance you want if there are multiple instances of the signal. You get all of them at the top level. I am pretty sure no synthesis tool supports hierarchical names for synthesis but my experience is limited to Design Compiler and Synplify. The hierarchy starts with the module name of the top level. A define should work in the context you mention. The synthesizer doesn't know the top level. You have to tell it. In synplify there is an option where the top level module name is entered. In Design Compiler scripts, you set what ever module you want to work with and compile, optimize, write edf etc on the currently selected module. Muzaffer Muzaffer FPGA DSP Consulting http://www.dspia.comArticle: 33631
Hi, I am trying to configure my XCV1000E FPGA through SelectMap mode( wothout pull ups). My Configuration file (.bit) is stored in flash mem, using the Jflash program. I am reading the content of the flash byte by byte using a micro processor and sending it to FPGA . I am bit reversing the data read from flash so that D0 comes as MSB and D7 as LSB. Also I am not downloading the header info in the .bit file. I am sending the data starting from the pad word onwards. The DONE bit is not going HIGH after downloading the file.The FPGA is working properly when it is programmed in JTAG mode. Am I right with my procedure? Can anybody tell me what can the pitfalls? Expecting ur early response With kind regs Rajesh Kumar E.V raj@sasken.comArticle: 33632
On Wed, 01 Aug 2001 10:13:05 +1200, Jim Granville <jim.granville@designtools.co.nz> wrote: [snip] We've had failures here of a similar nature. The fault was definitely inside the FPGA, and would only occur for one particular route. Re-routing the design (i.e. making it use different resources inside the FPGA) would make the fault disappear. That route worked fine on other boards. The design (in the area that was failing) was completely synchronous, and met the timing requirements comfortably. The failure wasn't affected by clock speed or temperature variations, so I'm fairly sure it wasn't speed related. The board that failed had been x-rayed as part of its regular manufacturing inspection, and was believed to have all required power connections to the FPGA intact. Xilinx asked for the relevant part to be returned for analysis. I'm not sure what the final conclusion was, but I could chase it up if anyone is interested. Regards, Allan.Article: 33633
Hi, Please tell me how I can update Xilinx Foundation 2.1i . Your help will be appreciated . Thanks LUU^THANH TRUNGArticle: 33634
Hi, I would like to point out that I've got a MSc in Telecommunication Engineering and that didn't stopped me in working on fields that weren't supposed to be the field I was trainned for. I spent two years programming C code for CG animations. Lately I have spent one year working as a Network Engineer dealing with switches, routers, wiring, etc. And now I am to start a PhD in HW Architectures using FPGAs and DSPs. As you can see I have been quite able to change subject with no problem. I have programmed even although my degree wasn't a "programming" one (like Computer Science). I think that the important thing are the skills and not the "official" labels that some certain people likes to attach to anyone else. (You could try to program applications for FPGA design and then move to HW design with FPGAs. Try Altera, Xilinx, Synopsis, etc) Good luck! "edgar" <pound_euro@altavista.com> wrote in message news:91f37648.0107311030.7c271698@posting.google.com... > heya, > > > This year, I got my Bachelor in computer science. i wanted to > undertake a PhD in the fielld of FPGA, but i have been refused even > that i have my degree with a mark of 65%. > > when i asked the boss there, he told me this is a computer engineering > department and not computer science, i can't accepet you even if you > got 90%!!!! > > i have decided to join a software company, but still wondering on what > he means, > what is the differences between computer science and computer > engineering ? > > > Edgar SArticle: 33635
Hi all, from a 'little' a bit older project I do have ~ 400 EPC1 devices - Unprogrammed! - for ALTERA FPGA's. If anyone is interested in buying them, I will shurely make an attractive price... markus -- ******************************************************************** ** Meng Engineering Telefon 056 222 44 10 ** ** Markus Meng Natel 079 230 93 86 ** ** Bruggerstr. 21 Telefax 056 222 44 10 ** ** CH-5400 Baden Email meng.engineering@bluewin.ch ** ******************************************************************** ** Theory may inform, but Practice convinces. -- George Bain **Article: 33636
> I am adding some code to a verilog design for debug and I need to access > signals in a remote portion of the design. I have been told that there > is a way to do this in the form of > "top_level.mid_level.low_level.signal_name" where the level names are > module instance names. This works ok in simulation, but I can't get it > to work in synthesis. We are using Synplify. Is this not supported by > this tool? Is this not supported by any synthesis tool? Synplify doesn't support hierarchical references. > If this is supported for synthesis, any idea what I am doing wrong? Also > is there a way to use a symbol for the top level part of the name since > we have a top level test bench in the case of simulation and the top > level module name has a unique instance name. Could I use a define such > as `TOP_LEVEL.mid_level... where TOP_LEVEL is a defined symbol? > Try : `ifdef SIMULATION fofo top_for_simulation() `else fofo top_for_synthesis() `endif Regards, Rotem. > Maybe that is what is wrong. In my code I am using the top level module > name since there is no instance name. Is there something I am missing > about the top level name? How does the synthesizer know which module is > the top level? > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAXArticle: 33637
Ray, I believe that the reason the error rate has remained constant over the years is because Xilinx has managed to improve their quality both in manufacturing and in testing to keep pace with the improvement in density. If you think about it all chip manufacturers have to improve the defect rate at the same rate as the density rate. If you had the same number of defects per gate at .13u as at 1.0u then the yields would be approaching zero. For any particular yield rate there has to a certain defect level per die. If the "hidden" defect rate is directly correlated with the "visible" defect rate then the rates over the years would remain constant if the yields have remained constant. If the quality of the testing improved then the hidden/visible ratio would drop and we would see lower hidden defect rates. Unfortunately I don't have good numbers on Virtex the way I did on the various 4000 family members, but from what I've seen in the lab on a sample size of a few thousand XCV800s I believe that the hidden defect rate is lower, possible as low as 1 in 400 as opposed to 1 in 50 for the 4000 families. Josh In article <3B67500D.31BE11ED@andraka.com>, "Ray Andraka" <ray@andraka.com> wrote: > I an see where my comment might have been inflammatory. It was not > intended to be so. I was merely making the observation that cost and > size of company do not determine the quality of a design. Knowing > nothing about this particular test suite I can't say whether or not > there is a design fault. My experience causes me to be very skeptical > when someone declares there is a chip problem, especially when there are > claims of very high failure rates. Most of the time it turns out to be a > problem with the design rather than the chip. If you look at your posts > from an outsider's point of view, I am sure you'd reach the same > conclusion. > > If the defects are of the order of magnitude Joshua indicates, there is > need to worry, especially in designs like many of mine where we are > taking some advantage of reconfiguration and depending on having a good > device. I do realize the that large designs do not necessarily use many > pips. In fact, for high performance designs, I try to minimize the > number of pips crossed. Much of the routing is purposely to adjacent > CLBs, which for the most part misses the majority of the pips in the > chip. I'm probably using significantly LESS than the average number of > used pips, so, I'll concede that my designs may not have hit a bad pip > yet. Perhaps I have a lower probability of hitting a defect as a result. > > One thing that puzzles me is Joshua's comment that the error rates have > remained pretty consistent over several generations of product. I would > expect that as the device density increases and the feature size is > decreased that the number of defects per chip would increase, not stay > at some constant level. The constant error rate was part of what > pointed me in the direction of a clock skew or signals integrity problem > in the first place. > > > > Jim Granville wrote: > >> <ray@andraka.com> wrote: >> > > No trying to be a pain, but I've seen some >> > > pretty bad design in very expensive equipment over the years. >> B. Joshua Rosen wrote: >> > >> > Ray I shouldn't dignify this with a response since you are clearly >> > talking about a subject that you know nothing about. >> >> Whoa guys, settle down..! >> >> The subject is very interesting, don't fall into the 'shoot the >> messenger' >> trap. >> >> This type of problem will be often missed, or taken as something else. >> >> IIRC, Josh did say he fed the info back to Xilinx, and it seems >> they have changed/improved their testing coverage as a result. >> That's both significant, and a step forward. >> >> Test coverage is a time/cost tradeoff, but there are interesting >> points >> that come from using a finite defect device. >> eg it means a field upgrade needs care, and may not work 100.0% of the >> time. >> ( if the thing is in orbit, that's something of a problem :) > > It also means that you may have a yield fallout in a shipping product. > > >> >> It also suggests that a single Eval/development PCB is not a good >> idea, >> unless that FPGA has had the extra cost screening, or perhaps the >> designer >> is experienced enough to 'know' when it's a HW problem, not a SW one >> :-) >> >> Reminds me of a story I heard about Russian Microcontrollers - they >> were >> pushing the yield/fab envelope and every chip came with it's own >> 'functional opcode' list. Code written for that device, had to avoid >> the broken opcodes :-) >> This was many years before the 'errata' became more common practice. >> >> -jg >> >> B. Joshua Rosen wrote: >> > I'll give more detail about the nature of the failures that we see. >> > We run these tests on approximately 30,000 FPGAs a year. Prior to >> > prescreening we were seeing a fall out rate of about 1 in 50. The >> > reports that we get back form Xilinx on the screened parts are >> > consistant with that number. The nature of the failure is that a bad >> > part will fail 2 or 3 patterns out of a total of about 150. We can't >> > identify a particular node because the tests are designed to give a >> > go/no go answer. However we can generally determine which half of the >> > FPGA failed because all of the tests are part of a pair, each member >> > testing approximately 50% of the CLBs. It's clear that the defects >> > are very small, maybe as small as a single gate. Bad parts mostly >> > work, i.e. out of 150 patterns they will pass 147 or 148. The clock >> > speed range is 12Mhz to 30Mhz. The designs are completely syncronous >> > and there are no gated clocks. Parts that fail will generally fail at >> > all clock speeds so you can see it's not a timing problem. It should >> > be obvious that a design that can't run at 12Mhz on one part is >> > unlikely to run at 30Mhz on the remaining 400 parts in the system, >> > but of course they do run on the remaining parts because there are no >> > timing problems in the designs. The reason that you haven't seen >> > these problems is because you aren't looking. We only knew that there >> > was a problem because we were getting reports from the field about >> > failures. The nature of ASIC emulators makes it's possible to >> > identify the source of a problem by shuffling the patterns between >> > different FPGAs. The field guys were then able to identify the bad >> > FPGAs. After we realized that there was a problem we developed these >> > test patterns. Now field failures are much much less frequent, >> > although they aren't zero because our coverage isn't 100%. > > -- > -Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. 401/884-7930 Fax > 401/884-7950 > email ray@andraka.com > http://www.andraka.com > >Article: 33638
I am using Leonardo Spectrum (Version: v20001a2.75 (Release Production, compiled Aug 29 2000 at 12:35:44)). I have done Post Synthesis Simulation for Xilinx Virtex devices using Unisim VHDL Library. But using this library I am unable to do post synthesis simulation for other Xilinx family devices. Can someone tell me whether it is possible to do Post Synthesis Simulation for Xilinx Spartan and 4000 series devices. If so please let me know how this can be done ?Article: 33639
Has any one had a go at opening schematic files in WebPack that were generated in Foundation 2.1? I have been sent some source for a 9572 CPLD and I would like to use it as a basis for further development. Any help would be appreciated. Regards, Simon -- -----------------------------------------Article: 33640
Hello all, just a simple question: I am concerned what might happen when I put a Xilinx Virtex part on a board where two package pins are connected to the same net. In the FPGA definetely only one of the pins (inputs) is connected to some logic / clock network. The other is left open / unused. This is because we a using the same board for different versions (with different pinouts) of this FPGA. Has anybody some experience with this? Does the connection to the unused pin have some impact on the net? What kind of problems do I have to expect? And most of all, what can I do to avoid them (while keeping the board connections)? Any help is appreciated. cheers olafArticle: 33641
A few thoughts about why my tests find problems that Xilinx's don't. Xilinx has always designed their tests to maximize PIP coverage, whereas mine are designed to test the maximum number of interconnect paths. I design my test suite to test a range of interconnect distances from nearest neighbor to the length of the die, and as many interconnect directions as I can reasonably cover. I use PIP count as a proxy for my test coverage but I don't drive my test design based on PIP count. In a truely digital system PIP coverage would be the same as chip coverage. However I believe that much of the interconnect on a Xilinx chip is based on transmission gates rather than on active gates (Peter is the Correct?). A transmission gate has analog properties, it has an on resistance and an off resistance. If the on resistance were higher than normal the path might still work if there were only one or two transmission gates in the circuit. But for long runs the resistance of each gate would add up as would the resistance of the lines between the pass gates. As a result it's possible to have paths that don't work even if all of the segments of the paths work individually. It also explains why it would be impossible to test any FPGA 100%. The number of possible paths across an FPGA is effectively infinite.Article: 33642
Hi all,
I haveing some trouble with this code I wrote...
the pronblem i'm getting is with the values of ma[], wat i'm trying to do is
copy the values od upad[] to ma[] and where ma[] is clocked with up_ale and
it doesn't gimme the write vales after copying it to ma[]...
Wat could be the problem?
Many thx for the help...
Abhimanyu.....
Code:--
SUBDESIGN hib_card
(
clk, reset :INPUT;
--micro inputs ( they already exist )
upad[7..0], /up_cs5, /up_rd, /up_wr, up_ale :INPUT;
data_out, band_config[2..0] :OUTPUT;
)
VARIABLE
moore_state : MACHINE OF BITS (q1, q2, q3) WITH STATES (
S0 = B"101", --hib_data2
S1 = B"100", --hib_data1
S2 = B"011", --hib_data0
S3 = B"010", --hib_status
S4 = B"001", --pr_data
S5 = B"000"); --pr_status (ignoring the last 2 states for the moment)
data_word[21..0] :DFFE; --for storing all 22 bits of address and data
ma[7..0] :DFFE; --for storing the data into the reg at every !up_ale
in_clk :DFFE;
hib :NODE;
status :NODE;
pll_sel :NODE;
p186_read :NODE;
p186_write :NODE;
hib_read_data2 :NODE;
hib_write_data2 :NODE;
hib_read_data1 :NODE;
hib_write_data1 :NODE;
hib_read_data0 :NODE;
hib_write_data0 :NODE;
hib_write_status :NODE;
BEGIN
(ma[], data_word[]).clk = !up_ale; --clocks ma, data_word with up_ale, so
that they change data at the same clock
ma[] = upad[]; -- saves data from the micro to altera
in_clk.clk = clk;
in_clk = !in_clk;
p186_read = !/up_cs5 & !/up_rd; --sets the flag to read from altera
p186_write = !/up_cs5 & !/up_wr; --sets the flag to write to altera
moore_state.clk = clk;
moore_state.reset = reset;
CASE moore_state IS
WHEN S0 =>
hib = VCC;
status = GND;
data_out = VCC;
hib_read_data2 = p186_read & hib & !status;
hib_write_data2 = p186_write & hib & !status;
data_word[21..16] = ma[5..0];
IF up_ale THEN
moore_state = S1;
ELSE
moore_state = S0;
END IF;
WHEN S1 =>
hib = VCC;
status = GND;
data_out = VCC;
hib_read_data1 = p186_read & hib & !status;
hib_write_data1 = p186_write & hib & !status;
data_word[15..8] = ma[7..0];
IF up_ale THEN
moore_state = S2;
ELSE
moore_state = S1;
END IF;
WHEN S2 =>
hib = VCC;
status = GND;
data_out = VCC;
hib_read_data0 = p186_read & hib & !status;
hib_write_data0 = p186_write & hib & !status;
data_word[7..0] = ma[7..0];
IF up_ale THEN
moore_state = S3;
ELSE
moore_state = S2;
END IF;
WHEN S3 =>
hib = VCC;
status = VCC;
data_out = GND;
IF ma[4] THEN
band_config[2..0] = ma[2..0];
pll_sel = VCC;
ELSE
pll_sel = GND;
END IF;
hib_write_status = p186_write & hib & status;
IF up_ale THEN
moore_state = S4;
ELSE
moore_state = S3;
END IF;
WHEN OTHERS =>
moore_state = S0;
END CASE;
END;
Article: 33643Rick Filipkiewicz wrote: > Ray Andraka wrote: > > > Paul Smart wrote: > > > > > Hi Ray, > > > > > > In principle, I agree with much of what you have said. > > > > > > On Tue, 31 Jul 2001 01:47:49 GMT, Ray Andraka <ray@andraka.com> wrote: > > > > > > > > > > >It is behavioral in the sense that you can't go back and run that vhdl > > > >through the tools to regenerate the design (wrong library). It doesn't > > > >map directly back into the unisim primitives. > > > > > > > > > > > Is there any way to take a modified verilog simulation file and put it > > > back through to create a modified design? > > > > not any easy paths that I am aware of. You can remap the simprims into > > unisims, but it is a very painful process. Probably less work starting on a > > fresh design. > > I think its actually impossible to do this since there is a lot of information loss > in the process of creating a Xilinx post-route sim netlist. e.g. all the various > 2-way muxes, MUXF5, MUXF6, MUXCY, get turned into a single simprim X_MUX2. At least > this is true for the flattened output from NGD2VER that I use. The ``re-create > hierarchy'' mode might be better but a lot of that is still flattened. THis is why I said is is a very painful process. You can get to something that is functional but may not map very well into the architecture fairly easily. Like you point out, you lose all the architectural features like the carry chain stuff. You also lose any placement you might have had. I suspect part of the reason for using different libraries is a (misguided?) attempt to retain design security. > > > Parenthetically I've always wondered why Xilinx don't follow standard ASIC practice > here and use the same lib for the design's EDIF netlist and the port-route sim one > ? My - guessed - answer is that post-route sim is done much less frequently for > FPGAs so the effort is not worth it, the unisims lib is far bigger than simprims. -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.comArticle: 33644
The problem is those labels seem to be pretty important when applying for advanced degrees, which is what prompted the question in the first place. Gabriel Caffarena wrote: > Hi, > > I would like to point out that I've got a MSc in Telecommunication > Engineering and that didn't stopped me in working on fields that weren't > supposed to be the field I was trainned for. I spent two years programming C > code for CG animations. Lately I have spent one year working as a Network > Engineer dealing with switches, routers, wiring, etc. And now I am to start > a PhD in HW Architectures using FPGAs and DSPs. As you can see I have been > quite able to change subject with no problem. I have programmed even > although my degree wasn't a "programming" one (like Computer Science). I > think that the important thing are the skills and not the "official" labels > that some certain people likes to attach to anyone else. > > (You could try to program applications for FPGA design and then move to HW > design with FPGAs. Try Altera, Xilinx, Synopsis, etc) > > Good luck! > > "edgar" <pound_euro@altavista.com> wrote in message > news:91f37648.0107311030.7c271698@posting.google.com... > > heya, > > > > > > This year, I got my Bachelor in computer science. i wanted to > > undertake a PhD in the fielld of FPGA, but i have been refused even > > that i have my degree with a mark of 65%. > > > > when i asked the boss there, he told me this is a computer engineering > > department and not computer science, i can't accepet you even if you > > got 90%!!!! > > > > i have decided to join a software company, but still wondering on what > > he means, > > what is the differences between computer science and computer > > engineering ? > > > > > > Edgar S -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.comArticle: 33645
You've defined ma[] as DFFE elements (D type flip flop with enable). Where's the enable? Abhimanyu Rastogi wrote: > Hi all, > I haveing some trouble with this code I wrote... > the pronblem i'm getting is with the values of ma[], wat i'm trying to do is > copy the values od upad[] to ma[] and where ma[] is clocked with up_ale and > it doesn't gimme the write vales after copying it to ma[]... > > Wat could be the problem? > > Many thx for the help... > > Abhimanyu..... > > Code:-- > > SUBDESIGN hib_card > ( > clk, reset :INPUT; > > --micro inputs ( they already exist ) > upad[7..0], /up_cs5, /up_rd, /up_wr, up_ale :INPUT; > > data_out, band_config[2..0] :OUTPUT; > ) > > VARIABLE > moore_state : MACHINE OF BITS (q1, q2, q3) WITH STATES ( > S0 = B"101", --hib_data2 > S1 = B"100", --hib_data1 > S2 = B"011", --hib_data0 > S3 = B"010", --hib_status > S4 = B"001", --pr_data > S5 = B"000"); --pr_status (ignoring the last 2 states for the moment) > > data_word[21..0] :DFFE; --for storing all 22 bits of address and data > ma[7..0] :DFFE; --for storing the data into the reg at every !up_ale > in_clk :DFFE; > hib :NODE; > status :NODE; > pll_sel :NODE; > p186_read :NODE; > p186_write :NODE; > hib_read_data2 :NODE; > hib_write_data2 :NODE; > hib_read_data1 :NODE; > hib_write_data1 :NODE; > hib_read_data0 :NODE; > hib_write_data0 :NODE; > hib_write_status :NODE; > > BEGIN > (ma[], data_word[]).clk = !up_ale; --clocks ma, data_word with up_ale, so > that they change data at the same clock > ma[] = upad[]; -- saves data from the micro to altera > in_clk.clk = clk; > in_clk = !in_clk; > p186_read = !/up_cs5 & !/up_rd; --sets the flag to read from altera > p186_write = !/up_cs5 & !/up_wr; --sets the flag to write to altera > moore_state.clk = clk; > moore_state.reset = reset; > CASE moore_state IS > WHEN S0 => > hib = VCC; > status = GND; > data_out = VCC; > hib_read_data2 = p186_read & hib & !status; > hib_write_data2 = p186_write & hib & !status; > data_word[21..16] = ma[5..0]; > IF up_ale THEN > moore_state = S1; > ELSE > moore_state = S0; > END IF; > WHEN S1 => > hib = VCC; > status = GND; > data_out = VCC; > hib_read_data1 = p186_read & hib & !status; > hib_write_data1 = p186_write & hib & !status; > data_word[15..8] = ma[7..0]; > IF up_ale THEN > moore_state = S2; > ELSE > moore_state = S1; > END IF; > WHEN S2 => > hib = VCC; > status = GND; > data_out = VCC; > hib_read_data0 = p186_read & hib & !status; > hib_write_data0 = p186_write & hib & !status; > data_word[7..0] = ma[7..0]; > IF up_ale THEN > moore_state = S3; > ELSE > moore_state = S2; > END IF; > WHEN S3 => > hib = VCC; > status = VCC; > data_out = GND; > IF ma[4] THEN > band_config[2..0] = ma[2..0]; > pll_sel = VCC; > ELSE > pll_sel = GND; > END IF; > hib_write_status = p186_write & hib & status; > IF up_ale THEN > moore_state = S4; > ELSE > moore_state = S3; > END IF; > WHEN OTHERS => > moore_state = S0; > END CASE; > END;Article: 33646
Since the XC2V6000 devices are about $8000 US each through distribution, maybe contracting someone to make a board for you to your own specifications is a cost effective way to achieve your goal. Rotem Gazit wrote: > I'm looking for a prototyping board containing 3 (or more) XC2V6000 FPGAs. > > Thanks, > > Rotem.Article: 33647
I'm new at this... i thought DFFE or DFF would not make a moajor difference.... but even after i change dffe to dff it still gives me the same old values for ma[]..... if u want i can also attach the correspondaing *.scf file.. Abhimanyu John_H <johnhandwork@mail.com> wrote in message news:3B681795.ECEA1DDB@mail.com... > You've defined ma[] as DFFE elements (D type flip flop with enable). > Where's the enable? > > > Abhimanyu Rastogi wrote: > > > Hi all, > > I haveing some trouble with this code I wrote... > > the pronblem i'm getting is with the values of ma[], wat i'm trying to do is > > copy the values od upad[] to ma[] and where ma[] is clocked with up_ale and > > it doesn't gimme the write vales after copying it to ma[]... > > > > Wat could be the problem? > > > > Many thx for the help... > > > > Abhimanyu..... > > > > Code:-- > > > > SUBDESIGN hib_card > > ( > > clk, reset :INPUT; > > > > --micro inputs ( they already exist ) > > upad[7..0], /up_cs5, /up_rd, /up_wr, up_ale :INPUT; > > > > data_out, band_config[2..0] :OUTPUT; > > ) > > > > VARIABLE > > moore_state : MACHINE OF BITS (q1, q2, q3) WITH STATES ( > > S0 = B"101", --hib_data2 > > S1 = B"100", --hib_data1 > > S2 = B"011", --hib_data0 > > S3 = B"010", --hib_status > > S4 = B"001", --pr_data > > S5 = B"000"); --pr_status (ignoring the last 2 states for the moment) > > > > data_word[21..0] :DFFE; --for storing all 22 bits of address and data > > ma[7..0] :DFFE; --for storing the data into the reg at every !up_ale > > in_clk :DFFE; > > hib :NODE; > > status :NODE; > > pll_sel :NODE; > > p186_read :NODE; > > p186_write :NODE; > > hib_read_data2 :NODE; > > hib_write_data2 :NODE; > > hib_read_data1 :NODE; > > hib_write_data1 :NODE; > > hib_read_data0 :NODE; > > hib_write_data0 :NODE; > > hib_write_status :NODE; > > > > BEGIN > > (ma[], data_word[]).clk = !up_ale; --clocks ma, data_word with up_ale, so > > that they change data at the same clock > > ma[] = upad[]; -- saves data from the micro to altera > > in_clk.clk = clk; > > in_clk = !in_clk; > > p186_read = !/up_cs5 & !/up_rd; --sets the flag to read from altera > > p186_write = !/up_cs5 & !/up_wr; --sets the flag to write to altera > > moore_state.clk = clk; > > moore_state.reset = reset; > > CASE moore_state IS > > WHEN S0 => > > hib = VCC; > > status = GND; > > data_out = VCC; > > hib_read_data2 = p186_read & hib & !status; > > hib_write_data2 = p186_write & hib & !status; > > data_word[21..16] = ma[5..0]; > > IF up_ale THEN > > moore_state = S1; > > ELSE > > moore_state = S0; > > END IF; > > WHEN S1 => > > hib = VCC; > > status = GND; > > data_out = VCC; > > hib_read_data1 = p186_read & hib & !status; > > hib_write_data1 = p186_write & hib & !status; > > data_word[15..8] = ma[7..0]; > > IF up_ale THEN > > moore_state = S2; > > ELSE > > moore_state = S1; > > END IF; > > WHEN S2 => > > hib = VCC; > > status = GND; > > data_out = VCC; > > hib_read_data0 = p186_read & hib & !status; > > hib_write_data0 = p186_write & hib & !status; > > data_word[7..0] = ma[7..0]; > > IF up_ale THEN > > moore_state = S3; > > ELSE > > moore_state = S2; > > END IF; > > WHEN S3 => > > hib = VCC; > > status = VCC; > > data_out = GND; > > IF ma[4] THEN > > band_config[2..0] = ma[2..0]; > > pll_sel = VCC; > > ELSE > > pll_sel = GND; > > END IF; > > hib_write_status = p186_write & hib & status; > > IF up_ale THEN > > moore_state = S4; > > ELSE > > moore_state = S3; > > END IF; > > WHEN OTHERS => > > moore_state = S0; > > END CASE; > > END; >Article: 33648
Olaf, there is no problem, as long as you don't configure both pins as outputs and drive them to opposite levels. :-( The extra input pin just represents a max 10 pF load and thus slows down the signal by at most a few hundred picoseconds. If you have a very tight signal-integrity situation, you may want so simulate this with HyperLynx. Peter Alfke, Xilinx Applications ===================== Olaf Reichenbaecher wrote: > Hello all, > > just a simple question: I am concerned what might happen when > I put a Xilinx Virtex part on a board where two package pins > are connected to the same net. > In the FPGA definetely only one of the pins (inputs) is connected to > some logic / clock network. The other is left open / unused. > This is because we a using the same board for different versions > (with different pinouts) of this FPGA. > > Has anybody some experience with this? Does the connection to > the unused pin have some impact on the net? What kind of problems > do I have to expect? And most of all, what can I do to avoid them > (while keeping the board connections)? > Any help is appreciated. > > cheers > > olafArticle: 33649
HI all, I have a design which consists of a data-path and a controller. Some controller signals drive two components of the data-path. During synthesis (Synopsys Design Comp.) such signals are divided in two seperate signals whereby always one of the both gets two inverters. During Mapping with XactM3.1 one of these inverters is removed because of being redundant. The other is mapped into a LUT, but this LUT don't invert, that's clear. But why all this is done? Does such a LUT act as a buffer or is it unnecessary? Pascal
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