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Rick Collins wrote:
> Rick Filipkiewicz wrote:
> > I've been working around this for some time by maintaining a list of what I
> > expect to see in the IOBs
> > and using a perl script to compare that with the last section of the MAP
> > report. The list, in fact, holds exceptions to the rule that everything is
> > registered onto & off the chip i.e. the default is to see INFF/OUTFF on an
> > input/output (or both on a bidir - the script parses the top level module to
> > get a list of the IOs).
>
> I am dealing with this problem right now. I can't seem to find the
> earlier posts on this topic that would have covered the details that can
> prevent an inferred FF from being moved to the IOB. I know you can't use
> the async S/R (other than via GSR) and you can't use the output for any
> other logic for an OFDX. A manager who has worked this design says you
> can't even source the FF from internal logic, but rather it has to be
> connected to another FF output. Anyone know about this?
>
That might have been true once, I vaguely remember it circa M1.4/5, but it
certainly isn't 2.1i+.
>
> I looked through a hundred or so results in the Xilinx data base, but
> could not find a doc that summarizes all of the things that are required
> to let a FF be placed in the IOB. Our parts are 4000XLA.
>
> Anyone care to take a stab at this list?
>
Here are the rules for IN/OUT FFs. The tri-state FFs are special and for XC4K
series parts that have them they have to be forced in some obscure way I cannot
remember.
R1: Out FF: No feedback from the output pin, no post output logic. For XC4K you
can do an inversion since the output polarity is selectable but that's all & even
that's dangerous since the synth tool might decide to merge some other logic in
with the inversion.
R2: In FF: No rules except the weak one that there must be no logic between the
pin & FF.
For BiDir IOs where both in & out are to be registered we have:
R3A: Common clock. Shouldn't be a problem if you stick to the globals.
R3B: Common initialisation signal. In can do different things to either FF e.g.
one can be an async set & the other a sync preset. A corollary to this is that if
one FF has an init condition so must the other & from the same signal. In other
words this sort of thing is not allowed:
always @(posedge clk)
if (reset_myinput)
reg_myinput <= 0;
else
reg_myinput <= myinput;
always @(posedge clk)
reg_myoutput <= myoutput_src
I'm not sure whether this last is a an architectural restriction or a s/w bug
that's now a feature.
R3C: [XC4K only, maybe only some of them] Common clock enable. Note that as in R3A
if one FF has a CE then so must the other.
Now for the crunches aka what Synplify does wrong:
o If you have a bidir registered IO bus with say 64 pins then R3B says that all 64
FF pairs have to have the same init signal. The simplest solution to this is to
just have one common signal. However even if you ensure this in the code Synplify
may do some replication for you & break the rule because it doesn't have the
intelligence to make sure that after fanning out it sticks to R3B is it can.
Similarly for R3C & XC4K parts.
o Synplify considers e.g. a synchronous reset as a "free and gate" in this sense:
If it sees this sort of structure in the logic feeding an FF:
!foo & bar
it will quite cheerfully put foo on the `D' input & bar on the sync reset -
potentially violating R3B. This is where I first came across the IOB packing
problem. Its also possible that this is what your manager has seen as well. You
can hack around this with ``syn_keep'' directives or adding an async set/reset to
the FF concerned.
o If the register you want to pack into an IOB output FF is buried deep inside
some state machine there's no way of telling the Syn' optimiser not to violate R1.
This is the one I'm fighting at the moment. I have a couple of seriously ugly code
specific kludges that work but I don't yet quite understand *why* they work.
However this might just be a consequence of my design style - I don't like
designing SMs as separate combinatorial & registered parts. Even that doesn't help
without adding some extraneous signals to confuse the optimiser.
Of course if you have Syn-Pro with retiming switched on globally that's yet
another source of IOB FF rule breaking.
This is the story as far as I know it & as long as I can (i) stick to the rules at
HDL level, (ii) persuade Syn not to break them behind my back, then IOB packing
works fine [I just set the -pr b flag to MAP].
Generally things go along o.k. for a long time then I do some change & my MAP
report parser barfs & I end up with long & tedious head scratching session.
I might be behind the s/w times on some of these rules & its just possible that
I've overspec'ed the restrictions but I don't think by very much. Basically IOB FF
packing is easy & automagic when it goes right but a serious, Class 1++, PITA when
it doesn't. I tend to leave fixing it till right to the end, if I can, after the
logic works & the timing analysis is fine everywhere but some IOB failed-to-pack
FFs. I don't like doing it like this but the patches that need to be applied are
sometimes build specific.
Your mileage will probably vary by an order of magnitude or so ... Good luck &
happy packing.
Article: 33501Hi Zimba, I'm interested on the 10$ PLX9052, where/how do I get its specification? who's manufacture? Best regards, Hong You Wrote: >>>Just to let you know, the Xilinx PCI core for Spartan II costs about $5000,- (I have one). A PLX9052 is about $10,-. Clemens<<<Article: 33502
Dave Feustel wrote: > The modelsim licensing program never asked me for the name > of the file containing the license. I think the problem is more > basic than that. And at this point I am pretty fed up with the > entire licensing fiasco that I have been experiencing. It would seem that radical measures are called for. (Tongue in cheek here) If you can afford the upfront outlay why not travel to Xilinx headquarters bearing your machine & the eval CD, get into the support area, and chain yourself to the release managers desk until they sort it & re-imburse the costs - if necessary also the ones associated with any HD reformat that might be needed. After succeeding there you move on to ModelSim. The lack of any sensible information about errors is absolutely typical of anything that's been touched by Visual C/C++. If its not license.dat the only way to get any further is to install some cheapo version VC/C++ and trigger the debugger on the error. One possibility occurs. From time to time I've edited the license.dat file with wordpad to add a new year's license that's arrived by email. If I select ``Save as plain text'' what happens is that a new file called ``license.dat.txt'' is created but Explorer cannot handle this so only displays ``license.dat''!? You can only see the error via the NT shell's DIR command. No more problems now I'm using the Xemacs on both the PC & the Unix box. <Flame> Does anyone but me find this idea utterly disgraceful that some s/w can do irreversible things to my HD that effectively trashes it if I just want to set my clock a bit more accurately? This isn't license protection its the rampant paranoia behind the ``Digital Millenium Copyright'' act that Adobe used recently on what appears to be a relatively innocent Russian. Xilinx I think don't do this,at the price of ``You don't buy the s/w you rent it''. <Flame turned down - a bit>Article: 33503
Haven't done that as far as I know. "Ben Franchuk" <bfranchuk@jetnet.ab.ca> wrote in message news:3B627063.4093183@jetnet.ab.ca... > Dave Feustel wrote: > > > > The modelsim licensing program never asked me for the name > > of the file containing the license. I think the problem is more > > basic than that. And at this point I am pretty fed up with the > > entire licensing fiasco that I have been experiencing. > > And if you ever set your real time clock ahead by accident, you practicaly > have to format the drive and reinstall everything ( and get a new licence) > if you want to run your computer at the correct time. The moment you > set you clock back the software will refuse to run. > Ben.Article: 33504
Haven't edited the license.dat file. Did try rerunning the install program as administrator in the faint hope that perhaps the program failed because I had downloaded and installed it as a restricted user. No Joy. Did discover that modelsim.ini was read only. made it writeable and reinstalled. Same useless error message with no info. This time the error message occurs during instal - I didn't have to run the licensing wizard to get the bad news. I think it's time to try Silos 3 again. "Rick Filipkiewicz" <rick@algor.co.uk> wrote in message news:3B631FA5.3510C44F@algor.co.uk... > > > Dave Feustel wrote: > > > The modelsim licensing program never asked me for the name > > of the file containing the license. I think the problem is more > > basic than that. And at this point I am pretty fed up with the > > entire licensing fiasco that I have been experiencing. > > It would seem that radical measures are called for. (Tongue in cheek here) If you can afford the upfront outlay why > not travel to Xilinx headquarters bearing your machine & the eval CD, get into the support area, and chain yourself to > the release managers desk until they sort it & re-imburse the costs - if necessary also the ones associated with any > HD reformat that might be needed. > > After succeeding there you move on to ModelSim. The lack of any sensible information about errors is absolutely > typical of anything that's been touched by Visual C/C++. If its not license.dat the only way to get any further is to > install some cheapo version VC/C++ and trigger the debugger on the error. > > One possibility occurs. From time to time I've edited the license.dat file with wordpad to add a new year's license > that's arrived by email. If I select ``Save as plain text'' what happens is that a new file called ``license.dat.txt'' > is created but Explorer cannot handle this so only displays ``license.dat''!? > You can only see the error via the NT shell's DIR command. No more problems now I'm using the Xemacs on both the PC & > the Unix box. > > <Flame> > Does anyone but me find this idea utterly disgraceful that some s/w can do irreversible things to my HD that > effectively trashes it if I just want to set my clock a bit more accurately? This isn't license protection its the > rampant paranoia behind the ``Digital Millenium Copyright'' act that Adobe used recently on what appears to be a > relatively innocent Russian. > > Xilinx I think don't do this,at the price of ``You don't buy the s/w you rent it''. > > <Flame turned down - a bit> > >Article: 33505
Can someone post the results of running 'find /modelsim' on a computer with a working version of the program so that I can compare that listing with the output of a find command run against /modelsim on my machine so I can look for the name of a file missing on my machine? (Just kidding! I'm going to Silos 3 now.)Article: 33506
"Rick Filipkiewicz" <rick@algor.co.uk> wrote in message news:3B631FA5.3510C44F@algor.co.uk... > > > Dave Feustel wrote: > > > The modelsim licensing program never asked me for the name > > of the file containing the license. I think the problem is more > > basic than that. And at this point I am pretty fed up with the > > entire licensing fiasco that I have been experiencing. > > It would seem that radical measures are called for. (Tongue in cheek here) If you can afford the upfront outlay why > not travel to Xilinx headquarters bearing your machine & the eval CD, get into the support area, and chain yourself to > the release managers desk until they sort it & re-imburse the costs - if necessary also the ones associated with any > HD reformat that might be needed. Actually this problem would pretty much seem to be Modelsim's doing, although I also gave up on installing Xilinx Foundation 3.3i eval software because of (apparently) unfixable problems with Xilinx licensing. > After succeeding there you move on to ModelSim. The lack of any sensible information about errors is absolutely > typical of anything that's been touched by Visual C/C++. If its not license.dat the only way to get any further is to > install some cheapo version VC/C++ and trigger the debugger on the error. Using Visual C doesn't prevent the programmer from emiting useful and informative error messages. Of course, neither does it guarantee that such error messages will be emitted. > One possibility occurs. From time to time I've edited the license.dat file with wordpad to add a new year's license > that's arrived by email. If I select ``Save as plain text'' what happens is that a new file called ``license.dat.txt'' > is created but Explorer cannot handle this so only displays ``license.dat''!? > You can only see the error via the NT shell's DIR command. No more problems now I'm using the Xemacs on both the PC & > the Unix box. > > <Flame> > Does anyone but me find this idea utterly disgraceful that some s/w can do irreversible things to my HD that > effectively trashes it if I just want to set my clock a bit more accurately? This isn't license protection its the > rampant paranoia behind the ``Digital Millenium Copyright'' act that Adobe used recently on what appears to be a > relatively innocent Russian. > > Xilinx I think don't do this,at the price of ``You don't buy the s/w you rent it''. > > <Flame turned down - a bit> > > Silos2001demo installed in about 30 seconds and it runs. :-)Article: 33507
Hi, In my application the FPGA is generating sampling clocks for various ADC's and DAC's. I was planning to use a divide by N counter then divide by 2 to generate the 50% duty cycle clock. I am wondering if there is any analysis I can do to predict how much jitter the counter will add to my ADC clock? It may be trivial for our application but I'm just not sure. The ADC max sampling rate is 8MHz, the ADC device itself has 50 ps aperture jitter. (I notice a DLL adds 60ps max jitter, not that a DLL is part of the clock chain in my design) Chip is XC2S100/200, Foundation ISE. Thanks AndrewArticle: 33508
> So it appears that both the Xilinx Foundation ISE install program > and now the Modelsim licensing program like to let their customers guess > what's wrong when the software won't install rather than just explicitly identify > the cause of the failure. I had a problem with running Xilinx Student Edition 2.1i under Win2000Pro. The application program worked fine, but the flexlm client didn't seem to know how to query Win2000 my ethernet-node address (the diagnostic tool said my address was 'FF.FF.FF.FF.FF' ?!?) That said, you can download the latest flexlm client package from http://www.globetrotter.com. Of course, you have to 'hunt down' the corresponding EXE/DLL files in the Modelsim/Xilinx install directories, then manually replace them (I think.) If they're embedded, or renamed, then well, good luck... The only other thing I can think of, which is probably NOT the cause, but you could check anyway... make sure you have set the LM_LICENSE_FILE environment variable from a MSDOS (not WinNT/2000) autoexec.bat file, SET LM_LICENSE_FILE = <path to license.dat> IN Win2000, I think you set these 'legacy' environment variables from the system setup control panel. Spawning a DOS-shell, typing the line in, then exiting, won't work because the variable is only active for that DOS session. When you download the flexlm-client from www.globetrotter.com, you should run the LMUTIL program and verify that FLEXLM can find&read your license file. > Welcome to the Brave New World of Software Licensing > > Any other alternatives to Modelsim?Article: 33509
Give "Verilogger Pro" a try. Same GUI front-end (with an HDL text editor), timing waveform entry and all sorts of goodies! http://www.syncad.com Very competitive pricing, too. Modelsim/PE was, what, $5000? > Modelsim licensing refuses to work on my computer. > > What alternatives to Modelsim are there for Verilog simulation > on Windows 2000?Article: 33510
"Steven K. Knapp" wrote: > > You might find some useful information on the Programmable Logic Jump Station. > > VHDL and Verilog Tutorials > http://www.optimagic.com/tutorials.html > > Free Software Page > http://www.optimagic.com/lowcost.html > > Philipp Krause <pkk@spth.de> wrote in message news:<3B594569.9000504@spth.de>... > > Are there any free tools around? I'd like to learn VHDL, but don't want > > to spend money on commercial software since I don't know which chip > > family I'll use when it comes to implementing something. > > > > Philipp Krause The xilinx webpack, or altera-leonardo spectrum. -- ___ ___ / /\ / /\ / /__\ Russell Shaw, B.Eng, M.Eng(Research) / /\/\ /__/ / Victoria, Australia, Down-Under /__/\/\/ \ \ / http://home.iprimus.com.au/rjshaw \ \/\/ \__\/ \__\/Article: 33511
Here's another link that may be of interest. The Programmable Logic Jump Station maintains a set of links to free evaluation software. It includes various CPLD/FPGA software, synthesis tools, tutorials, etc. http://www.optimagic.com/lowcost.html There are also synthesis tutorials at http://www.optimagic.com/tutorials.html All the best in finding a new position. Keep the faith! When the eventual turn-around comes, it will be programmable logic leading the way! "Speedy Zero Two" <david@manorsway.freeserve.co.uk> wrote in message news:<9juqde$nua$1@news8.svr.pol.co.uk>... > FH, > > Try http://www.xilinx.com/sxpresso/webpack.htm > It's all free but you may have to register. > Dave > > "feather head" <shyboy1@bellsouth.net> wrote in message > news:jtm5mtsmvo1p2ums2on744nfreb3punhfh@4ax.com... > > I was recently laid off from an employer due to a downturn in tech > > industries. > > During the time between jobs I would like to improve my base skills in > > FPGA design and programming. > > Could someone please post some xilinx design software. > > thanks, This will help me find a job. I own a copy of OrCad 7.2 > >Article: 33512
If this is the problem why hasn't Modelsim been fixed to work with Windows 2000? "Jjdur Ukfjg" <nnvh@htkd.net> wrote in message news:3B6361F5.3E4DB801@htkd.net... > > So it appears that both the Xilinx Foundation ISE install program > > and now the Modelsim licensing program like to let their customers guess > > what's wrong when the software won't install rather than just explicitly identify > > the cause of the failure. > > I had a problem with running Xilinx Student Edition 2.1i under > Win2000Pro. > The application program worked fine, but the flexlm client didn't seem > to > know how to query Win2000 my ethernet-node address (the diagnostic tool > said my address was 'FF.FF.FF.FF.FF' ?!?) > > That said, you can download the latest flexlm client package from > http://www.globetrotter.com. Of course, you have to 'hunt down' the > corresponding EXE/DLL files in the Modelsim/Xilinx install directories, > then manually replace them (I think.) If they're embedded, or renamed, > then well, good luck... > > The only other thing I can think of, which is probably NOT the cause, > but > you could check anyway... > > make sure you have set the LM_LICENSE_FILE environment variable > from a MSDOS (not WinNT/2000) autoexec.bat file, > > SET LM_LICENSE_FILE = <path to license.dat> > > IN Win2000, I think you set these 'legacy' environment variables from > the > system setup control panel. Spawning a DOS-shell, typing the line in, > then exiting, won't work because the variable is only active for that > DOS session. > > When you download the flexlm-client from www.globetrotter.com, you > should run the LMUTIL program and verify that FLEXLM can find&read your > license file. > > > Welcome to the Brave New World of Software Licensing > > > > Any other alternatives to Modelsim?Article: 33513
Jjdur Ukfjg wrote: > > > So it appears that both the Xilinx Foundation ISE install program > > and now the Modelsim licensing program like to let their customers guess > > what's wrong when the software won't install rather than just explicitly identify > > the cause of the failure. > > I had a problem with running Xilinx Student Edition 2.1i under > Win2000Pro. > The application program worked fine, but the flexlm client didn't seem > to > know how to query Win2000 my ethernet-node address (the diagnostic tool > said my address was 'FF.FF.FF.FF.FF' ?!?) Try installing IPX/SPX protocol in windows to fix that. > That said, you can download the latest flexlm client package from > http://www.globetrotter.com. Of course, you have to 'hunt down' the > corresponding EXE/DLL files in the Modelsim/Xilinx install directories, > then manually replace them (I think.) If they're embedded, or renamed, > then well, good luck... > > The only other thing I can think of, which is probably NOT the cause, > but > you could check anyway... > > make sure you have set the LM_LICENSE_FILE environment variable > from a MSDOS (not WinNT/2000) autoexec.bat file, > > SET LM_LICENSE_FILE = <path to license.dat> > > IN Win2000, I think you set these 'legacy' environment variables from > the > system setup control panel. Spawning a DOS-shell, typing the line in, > then exiting, won't work because the variable is only active for that > DOS session. > > When you download the flexlm-client from www.globetrotter.com, you > should run the LMUTIL program and verify that FLEXLM can find&read your > license file. > > > Welcome to the Brave New World of Software Licensing > > > > Any other alternatives to Modelsim? -- ___ ___ / /\ / /\ / /__\ Russell Shaw, B.Eng, M.Eng(Research) / /\/\ /__/ / Victoria, Australia, Down-Under /__/\/\/ \ \ / http://home.iprimus.com.au/rjshaw \ \/\/ \__\/ \__\/Article: 33516
don't miss FPL 2001 ! August 27 - 29, 2001 at Belfast, Northern Ireland tutorials by Peter Alfke, Xilinx / Pat Mead, Altera: Recent progress in FPGAs / System-On-a-Programmable-Chip (SOPC) homepage: http://www.ee.qub.ac.uk/dsp/fpl2001/ links to keynotes, tutorials, highlights, also see: http://www.fpl.uni-kl.de/fpl/index.html#fpl2001 Reiner HartensteinArticle: 33517
I've decided to market the little Flex 10K10 design kit I originally designed for my own amazement: http://www.leonheller.com/lfh.html I'll also be putting the design files into the public domain. Whilst it isn't big enough for any of the sexy FPGA CPUs that are floating around, it is suitable for learning about programmable logic at very little cost. I've implemented the small 8-bit CPU in Hamblen and Furman's book on its precursor. I'll be doing a similar design for one of the larger Spartan-II chips. LeonArticle: 33518
Jan Martin wrote: > > Hi, > > I believe they only transfer through an FTP site from there. If I am not mistaken Xilinx used > to have HTTP download possibilities on a 'documentation' page on their site, which used to be > accessible from the downloads page of the updates. > I also tried to download individual files and then tried to recombine using the batch file, > but have never been able to get it to work. I now download using an FTP program. Advantage is > that the 'resume' option of the FTP site does work; with some 80Mb to download on a telephone- > line.... > > You may want to try installing a FTP program (CuteFtp for example) and use that to download > the one large file. > > Cheers, > Jan Martin Wagenaar > > In article <3B5C2513.7030409@amontec.com>, laurent.gauch@amontec.com says... > > I am on > > http://support.xilinx.com/support/techsup/sw_updates/31i/sw_f33i_pc.htm > > trying to download the Foundation 3.3i Software Updates for PC (3.3i > > service pack 8), but I cannot download these single files. Why? > > > > Or you might try asking Xilinx to send you the update on CD. I think it is rediculous that Xilinx thinks everyone has a high speed connection to the web or that they have the patience to spend several nights trying to download these huge files. Is there some reason that Xilinx can't split them up into multiple smaller files? 5 MB chunks would be much easier to download. With my FTP program I can select them all for download and it will do them sequentially which maximizes the probability of sucess on them all. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 33522
cyber_spook wrote: > > Hi, > > Rick Filipkiewicz wrote: > > > My conclusion from this small sample is that the P&R tool speed is > > dominated by memory performance. > > With this type of application (memory hugary!) the speed of the CPU is only > any good when it has the data to process. In other words a 450, 600 or 1.4 > will just spend most of its time sitting on its "bum" waiting for memory. > > This was proven when Cambridge Uni fitted 4Gb of SRAM (not DRAM) to a 40Mhz > 386DX - Was the fastest thing you have ever seen!! > > Cyber_Spook_Man I find this hard to believe. I don't doubt that the general rule for memory is faster is better. But I don't think a 40 MHz 386 will outrun a 1 GHz anything just because the 386 is running in zero wait state memory. I also find it hard to believe you can fit 4 Gb of SRAM to a processor without slowing down the SRAM. That is a lot of memory, about 512 chips (assuming the Gb means gigabits, not gigabytes)!!! It would be useful to obtain benchmarks on some different platforms. I can easily access a 1 GHz Intel machine (2 GB) and some slower Intel machines (1 GB and less) with Foundation 3.3i. Anyone have a design that they would like to use as a test case? Of course, the other variable is the design. Even if we come up with a common design to test, other designs may perform differently across the different platforms. But this may only be a very slight difference. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 33523
The coverage that the FPGA vendors provide is less than perfect but it's good enough for most applications. In my experience, writing FPGA test programs for an ASIC emulator manufacturer, about 1 in 50 FPGAs have some defect although the chance of any one pattern running into that defect is in the neighborhood of 1 in 100. As a result the chance that any one pattern will have a problem on any particular FPGA is about 1 in 5000. As you raise the number of patterns that you run on a particular FPGA the chances that you will run into a problem approached the 1 in 50 number. The way that you test FPGAs is different then the way that you test an ASIC. FPGAs are mostly interconnect which makes them harder to test. On the other hand because they are soft you can run an unlimited number of different test patterns on them, which simplifies the problem as compared to an ASIC. If you are concerned about shipping an FPGA with a hidden defect then the way that you solve it is to run a large number of test patterns on your FPGAs and throw out the bad ones. The FPGA vendors do some of this but they are limited by the amount of time that they can tie up a chip tester for. Generally the vendor tests runs in under a second, in my experience it takes about 20 minutes to really test an FPGA. If you are selling low volume high value equiptment that contains a large number of FPGAs and loads many different patterns into them, like and ASIC emulator, then this degree of testing is necessary. If you are shipping high volume low priced boards then it's cheaper to live with the one in 5000 fall out. Adding scan logic to a particular circuit is useless because any change to the pattern, including another place and route on the same design, will change which resources are used inside of the FPGA. In article <996308678.26850.0.nnrp-07.9e9832fa@news.demon.co.uk>, "Tim" <tim@rockylogic.com.nospam.com> wrote: > "Andy Botterill" <csm@plymouth2.demon.co.uk> wrote in message > news:YNNvDUAmacY7EwX0@plymouth2.demon.co.uk... > >> >Programmable parts have different test requirements to ASICs, so I >> >guess the answer to your question is Yes. >> >> If you cannot insert scan into an FPGA how do you get a high fault >> coverage? If you have a poor fault coverage you will be shipping >> defective parts which is not good for your business. > > The FPGA manufacturers do this for you. They use a combination of the > reprogrammability of the part and, presumably, a few undisclosed test > structures. > > The result is closer to 100% tested than just about any ASIC. All you > have to worry about is logical and timing errors :) > > > > >Article: 33524
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