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The webpack files *are* available as single files at http://www.xilinx.com/webpack. The entire file collection is ~175 MB. You can get by with much less if you only download for specific chips (e.g. Spartan or Virtex). The 3.8 service pack is already applied to these modules. Only the Webpack Modelsim exes require licenses. Since Modelsim licensing for these modules is broken on my machine, I downloaded the Silos demo program instead. Now I'm looking for a webpack tutorial to help me get started programming my Spartan-II and Virtex-II chips. "Rick Collins" <spamgoeshere4@yahoo.com> wrote in message news:3B643C56.69A30F38@yahoo.com... > Or you might try asking Xilinx to send you the update on CD. I think it > is rediculous that Xilinx thinks everyone has a high speed connection to > the web or that they have the patience to spend several nights trying to > download these huge files. Is there some reason that Xilinx can't split > them up into multiple smaller files? 5 MB chunks would be much easier to > download. With my FTP program I can select them all for download and it > will do them sequentially which maximizes the probability of sucess on > them all. > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAXArticle: 33551
John Larkin <jjlarkin@highlandSNIPTHIStechnology.com> wrote in message news:<QF5QO=H9HmaE7PjpmwudSPnn48ZG@4ax.com>... > On Tue, 10 Jul 2001 19:14:29 +0200, Falk Brunner <Falk.Brunner@gmx.de> > wrote: > > >Lionel DORIS schrieb: > >> > >> I would like to know which is state of all I/Os before the configuration is > >> loaded in FPGA. > > > >They are all tristated. > > > > But beware 'dual use' pins like HDC and LDC! > > John All the output pins except for those used for configuration are tri-stated + weakly pulled-up (about 80K or so) before and during the device configuration.Article: 33552
You're trying to do all the work for the synthesizer by telling it how to perform addition. Let the synthesizer to the addition - you just concentrate on the saturable aspect. Leonardo spectrum should get all the carry chains together fine because it know how to utilize them to add. Russell Shaw wrote: > Hi all, > > I made this saturable adder from converting AHDL code in a previous > message. > > It adds signed HEX numbers together, but doesn't roll-over if there's > an overflow. > > I'm using leonardo-spectrum to generate an edif netlist, which is > compiled by altera maxplus2. > > Where and how, if any, can i add technology-dependent optimizations > such as carry chains etc? > > Also, are there such things as VHDL debuggers where you can single- > step thru the code and see what all the signals and variables are > doing? > > LIBRARY ieee; > USE ieee.std_logic_1164.all; > > PACKAGE types IS > subtype word is std_ulogic_vector(3 downto 0); > END types; > > LIBRARY ieee; > USE ieee.std_logic_1164.all; > use work.types.all; > > ENTITY saturable_adder IS > port( > a,b: in word; > s: out word > ); > END adder; > > LIBRARY ieee; > USE ieee.std_logic_1164.all; > use work.types.all; > > ARCHITECTURE total OF saturable_adder IS > BEGIN > behav: PROCESS (a,b) is > variable sum: word; > variable carry_in,carry_out: std_ulogic; > constant msb:integer:=word'left; > > BEGIN > carry_in:='0'; > for ndx in 0 to (word'left-1) loop > sum(ndx):=a(ndx) xor b(ndx) xor carry_in; > carry_out:=(a(ndx) and b(ndx)) or (a(ndx) and carry_in) or (b(ndx) > and carry_in); > carry_in:=carry_out; > end loop; > sum(msb):=a(msb) xor b(msb) xor carry_in; > if( (a(msb) and b(msb) and not carry_in)='1' ) > then > sum:=(others=>'0'); > sum(msb):='1'; > elsif( (not a(msb) and not b(msb) and carry_in)='1' ) > then > sum:=(others=>'1'); > sum(msb):='0'; > end if; > s<=sum; > END PROCESS behav; > END total; > > -- > ___ ___ > / /\ / /\ > / /__\ Russell Shaw, B.Eng, M.Eng(Research) / /\/\ > /__/ / Victoria, Australia, Down-Under /__/\/\/ > \ \ / http://home.iprimus.com.au/rjshaw \ \/\/ > \__\/ \__\/Article: 33553
This is a multi-part message in MIME format. --------------DE2A80CB0683D6E94873AC15 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Rick, The solution record that sumarizes IOB FF packing is at: http://support.xilinx.com/techdocs/2207.htm I found it by typing in -pr (the switch in Map to pack registers) as the search word and it came up as the first record. I do understand how it can be hard to find what you are looking for though. -- Brian Rick Collins wrote: > Rick Filipkiewicz wrote: > > I've been working around this for some time by maintaining a list of what I > > expect to see in the IOBs > > and using a perl script to compare that with the last section of the MAP > > report. The list, in fact, holds exceptions to the rule that everything is > > registered onto & off the chip i.e. the default is to see INFF/OUTFF on an > > input/output (or both on a bidir - the script parses the top level module to > > get a list of the IOs). > > I am dealing with this problem right now. I can't seem to find the > earlier posts on this topic that would have covered the details that can > prevent an inferred FF from being moved to the IOB. I know you can't use > the async S/R (other than via GSR) and you can't use the output for any > other logic for an OFDX. A manager who has worked this design says you > can't even source the FF from internal logic, but rather it has to be > connected to another FF output. Anyone know about this? > > I looked through a hundred or so results in the Xilinx data base, but > could not find a doc that summarizes all of the things that are required > to let a FF be placed in the IOB. Our parts are 4000XLA. > > Anyone care to take a stab at this list? > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAX --------------DE2A80CB0683D6E94873AC15 Content-Type: text/x-vcard; charset=us-ascii; name="brian.philofsky.vcf" Content-Transfer-Encoding: 7bit Content-Description: Card for Brian Philofsky Content-Disposition: attachment; filename="brian.philofsky.vcf" begin:vcard n:Philofksy;Brian x-mozilla-html:TRUE org:Xilinx, Inc.;System Level & Alliance Marketing adr:;;;;;; version:2.1 email;internet:brian.philofsky@xilinx.com title:Technical Marketing Engineer fn:Brian Philofksy end:vcard --------------DE2A80CB0683D6E94873AC15--Article: 33554
Hi Rick, I have the TestBench product guys at IBM telling me that the output from the ngd2ver is "behavioral", not "structural". Paul On Fri, 27 Jul 2001 19:17:38 +0100, Rick Filipkiewicz <rick@algor.co.uk> wrote: > > >Rick Filipkiewicz wrote: > >> Paul Smart wrote: >> >> > Hi All, >> > >> > I was wondering if anyone can shed some light on this: >> > >> > The Xilinx and Altera tools seem to produce a behavioral verilog file >> > for simulation. Is there any way I can get a structural verilog file? >> > >> >> You need to go all the way through to place & route and then >> >> (1) Run NGDANNO on the routed database .ncd file => a timing >> backannotated .nga file. >> >> (2) Use the .nga + .ngm from the MAP stage as input to NGD2VER to get a >> post-route structural netlist based on the ``simprims'' library. Also >> outputs an SDF file. >> >> Details are in the ``Development System Reference Guide'' aka >> dev_ref..pdf aka the Xilinx P&R Bible part I. [Part II is the Libraries >> guide]. >> >> If you are not worried about timing info you can run NGD2VER on the .ngd >> output from NGDBUILD. > >I should of course have begun this as ... for Xilinx devices ...Article: 33555
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(+)--(z)----(+)--(z)----(+)--(z)---(+)----->
Excuse the poor ascii art. The (z)'s are the delays, (+) are combinatorial adds. If
the system is 1 clock per sample, then using registered adders combines the (z) and the
(+) so the adders are connected in a chain. The input at the top is actually your
coefficient times the input, but since the input is +/-1 in your case then it reduces to
an add subtract control for each adder, with the adder a and b inputs connected to the
coefficient and the previous adder respectively.
Antonio wrote:
> Hy Ray,
> can you better explain where I've to put the delay of the adder??
>
> Ray Andraka <ray@andraka.com> wrote in message news:<3B590A8D.AE5DCA72@andraka.com>...
> > Oops, pushed the send too fast....
> >
> > Antonio wrote:
> >
> > > 3) If for example one input of the multiplier is 10 bits, also the
> > > other must be ten bits ?? and how much for the output ???
> >
> > No, you can have both inputs have arbitrary sizes. I believe the latest
> > Xilinx core generator allows you to set the widths of the inputs
> > independently. In your case, you do not need multipliers: each
> > coefficient is a constant that you are either adding to or subtracting
> > from the sum of products (you are multiplying by either 1 or -1), so
> > instead, use adder/subtractors with the signal input controlling the a/s
> > control. Since this is a filter, the signal is delayed in a tapped delay
> > queue. You can transpose the delay to the output side of the filter,
> > which allows you to perform the adds in a chain, then the structure is a
> > chain of adder/subtractors that have one input connected to a constant
> > coefficient, and the other to the output of the previous adder in the
> > chain.
> >
> > >
> > >
> > > 4) By the way , it is important that the inputs of the multiplier have
> > > the same rate ??
> >
> > No, but they should both change as a result of transitions on the same
> > clock signal. For example, one input can change on every clock cycle
> > while the other only changes every 4th cycle. The multiplier in an FPGA
> > is generally deeply pipelined (takes several clocks before the product of
> > the inputs appears on the output).
> >
> > >
> > >
> > > 5) if for example the input of the following adder are both 10 bits,
> > > how much bits I've to provide for the output.
> >
> > In your case, you know the values at the input of the adders, since they
> > are constants. From these, you can compute the maximum value at the
> > output of each adder, which in turn tells you how many bits of
> > significance you need at that node. For example, the coefficient
> > mentioned above (previous post) could be represented with only 11 bits
> > instead of the 16 without loosing any more precision than the original
> > quantization. If you add that with another coefficient of similar
> > magnitude, you will likely need 12 bits to represent the largest possible
> > sum without overflow.
> >
> > >
> > >
> > > I know many of these question could be stupid , but, how I can say,
> > > I've not the answer so if you have some answer also only at some of
> > > them I'll be really happy if you tell it to me or also if you redirect
> > > me to some resource speaking strictly about these thinghs ...
> > >
> > > Antonio D'Ottavio
--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
Article: 33556Jjdur Ukfjg wrote: > > Give "Verilogger Pro" a try. Same GUI front-end (with an HDL > text editor), timing waveform entry and all sorts of goodies! > > http://www.syncad.com I like Timing Designer and Waveformer Pro, but as a full-blown simulation tool, I don't think the Synapticad tools are up to the level of ModelSim. F'rinstance, try simulating your entire board (FPGAs, RAMs, bus-interface chips, etc.) in Verilogger. > Very competitive pricing, too. Modelsim/PE was, what, $5000? Verilogger ain't much cheaper. -aArticle: 33557
Jjdur Ukfjg wrote: > The only other thing I can think of, which is probably NOT the cause, > but > you could check anyway... > > make sure you have set the LM_LICENSE_FILE environment variable > from a MSDOS (not WinNT/2000) autoexec.bat file, > > SET LM_LICENSE_FILE = <path to license.dat> > > IN Win2000, I think you set these 'legacy' environment variables from > the > system setup control panel. Spawning a DOS-shell, typing the line in, > then exiting, won't work because the variable is only active for that > DOS session. You set environment variables by using the System control panel. Set LM_LICENSE_FILE in both the user and the system-wide (administrator) sections. THEN REBOOT (very important). Even though you might think that the new environment variables take effect immediately, they don't. Since it's Windows, you must reboot. -andyArticle: 33558
Even at a 1 in 25000 rate I'd expect to see several failures in my own stuff, which I have not. At even 10 times that (1 in 250,000), there would be enough of an outcry in the industry to be at least heard. There is none. I don't throw boards on a "dog pile" until I have tested them sufficiently to pinpoint and prove WHY they are failing...if you get a failure on a lab sample you can be darned sure that failure is going to be a frequent problem in the field. My experience, and I am sure most of the others here have the same experience, is that if the design passes a _rigorous_ static timing analysis, it will behave the same in functional simulation as it does in the chip (when it doesn't you either missed something in the timing analysis or you haven't matched the initialization in the simulations). Is there any chance of you posting your test code so that it can be scrutinized? If you are going to claim such extreme failure rates, let's see the backup for your claim. "B. Joshua Rosen" wrote: > I've got these figures based on the tests that I have written for an > ASIC emulator company. Each box has hundreds of FPGAs so we would typically > find several bad FPGAs per system. I don't have exact figures for the > Virtex family, although they seem to be better than the 4000 > family, but the 1 in 50 number held for various incarnations of the > 5200 and 4000 series. My tests do not violate any timing restrictions, in fact we > run them at various clock rates and failures happen at the lowest speeds > as well as for the higher speeds. Before adding these tests we would > frequently run into problems with customer patterns, now that's much > much rarer although it can still happen occasionally. Even with about 150 > test patterns we are only getting coverage of 93% of the PIPs, although > the coverage of the PIPs that we actually use is probably closer to 99%. > Xilinx has added tests to their test suites which use the same methodology as > my tests and it does seem that the Virtex parts have a lower fallout than > the older families. I've also used a Xilinx internal tool to determine > what my coverage is. I could be wrong about the chances of a particular > pattern hitting a defect but I'm not wrong about defect rate. With my > test patterns I will generally see 2 or 3 patterns fail on a bad part > out of a suite of approximately 150. However my patterns are designed for > maximum coverage, it's possible that a typical pattern has only a 1 on > 500 chance of seeing the defect as opposed to the 1 in 50 that I see. So > if 1 in 50 parts has a defect and 1 in 500 patterns hits it then you > would see a 1 in 25000 fallout in real systems. If my test patterns are > closer to the real world then the system fallout rate would be 1 in 2500. > Either way the system fallout rate is low enough that you wouldn't notice > it. Also without a test suite like I wrote for the emulator company you > would have no way of knowing that it was the FPGA that caused the > problem, the board will simply be declared a dog and tossed aside on the > dog board pile. > > In article <3B649C58.D09F96FC@andraka.com>, "Ray Andraka" > <ray@andraka.com> wrote: > > > Where are you getting these numbers from? My experience with FPGAs over > > the past 13 years and several hundred designs certainly doesn't support > > such numbers. Is it possible you might have been violating timing??? > > What devices were you testing? > > > > "B. Joshua Rosen" wrote: > > > >> Date codes don't matter it's really a random process that causes > >> problems. Having several boards is certainly useful in development but > >> you would probably do that anyway. As I say the chances of actually > >> hitting a problem are low, but if you go through 10 ro 20 spins you > >> will likely have a one in a few hundred chance of hitting a defective > >> switch. > >> > >> Josh > >> > >> In article <3B6477B1.575B@designtools.co.nz>, "Jim Granville" > >> <jim.granville@designtools.co.nz> wrote: > >> > >> > B. Joshua Rosen wrote: > >> >> > >> >> The coverage that the FPGA vendors provide is less than perfect but > >> >> it's good enough for most applications. In my experience, writing > >> >> FPGA test programs for an ASIC emulator manufacturer, about 1 in 50 > >> >> FPGAs have some defect although the chance of any one pattern > >> >> running into that defect is in the neighborhood of 1 in 100. As a > >> >> result the chance that any one pattern will have a problem on any > >> >> particular FPGA is about 1 in 5000. As you raise the number of > >> >> patterns that you run on a particular FPGA the chances that you will > >> >> run into a problem approached the 1 in 50 number. > >> >> > >> >> The way that you test FPGAs is different then the way that you test > >> >> an ASIC. FPGAs are mostly interconnect which makes them harder to > >> >> test. On the other hand because they are soft you can run an > >> >> unlimited number of different test patterns on them, which > >> >> simplifies the problem as compared to an ASIC. If you are concerned > >> >> about shipping an FPGA with a hidden defect then the way that you > >> >> solve it is to run a large number of test patterns on your FPGAs and > >> >> throw out the bad ones. > >> > <snip> > >> > > >> > Very interesting stats. > >> > Besides shipping product, this also has issues for development > >> > itself. > >> > With a 1:50 chance of a defect, it would make sense to have two, > >> > or maybe three, (and probably with different date codes), test boards > >> > that are called on for second opinions when a curly fault arises. > >> > As these boards rack up more 'passes', they increase in value :-) > >> > > >> > Sounds like the tools could benefit from a 'randomise' switch > >> > - or maybe a start-from-other-corner placement alogrithm ? > >> > > >> > -jg > > > > -- > > -Ray Andraka, P.E. > > President, the Andraka Consulting Group, Inc. 401/884-7930 Fax > > 401/884-7950 > > email ray@andraka.com > > http://www.andraka.com > > > > -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.comArticle: 33559
Hi I have a problem. I have XILINX Foundation Software v1.3 . I have FLEXlm license. I work under Windows NT. When I want to create ".bit" file I have error: map -p xc4005xl-3-pc84 -o map.ncd ../xc4000xl.ngd vgatst.pcf map: version M1.3.7 Copyright (c) 1995-1997 Xilinx, Inc. All rights reserved. par -w -l 4 -d 0 map.ncd vgatst.ncd vgatst.pcf PAR: Xilinx Place And Route M1.3.7. Copyright (c) 1995-1997 Xilinx, Inc. All rights reserved. ERROR:baspw:110 - Cannot find Input file "map.ncd". Please verify that your paths and permissions are properly set for this file. Why? This error shows even when I created simple LED decoder. I can't work because I can't generate file. TomekArticle: 33560
David Wright wrote: > > I just got done using the Cypress Warp 6 on my project. It was a no go. > After fighting problems a couple of weeks, tech-support left me holding the > bag. Evidently, split-busses do not work on CPLD's (no compile). Can't use > /x/ identifiers in VHDL on some compilers. Other problems. Cost $175 for > Warp plus $300 for parts. Not sure if Cypress or their distributor will > take them back. Last time I looked at the Warp software (v5.1?), it had abysmal language support. So much so that it was nowhere near worthwhile switching from Brand X, whose tools were far superior (and probably still are). Cypress also has a nasty tendency to put parts on their end-of-life list without informing anyone -- including their local sales reps. Go look on their web page and see if there are any parts that are obviously EOLed. They could learn a lesson from National Semiconductor, whose home page has a big bold link to Obsolete Parts. Fuck 'em. --a PS: for at least the PAST THREE YEARS, the Cypress web site has had a link to something called CySolutions (http://www.cypress.com/design/support/cysolutions/index.html), and it you venture the link, you get an interesting message: "CYSolutions is currently not available. We are currently working on a new release. More information to be released soon. "For further technical assistance you can either contact the applications hotline at (408)943-2821 or send email to cyapps@cypress.com. "We regret any inconvenience this may cause." I mean: THREE YEARS!Article: 33561
Thanks to all who responded. The following "threads" of thought have been discussed (so far): ---------- The output of ngd2ver is considered "behavioral" by at least one ATPG tool vendor (IBM TestBench product). Some tools can work with behavioral verilog, some tools cannot work with non-scan architecture. ---------- "Timing errors in placed and routed design" This illustrates why the manufacturer cannot 100% test, as he is not testing the customers exact placed and routed design. My customer may see failures in the system. ---------- "Manufacturers do the testing for you" Shortcuts *may* be taken by the FPGA manufacturer to reduce the cost of test, and the customers design can never be 100% tested for (unless it is one of the test designs, and is a 100% testable design). My customer may see failures in the system. ---------- "Parts are not 100% testable (absence of scan or other DFT tools)" " DPM levels" My customer is in the following categories: -Comparatively high volume of FPGA's per board/system -Comparatively low volume of systems -Extremely high system reliability requirements My customer DOES see significant failures in boards/system (100's of devices per month) They experience DPM from 300-500 (reasonable) 1000-5000 (painful) 5000-10,000 (extreme production impact) These failures are uncovered during the thorough board level and system level testing perfomed during manufacturing. DPM in the 1000 to 2000 range are common. They have seen as high as 50,000 DPM in an extreme case (design routing problem (caused by software?) was identified). Die steps and new generation devices see higher failure rates initially, and then scale back over time (product maturity?). Many of the failed components cannot be verified as rejects by the manufacturer (the manufacturers test methods missed the problem). This applies to both X and A, my customer is a large user of both. ---------- My ideal first goal would be to have the verilog output from the tools be directly usable with existing ASIC ATPG tools, specifically those that can work with non scan designs. It is not a final solution, but it is a step in the right direction. DFT tools for FPGA might be the next step. Given that this problem does not significantly affect all users of FPGAs, I don't know how reasonable it is to expect such tools to become a reality in the near future. My end goal is to test and remove as many defects as possible at the component level, before my customer places them on a board. It remains to be seen how we will get there.Article: 33562
Hi, colleague, are there multi context FPGAs on the market having 2 or 4 banks of configuration memory ? ReinerArticle: 33563
Huang wrote: > Is there any difference between Virtex and Virtex2 regarding SRL16? Yes, there is: Virtex SRL16s have only one output, the one defined by the register length code applied to the address pins. Virtex-II has that same output, but also adds a cascading maximum-length output. This makes it much easier to cascade SRL16s, since the cascade output is not affected by the applied address. See bottom paragraph on page 50 of the Virtex-II Handbook. Otherwise no difference. Peter Alfke, Xilinx ApplicationsArticle: 33564
In article <790bmt8rcd74obc5l6bn7dof5s3pr829a8@4ax.com>, Paul Smart <pablo*@*maine.rr.com> writes >---------- >"Parts are not 100% testable (absence of scan or other DFT tools)" >" DPM levels" > >My customer is in the following categories: >-Comparatively high volume of FPGA's per board/system >-Comparatively low volume of systems >-Extremely high system reliability requirements Have you considered using an FPGA to validate the logic and then converting it to an ASIC. Do your overall volumes justify this option? > >My customer DOES see significant failures in boards/system (100's of >devices per month) > >They experience DPM from >300-500 (reasonable) >1000-5000 (painful) >5000-10,000 (extreme production impact) > >These failures are uncovered during the thorough board level and >system level testing perfomed during manufacturing. > >DPM in the 1000 to 2000 range are common. > >They have seen as high as 50,000 DPM in an extreme case (design >routing problem (caused by software?) was identified). > >Die steps and new generation devices see higher failure rates >initially, and then scale back over time (product maturity?). > >Many of the failed components cannot be verified as rejects by the >manufacturer (the manufacturers test methods missed the problem). This >applies to both X and A, my customer is a large user of both. > >---------- >My ideal first goal would be to have the verilog output from the tools >be directly usable with existing ASIC ATPG tools, specifically those >that can work with non scan designs. It is not a final solution, but >it is a step in the right direction. Surely RTL can be synthesised for an FPGA or an ASIC? > >DFT tools for FPGA might be the next step. Given that this problem >does not significantly affect all users of FPGAs, I don't know how >reasonable it is to expect such tools to become a reality in the near >future. > >My end goal is to test and remove as many defects as possible at the >component level, before my customer places them on a board. It remains >to be seen how we will get there. > -- Andy BotterillArticle: 33567
Yip, I agree. But I believe Xilinx thinks this is easier for us customers. We now do not have to download all them servicepacks from days gone by, just the latest. Ah well. In my humble opinion it would be nice service from Xilinx to send the CD to registered user's anyway. I paid a lot for the software, registered a zillion times for software and the XIlinx sites. But well. For the time being I will simply annoy my valued colleagues the network administrators, as I will be stalling our companies internet access each time a service pack arrives. > Or you might try asking Xilinx to send you the update on CD. I think it > is rediculous that Xilinx thinks everyone has a high speed connection to > the web or that they have the patience to spend several nights trying to > download these huge files. Is there some reason that Xilinx can't split > them up into multiple smaller files? 5 MB chunks would be much easier to > download. With my FTP program I can select them all for download and it > will do them sequentially which maximizes the probability of sucess on > them all. > >Article: 33568
Tomek, The quick answer is to check you path, I beleive that there could be some problems with certain characters , such as space and # etc. Do a simple project with a simple path will check this Dave "Tomek" <tbednar@poczta.onet.pl> wrote in message news:3b65990e$1@news.vogel.pl... > Hi > I have a problem. I have XILINX Foundation Software v1.3 . I have FLEXlm > license. I work under Windows NT. > When I want to create ".bit" file I have error: > > map -p xc4005xl-3-pc84 -o map.ncd ../xc4000xl.ngd vgatst.pcf > map: version M1.3.7 > Copyright (c) 1995-1997 Xilinx, Inc. All rights reserved. > > par -w -l 4 -d 0 map.ncd vgatst.ncd vgatst.pcf > PAR: Xilinx Place And Route M1.3.7. > Copyright (c) 1995-1997 Xilinx, Inc. All rights reserved. > > ERROR:baspw:110 - Cannot find Input file "map.ncd". Please verify that your > paths and permissions are properly set for this file. > > Why? This error shows even when I created simple LED decoder. > I can't work because I can't generate file. > > Tomek > > >Article: 33569
Russell, When I first looked into CPLD and FPGA design I had a simple design which would not fit due to bi-directional buffers. Cypress rep said they had no reason to change there software but I should change mine as nobody used them, YEAH RIGHT I also looked at others ATMEL, ACTEL, ALTERA etc, who gave "free" software but they had other restrictions. (time limits etc) Eventually I ended up with Xilinx webpack which is not perfect but does what it says on the tin. I also liked the spare space in the XCV300 and have no routing problems yet, where's LATTICE have a software problem which the 81080V and it's sooo small. Xilinx have RAM also. Dave P.S. I am not affiliated with Xilinx in any way (but some free samples would be nice :-) "Russell Shaw" <rjshaw@iprimus.com.au> wrote in message news:3B60D8E1.1ECB1D9D@iprimus.com.au... > Hi all, > > How's the cypress warp 6.1 ($99) compare to other cheap/free > VHDL editors/synthesizers? > > I'm interested in the delta39k devices which have internal ram. > > A particularly attractive feature of the delta39k parts (which > seem to be in a similar area to the altera acex 1k parts), is > that they have internal flash and internal (as well as external) > boot option. The acex 1k parts don't have flash, so you always > need an external configuration device, which takes up space, > inventory, and is more exposed to copying... > > http://www.cypress.com/pld/warp.html?homeadwarp > > -- > ___ ___ > / /\ / /\ > / /__\ / /\/\ > /__/ / Russell Shaw, B.Eng, M.Eng(Research) /__/\/\/ > \ \ / Victoria, Australia, Down-Under \ \/\/ > \__\/ \__\/Article: 33570
Hi,
I'm looking for some open source for a i2c bus master...does anyone
know of some?
Thanks.
Article: 33571"Rémi SEGLIE" wrote: > > Xilinx software doesn't work under Windows Me : try Windows 98 or better, Um, Me is is supposed to be the "better" replacement for Win98... > Windows NT 2000, the most appropriate OS, from microsoft, for such work... Actually, a Unix variant is the most appropriate OS for such work. I have one word: symbolic fargin' links. -andyArticle: 33572
The Summer 2001 issue of Xilinx Excell Journal contains an article describing the implementation of Hypertransport as one of the i/o pin configurations supported by the Virtex-II chips. Is anyone using Virtex-II i/o pins this way? Thanks, Dave FeustelArticle: 33573
I just read an article a few days ago about a new chip that supports multiple (cached) configuration rams that permit that company's FPGA chip to be completely reconfigured in something under 10 clocks while the FPGA is actually running. PACT offers 80 Pentium4s on a 100Mhz chip "PACT Corporation will reveal more details about takers for its 'extreme' XPP processor at the Inquest forum in San Jose this week. " http://www.theregister.co.uk/content/3/20576.html See also http://www.pactcorp.com/ "Reiner Hartenstein" <hartenst@rhrk.uni-kl.de> wrote in message news:a5a7222d.0107300945.151ab8d2@posting.google.com... > Hi, colleague, > > are there multi context FPGAs on the market > having 2 or 4 banks of configuration memory ? > > ReinerArticle: 33574
I've got Webpack download and installed. Where can I find tutorials that will show me how to use the software? Thanks, Dave Feustel
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