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Ben,
I'd like to see an Intel Pentium IV emulate an FPGA. Maybe 0.002 Hz?
The MicroBlaze 32 bit RISC softcore is running at 50 MHz. Not bad for a 'crummy'
FPGA.
http://www.xilinx.com/ipcenter/processor_central/qna.htm
If all you want to have is a single chip, then maybe the FPGA is the least
expensive solution.....
Austin
Ben Franchuk wrote:
> Jim Granville wrote:
> > Even $2.50 is significant in some silicon sectors.
> >
> > 8032, romless 8 bit uC, are available for about 60c, 40/44 pins, and
> > I think Z80's are still used, for under $2
>
> The point here is there is really no "middle class"
> in computer chips and design.{I have a "middle class" PC and I need to upgrade
> :-( }
> You have the "peanut" systems for $.25 with 1 chip
> You have the Elephant stuff for $2500 with the latest design. While there has
> been
> new designs developed we still have the crummy cpu's cause
> the are cheap.I don't expect any new features or other designs
> from FPGA chips because they don't cut the mustard for any
> designs other than simple RISC.
> Ben.
> --
> "We do not inherit our time on this planet from our parents...
> We borrow it from our children."
> "Luna family of Octal Computers" http://www.jetnet.ab.ca/users/bfranchuk
> Updated - Now with schematics.
Article: 31926stefaan vanheesbeke wrote: > > Hi, > > As far as I know, the configuration pins become user I/O's after > initialisation. You can't do anything with changing the mode pins after > configuration. > > Are you really sure that the device is configured (check the MODE pin)? > Hi Stefaan, I have found the answer in the virtex data sheet: "After configuration, the pins of the SelectMAP port can be used as additional user I/O. Alternatively, the port may be retained to permit high-speed 8-bit readback. Retention of the SelectMAP port is selectable on a design-by-design basis when the bitstream is generated. If retention is selected, PROHIBIT constraints are required to prevent the SelectMAP-port pins from being used as user I/O." Bad news, I can't use the pins for readback and as user I/Os with the same design (same bitfile). (assumed Virtex SelectMAP mode is the same as SpartanII Slave Parallel mode; Peter Alfke told me to look at the virtex data sheet). I can't test it, I have no device, I'm in the process of designing the board.Article: 31927
If you are using enumerated types, then your when others clause is doing nothing. You've already listed all of the elements of the state type when you built your case statement. So, the first thing is, your synthesis tool tosses that line. Next, your synthesis engine decides to one-hot build the state machine. OK, great. Then, you screw up the state by forcing two bits high, and it goes out to lunch. Makes sense. The synthesis tool was not instructed to put in logic to avoid or get out of lockout states. Either enumerate the Illegal states and get the synthesis tool to build a regulare state machine or Get the synthesis tool to put the lockout state protection in. I'm not familiar with Leonardo, so someone else will have to suggest specific solutions. Bob "Thomas Karlsson" <thomas.karlsson@sys.sigma.se> wrote in message news:3b20e7f9.0@d2o947.telia.com... > Hi experts! > > I have a state machine with 18 states. No matter what kind of state encoding > I choose, I will get some "dead states". In order to take care of the the > possibility that the > machine enters one of those illegal states, I write > when others => > NEXT_STATE <= IDLE; > > in the case construct for next_state, to make it return to a legal state > immediately. > > I have always thougth that this would work, but after synthesis (Leonardo > Spectrum) and P&R (M3.1i) > I get problems when I do timing simulation.(in Modelsim) > I force the state vector flops into an illegal state for a moment (two flops > set in a one-hot coded machine in this case) > to simulate a disturbance, but then the next_state signal doesn't get the > value for the state IDLE. (It gets a "five-hot" value!). > Everything gets messy and the machine does not work again until reset is > applied > > What is wrong? I guess that the necessary logic for doing this jump to a > legal state has been optimised away. > How can I avoid that? > > In Leonardo I get the warning "others clause is never selected", but since I > never assign "others" to the state vector, > that is only natural, or??? > > Any hints greatly appreciated. > > /Thomas > > >Article: 31928
Didnt try myself and running Win2000 Can you install as administrator (with rights) and then not run when User (without rights)? Looking at the registry using regedit it seems like the only obvious file in the WINNT was the uninstall function. (Only using PE myself) C:\WINNT\IsUninst.exe -fC:\Program\Modeltech\v_5.5\win32\Uninst.isu -- Best regards, ulf at atmel dot com The contents of this message is intended to be my private opinion and may or may not be shared by my employer Atmel Sweden "Jonas Thor" <thor@sm.luth.se> skrev i meddelandet news:gk61it0uv7ot3rc7l0mbf419l9mi9gqk9c@4ax.com... > Hi all! > > I'm going to setup a Windows NT lab with either Xilinx webpack or > Xilinx Foundation 3.1. We have up until now only been using Xilinx > Alliance for Solaris. > > Anyway, my question is if anyone sucessfully has managed to setup such > a lab. We tried to install Webpack with MXE (Modelsim XE) but, for > some reason, Modelsim needs write access to the windows system > directory. We do not want several hundreds of students having write > access to the system directory... > > Has anyone got a solution to this problem? > > / Jonas ThorArticle: 31929
Hi experts!
I have a state machine with 18 states. No matter what kind of state encoding
I choose, I will get some "dead states". In order to take care of the the
possibility that the
machine enters one of those illegal states, I write
when others =>
NEXT_STATE <= IDLE;
in the case construct for next_state, to make it return to a legal state
immediately.
I have always thougth that this would work, but after synthesis (Leonardo
Spectrum) and P&R (M3.1i)
I get problems when I do timing simulation.(in Modelsim)
I force the state vector flops into an illegal state for a moment (two flops
set in a one-hot coded machine in this case)
to simulate a disturbance, but then the next_state signal doesn't get the
value for the state IDLE. (It gets a "five-hot" value!).
Everything gets messy and the machine does not work again until reset is
applied
What is wrong? I guess that the necessary logic for doing this jump to a
legal state has been optimised away.
How can I avoid that?
In Leonardo I get the warning "others clause is never selected", but since I
never assign "others" to the state vector,
that is only natural, or???
Any hints greatly appreciated.
/Thomas
Article: 31930"Thomas Karlsson" <thomas.karlsson@sys.sigma.se> wrote in message news:<3b20e7f9.0@d2o947.telia.com>... > Hi experts! > > I have a state machine with 18 states. No matter what kind of state encoding > I choose, I will get some "dead states". In order to take care of the the > possibility that the > machine enters one of those illegal states, I write > when others => > NEXT_STATE <= IDLE; > > in the case construct for next_state, to make it return to a legal state > immediately. > > I have always thougth that this would work, but after synthesis (Leonardo > Spectrum) and P&R (M3.1i) > I get problems when I do timing simulation.(in Modelsim) > I force the state vector flops into an illegal state for a moment (two flops > set in a one-hot coded machine in this case) > to simulate a disturbance, but then the next_state signal doesn't get the > value for the state IDLE. (It gets a "five-hot" value!). > Everything gets messy and the machine does not work again until reset is > applied > > What is wrong? I guess that the necessary logic for doing this jump to a > legal state has been optimised away. > How can I avoid that? > > In Leonardo I get the warning "others clause is never selected", but since I > never assign "others" to the state vector, > that is only natural, or??? > > Any hints greatly appreciated. > > /Thomas Illegal states are not that problematic. Leonardo (or any good synthesis tool) will synthesize out the logic to recover from them. The reason being is that state machines usually have a reset. As long as the machine is running at the correct speed stated during timing analysis, it will never enter those other states unless something catastrophic happens, which will require a system reset. The only way a one-hot state machine is faster (and possibly smaller) than binary machines is that the illegal states are ignored. Think of the fan in to each bit if you look at all states. 18 inputs from the bits are added. One hot state machines have been used for years and nothing catastrophic has happened. I hope this helps.Article: 31931
Hi, Maybe I'm restating the obvious, but check your synthesis tool for some hidden option dialog that allows you to control how the tool handles FSMs. Foundation/FPGA express has a handy option for selecting fastest or safest FSM encoding. I always select safest and haven't had any problems. Hope this helps, Jeff *********************************************** Jeffrey Vallier Sr. FW Engineer Gibson Guitar Corp. GMICS Division 1283 F Old Mtn View/Alviso Rd. Sunnyvale, CA 94089 408 734 4394 *********************************************** "Thomas Karlsson" <thomas.karlsson@sys.sigma.se> wrote in message news:3b20e7f9.0@d2o947.telia.com... > Hi experts! > > I have a state machine with 18 states. No matter what kind of state encoding > I choose, I will get some "dead states". In order to take care of the the > possibility that the > machine enters one of those illegal states, I write > when others => > NEXT_STATE <= IDLE; > > in the case construct for next_state, to make it return to a legal state > immediately. > > I have always thougth that this would work, but after synthesis (Leonardo > Spectrum) and P&R (M3.1i) > I get problems when I do timing simulation.(in Modelsim) > I force the state vector flops into an illegal state for a moment (two flops > set in a one-hot coded machine in this case) > to simulate a disturbance, but then the next_state signal doesn't get the > value for the state IDLE. (It gets a "five-hot" value!). > Everything gets messy and the machine does not work again until reset is > applied > > What is wrong? I guess that the necessary logic for doing this jump to a > legal state has been optimised away. > How can I avoid that? > > In Leonardo I get the warning "others clause is never selected", but since I > never assign "others" to the state vector, > that is only natural, or??? > > Any hints greatly appreciated. > > /Thomas > > > >Article: 31932
Hi Austin,
MicroBlaze is actually running at 125 MHz in VII.
Göran Bilski
Austin Lesea wrote:
> Ben,
>
> I'd like to see an Intel Pentium IV emulate an FPGA. Maybe 0.002 Hz?
>
> The MicroBlaze 32 bit RISC softcore is running at 50 MHz. Not bad for a 'crummy'
> FPGA.
>
> http://www.xilinx.com/ipcenter/processor_central/qna.htm
>
> If all you want to have is a single chip, then maybe the FPGA is the least
> expensive solution.....
>
> Austin
>
> Ben Franchuk wrote:
>
> > Jim Granville wrote:
> > > Even $2.50 is significant in some silicon sectors.
> > >
> > > 8032, romless 8 bit uC, are available for about 60c, 40/44 pins, and
> > > I think Z80's are still used, for under $2
> >
> > The point here is there is really no "middle class"
> > in computer chips and design.{I have a "middle class" PC and I need to upgrade
> > :-( }
> > You have the "peanut" systems for $.25 with 1 chip
> > You have the Elephant stuff for $2500 with the latest design. While there has
> > been
> > new designs developed we still have the crummy cpu's cause
> > the are cheap.I don't expect any new features or other designs
> > from FPGA chips because they don't cut the mustard for any
> > designs other than simple RISC.
> > Ben.
> > --
> > "We do not inherit our time on this planet from our parents...
> > We borrow it from our children."
> > "Luna family of Octal Computers" http://www.jetnet.ab.ca/users/bfranchuk
> > Updated - Now with schematics.
Article: 31933Hi, Check your bitgen.ut file and see if the default clock is JTAGCLK or CCLK. If you're JTAG-ing it into you chip, this has to be set to JTAGCLK or the device will be looking for a PROM or uC clocked by the CCLK pin to boot from. Hope this helps, Jeff -- *********************************************** Jeffrey Vallier Sr. FW Engineer Gibson Guitar Corp. GMICS Division 1283 F Old Mtn View/Alviso Rd. Sunnyvale, CA 94089 408 734 4394 *********************************************** "Asfandyar Khan" <asfandyar@telematix-corp.com> wrote in message news:ee70d5f.1@WebX.sUN8CHnE... > Hi, > > I have generated a bit file for Virtex-E using BitGen. > > While trying to download the design on the chip which resides on a development kit, the folowng error pops up in the Hardware Debugger: > > "Device is not configured. Done is not high." > > Regards, > Asfandyar. >Article: 31934
That's a common use for JTAG. You can read the details of how to do that at Intel's or Corelis's Web sites: http://developer.intel.com/design/flcomp/applnots/292186.htm http://www.corelis.com (ask for their application notes). The Intel site uses one of their CPUs to actually drive the Flash pins, but the same trick of pin control works with most modern FPGAs as described by Corelis (who even sells the software to do it almost automatically - but for as much as US$9600). Best to you and your project - Jim Horn WB9SYN/6Article: 31935
Hi, Thanxfor your reply. I thn the optos are fine. Please check if you could find an error. I am not JTAg-ing. I am trying to download the bitstream on to the chip. -g DebugBitstream:No -w -g Gclkdel0:11111 -g Gclkdel1:11111 -g Gclkdel2:11111 -g Gclkdel3:11111 -g ConfigRate:4 -g CclkPin:PullUp -g M0Pin:PullUp -g M1Pin:PullUp -g M2Pin:PullUp -g ProgPin:PullUp -g DonePin:PullNone -g TckPin:PullUp -g TdiPin:PullUp -g TdoPin:PullNone -g TmsPin:PullUp -g UserID:0xFFFFFFFF -g StartUpClk:CClk -g DONE_cycle:4 -g GTS_cycle:5 -g GSR_cycle:6 -g GWE_cycle:6 -g LCK_cycle:NoWait -g Security:None -g Persist:Yes -g DonePipe:Yes -g DriveDone:YesArticle: 31936
-g DebugBitstream:No -w -g Gclkdel0:11111 -g Gclkdel1:11111 -g Gclkdel2:11111 -g Gclkdel3:11111 -g ConfigRate:4 -g CclkPin:PullUp -g M0Pin:PullUp -g M1Pin:PullUp -g M2Pin:PullUp -g ProgPin:PullUp -g DonePin:PullNone -g TckPin:PullUp -g TdiPin:PullUp -g TdoPin:PullNone -g TmsPin:PullUp -g UserID:0xFFFFFFFF -g StartUpClk:CClk -g DONE_cycle:4 -g GTS_cycle:5 -g GSR_cycle:6 -g GWE_cycle:6 -g LCK_cycle:NoWait -g Security:None -g Persist:Yes -g DonePipe:Yes -g DriveDone:YesArticle: 31937
In article <3B20982D.5EC2C857@free.fr>, sjulhes@free.fr (Stephane) wrote: > Hi, > > I'm studying the following architecture : > > I have an APEX200E with 1 embbeded NIOS microcontroller which runs his > program from an external flash. > The APEX's configuration file beeing contained in his 2 EPC2 > configuration flash PROM. > > My main problem is NIOS and FPGA software update. > > I intend to use JTAG. > > The FPGA's EPC2 would be programmed by their JTAG pins. > The flash memory has no JTAG pins. > So I was wondering if I could program it by driving the FPGA's pins ( > the address, data and control bus pins ) using the FPGA's JTAG > capabilities. Yes. > Does anyone has already done such a thing ? Yes. > Does it works ? Yes. Only downside is that it's slow; if you use a ByteBlaster-style parallel port adaptor, it's /very/ slow. > What is the consequence on the JTAG software on the host PC ? Sorry, don't understand the question. If you mean, "Where can I get software to do it?" there are two answers. 1) You can pay huge amounts of money (of the order of US$10k) to one of the high-end JTAG vendors (TTBOMK, there /are/ no low-end JTAG vendors). 2) You can pay nothing at all for my program (go to http://www.rsn-tech.co.uk/pjtag) and do it yourself. I even include a sample program that does exactly that for a Flex10K design. 3) Ok, three answers - you can pay rather less than $10k for my program and get some help from me as well :-) -- Steve Rencontre http://www.rsn-tech.co.uk //#include <disclaimer.h>Article: 31938
You might want to look at www.vmware.com . Their product allows
you to create a virtual machine (VM), with virtual disks.
1) On a NT4 system, create a virtual NT4 system, with its virtual disks
as files, not partitions.
2) Install Xilinx and other software on the virtual system
3) Make a copy of the complete virtual system to a safe and secure system,
maybe also a CD copy, for later easy restore.
4) Put a copy of the virtual system on each stuudent system.
5) Let the kids go wild inside their virtual system. They cant do any damage
to the host system (if you set things up the right way).
6) When a student crashes or corrupts his VM, or if you are starting a
new semester/class, just wipe all the VMs, and install a fresh copy
of the master.
Philip Freidin
On Fri, 08 Jun 2001 11:38:39 +0200, Jonas Thor <NOthor@SPAMsm.luth.se> wrote:
>Hi all!
>
>I'm going to setup a Windows NT lab with either Xilinx webpack or
>Xilinx Foundation 3.1. We have up until now only been using Xilinx
>Alliance for Solaris.
>
>Anyway, my question is if anyone sucessfully has managed to setup such
>a lab. We tried to install Webpack with MXE (Modelsim XE) but, for
>some reason, Modelsim needs write access to the windows system
>directory. We do not want several hundreds of students having write
>access to the system directory...
>
>Has anyone got a solution to this problem?
>
>/ Jonas Thor
Philip Freidin
Fliptronics
Article: 31939Nice ... now if only they came in hobbyist-friendly packages (PLCC, QFP, etc.), they'd be perfect! Luke On Thu, 7 Jun 2001, Austin Lesea wrote: > Ben, > > I can't resist. > > the Virtex II 2V40 is less than ~$25 in quantities, and due to drop even less in the > future (fg256). > > Not bad for four DCM's (DLL+DPS+DFS), four 18Kb block rams, four 18x18 multipliers, > 512 LUTS, 512 FF's, and the commeasurate IO's. > > It is less expensive to place all of the clock management, mirroring, and deskew for a > system (the heck with the logic!) on a 2V40 than to buy just one 'robo clock.' > > Sorry about needing 256 fingers and toes though. It is also avaliable in a cs144 > (only 8 people's fingers and toes?) > > Austin > > Ben Franchuk wrote: > > > Peter Alfke wrote: > > > The device came in a 16-pin package. 4 Din, 4 Dout, clock and Busy on the input, > > > clock and Ready on the output. Could be cascaded ad infinitum. > > > > Ah! the good old days when you could count pins on ones fingers and toes. > > Also what ever happened to LOW COST chips like $25 not $250 or $2,500. > > Ben. > >Article: 31940
Stephane <sjulhes@free.fr> wrote in message news:<3B20982D.5EC2C857@free.fr>... > Hi, > > I'm studying the following architecture : > > I have an APEX200E with 1 embbeded NIOS microcontroller which runs his > program from an external flash. > The APEX's configuration file beeing contained in his 2 EPC2 > configuration flash PROM. > > My main problem is NIOS and FPGA software update. > > I intend to use JTAG. > > The FPGA's EPC2 would be programmed by their JTAG pins. > The flash memory has no JTAG pins. > So I was wondering if I could program it by driving the FPGA's pins ( > the address, data and control bus pins ) using the FPGA's JTAG > capabilities. > > Does anyone has already done such a thing ? > > Does it works ? > What is the consequence on the JTAG software on the host PC ? > > Thanks in advance. > > Stephane. > Thales Microelectronics. Hi Stephane, I'm sorry that I can't help you right now but later... We at BlueIguana (http://www.blueiguana.com) working hard to solve this problem to update an whole system consisting of FPGA, microcontrollers, FLASH, EEPROM, etc. in a secure way... The JTAG port on the FPGA can be used to configure the FPGA and access internal registers (readback). The TAP controller in the FPGA can be switched to a transparent mode, therefore other devices in the JTAG chain can be configured.... To program the FLASH you have to implement a TAP controller together with a statemachine to program the FLASH, therefore developing a JTAG interface for the FLASH. You can implement such an interface in a part of the FPGA you are already using or using a different part... This 'user JTAG port' you daisychain with the JTAG port of the FPGA.... Then you can configure/program both.... I don't know if there any other solutions available that you can use... I hope this clearified it a little... cul8r, AS (Andreas)Article: 31941
Just curious, The Coregen that is a part of Foundation Tools (non-ISE) generates cores based on a revision of unisim and/or simprim libraries that is different from those precompiled into Modelsim XE. Which means that during Modelsim XE compilation one would orinarily get an error indicating that an entity referenced in the configuration block was not found. What was your strategy in getting over the above obstacle? YuryArticle: 31942
Pak K Chan Univ of CA, Santa Cruz 225 Applied Sciences Santa Cruz, CA 95064 (408) 459-4156 pak@cse.ucsc.edu Donald Hung San Jose State University One Washington Square San Jose, CA 95192-0180 (408) 924-4087 dhung2@email.sjsu.edu -- ***************************** Anna M. Acevedo Xilinx University Program 2100 Logic Drive San Jose, CA 95124 PH: (408) 879-5338 FAX: (408) 879-4780 Email: anna.acevedo@xilinx.com http://www.xilinx.com/programs/univ.htm *****************************Article: 31943
Hello, I am planning an application where I need a remote FPGA based architecture which I want to reconfigure using a microcontroller. The Triscend E5 CSoc (8051 + FPGA) specifications seem very interesting since all resides in a single chip but, is it possible to reconfigure the FPGA part of the chip using a program in the internal microcontroller? Based on the specifications, reconfiguration goes through the JTAG input, which I could control using the PIOs of the E5, but for security reasons, I would prefer to find out an internal way to do this, is it possible? Thanks for any comments with a copy to my email. Miguel FPGAs for Computer Vision INAOE - MexicoArticle: 31944
The problem yo are having is a mismatch between what the place and route needs and what the simulation needs. For simulation, you need to specify the INIT generic, as you have done. Simulation uses that to apply the LUT function to the LUT component. The synthesizer won't do anything with the generic, and in fact will usually either complain or generate a different black box for the primitive (depends on the synthesis tool...SYnplicity will create a unique black box and issues a warning that it doesn't know what to do with generics on black boxes). The synthesis just puts down a LUT if you instantiate one. It doesn't create an init attribute unless it inferred the LUT. You need to add an INIT= attribute to the LUT instantiation to get the contents into the implemented design. If you do not, then the LUT gets loaded with a default init value of X"0000". Unfortunately, as you have found, this means another opportunity to have your implemented code behave differently than the simulation. You can gt around that by either not using LUTs (if using synplicity, you can put RTL code for the logic that goes in a LUT in a separate component and use the synplicity xc_lut or xc_fmap attributes to get the same effect as an FMAP), or by writing your code so that it derives the init generic and init attribute values from the same source. The formats for the two are also different: the generic is a bit vector and the attribute is a hex string. THe snippet below is for a design that preloads an SRL16, but the idea is the same itoh is a home-spun function to convert an integer to a hex string and int2bit_vec is one that converts an integer to a bit vector. The translate on and off pragmas are necessary to hide the generics on the primitive, which is a black box from the synthesizer. Note both values are functions of the same integer in this code, so I only need to test that the translations work correctly once, then I should always get simulations that match the hardware. --INIT= attribute to pass to PAR through synplicity attribute INIT of U1 : label is itoh(lut_init); begin U1: SRL16E --synthesis translate_off -- init generic is for simulation model, not seen by Synplicity or PAR generic map ( INIT => int2bit_vec(lut_init,16)) --synthesis translate_on port map ( Q => y, Michael Dales wrote: > Hi there, > > I'm trying to implement an algorithm using the LUT4 on Virtex. I have > numerous variations on the following: > > lut_0: LUT4 generic map (INIT => X"0E6E") > port map (res(0), val(0), val(1), val(2), val(3)); > > This simulated fine using the Alliance libraries compiled for Cadence > Leapfrog, but when I tried to run it through FPGA Express it barfs on > my generic map, with the following error: > > "Bad formal part - port names in entity and component declarations do > not match." > > I checked the unisim vcomponents file and the component declaration > seems to be correct. > > Any suggestions?Article: 31945
Russell Shaw wrote: > > Using the Quartus fitter in maxplus2 (for acex1k), it crashes at > 28% when doing a simple 32x8 lpm fifo function and not much else > (pc has 256MB ram). By setting the option not to use quartus, the > compilation completes without error. Have you found the same bugginess? Using a 10k10 fpga I find fitting can be a real pain. I have over 85% of the chip full and am router bound on my design. It is right on the threshold of Not Routing!. The best I can do is lock only the pins needed for testing a small prototype and have the other pins float. Ben.Article: 31946
Hi all, I fitted an AHDL design into a max7000s device, but some pins had to be moved to make a fit. Is there a way to group pins in maxplus2 so that the fitter can move the whole group without splitting it? (useful for buses) Also posted in: alteraFPGA@egroups.com (yahoo groups) -- ___ ___ / /\ / /\ / /__\ / /\/\ /__/ / Russell Shaw, B.Eng, M.Eng(Research) /__/\/\/ \ \ / Victoria, Australia, Down-Under \ \/\/ \__\/ \__\/Article: 31947
Rick Filipkiewicz wrote: > The other missing issue, heavily related to the above, is portability. I think schematics are not portable ( ignoring the fact that there is no schematic drafting standard) because they often are closer to the underlining hardware than HL's are. People drawing schematics tend to draw schematic more optimized to the underlining hardware than generic stuff. This points out that all FPGA's (from different companies) are not created equal and logic elements in FPGA's are non portable. If one tries to use features common to all FPGA's you are 50% slower and 50% less dense in most designs. Ben.Article: 31948
Have anybody used FPGA device to control STN LCD panels either 16 bit or 24 bit? What is the possibility to do it ? we have a lots of stock of 6" STN panels so we want to make standalone monitor for Video or VGA interface or both. All the controllers for STN LCD's are either ISA or PCI based which is not suitable for our application. Any comments will be appreciated. Regards, -- *********************** Chaudhry ICQ# 11502664 Singapore ***********************Article: 31949
Hi, I've been using a cypress async. fifo chip, and tried to do the same thing in maxplus2. However, the lpm functions only have fifos that require clocks. The fifo chip i was using didn't need *any* clocks. Will i need to do my own? -- ___ ___ / /\ / /\ / /__\ / /\/\ /__/ / Russell Shaw, B.Eng, M.Eng(Research) /__/\/\/ \ \ / Victoria, Australia, Down-Under \ \/\/ \__\/ \__\/
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