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I would want to know if the core produced by the core generator of Xilinx 3.1 Foundation ISE are free or I must to pay to have it, for example I'm talking about the IQ NCO available. Another question is how I can insert the cores in my project. Thank you for your help... Antonio D'OttavioArticle: 32726
Use the Configuration-Troubleshooter on the Xilinx webpage. ManfredArticle: 32727
Hello, We`re looking for a simple 5V PCI (or universal 5V/3.3V) board with a Virtex or SpartanII on it for some PCI prototyping. No RAM needed, no software drivers needed (Linux), just a simple PCI form factor card with an Xilinx FPGA on it (we licensed the Xilinx PCI core). Any pointers? Thanx in advance! StevenArticle: 32728
Insight Spartan II PCI development kit. H. "Steven Sanders" <steven.sanders@imec.be> wrote in message news:3B4570AA.9CE9AE1F@imec.be... > Hello, > > We`re looking for a simple 5V PCI (or universal 5V/3.3V) board with > a Virtex or SpartanII on it for some PCI prototyping. No RAM needed, > no software drivers needed (Linux), just a simple PCI form factor card > with an Xilinx FPGA on it (we licensed the Xilinx PCI core). > > Any pointers? > > Thanx in advance! > > StevenArticle: 32729
Nial Stewart wrote: > Further to my comment above, it looks like Nutscrape doesn't > pick up attachments, or something's blocking the binaries > on the server I'm on. I had no problems at all. (NN4.73, UNIX)Article: 32730
Torbjörn Stabo wrote: > > Nial Stewart wrote: > > > Further to my comment above, it looks like Nutscrape doesn't > > pick up attachments, or something's blocking the binaries > > on the server I'm on. > > I had no problems at all. (NN4.73, UNIX) I think it's probably more to do with the Usenet server than Netscape. Some servers auto block binaries on non binary newsgroups. Nial.Article: 32731
Thu, 5 Jul 2001 08:01:20 +0200 "Marco" <curgan@t-online.de> ×ÙÄÁÌ: >i am developing with an ACEX EP1K30. >My question: Do anybody know the best configuration device for that device? >i only know the EPC1 and EPC2. Are there some form other manufacturers ? I use configuration devices AT17C512A (www.atmel.com) with FPGA Flex10K20. These devices on 5 volts. For 3-V devices (ACEX) it will take to use the AT17LV***A. Use the own homemade sofware for frequentative programming in system. http://www.orc.ru/~dkuzn/at17isp_e.htm I also known someone else experience of using of such devices with Xilinx. Because of this I specially ask to comprise of software a function of disable the built-in generator DCLK. Best regards! Dmitry Kuznetsov, Moscow, http://www.orc.ru/~dkuzn/index.htm [Team RaceTerrapin] [Team LEXX] ===Article: 32733
Hello FPGA Gurus, I've been trolling the Google archives for this news group looking for a Logic Analyzer that I may built as a kit (or buy cheaply) I came across reference in Oct 1996 for a company - 'ProBoard Circuits' which sell a cheap logic analyzer. Does anyone have any experience with this Company and have any further contact info? Can anyone point me in the right direction in being able to find a low cost login analyzer for, relatively' low speed work. I am looking for something pretty basic - around 8 channels (min) - perhaps 20 MHz max freq. Any ideas? TIA IvanArticle: 32734
X2S_EVAL from CESYS has SPARTAN-II and PCI www.cesys.com Manfred Kraus Harjo Otten <h.otten@rohill.geen.spam.nl> schrieb in im Newsbeitrag: ub34i9.uma.ln@svr004.rohill.nl... >Article: 32735
Hello Subodh, /PROGRAM ist low-active. While /PROGRAM is low, the FPGA clears it's configuration. You should change something: Subodh Nijsure wrote: > > Hello, > > Is the following sequence to download bit file to Xilinx Vertex_E correct? > I am using CPLD which to send bit stream to FPGA. > > Here are the steps I am doing from my Linux driver that downloads the > bitstream to the FPGA. > > 1. Hold PROGRAM high wait for 400 us hold /PROGRAM low. [check, if DONE goes to low] > 2. Hold PROGRAM low, monitor the INIT pin, wait for it to go high, this > will indicate FPGA has cleared the memory. hold /PROGRAM high ... > > 3. Then hold PROGRAM pin high, CCLK 0, send data bit 0, > 4. Then hold PROGRAM pin high, CCLK 1, send data bit 0, > Repeat steps 3 through 4 for entire .bit file. > > Now monitor the DONE pin if its high everything is okay else FPGA download > failed. If DONE has not gone to high, you should check INIT. If it is low, there was an error. If it is high, the FPGA still waits for more data. 5. send some additional CCLK pulses for startup of the FPGA (while DIN high) (leave /PROGRAM high) > > WHat I have observed is after step 2 above if i wait for 100 us and go > back and check the INIT pin it has gone low, I haven't sent any data bits while /PROGRAM is low, the FPGA repeats clearing the configuration memory. INIT = low signals this situation. > to FPGA yet. So if INIT pin has gone low (0) should I still continue to > send data? > Also in steps 3 and 4 should one be checking if INIT has gone low or DONE > has gone high? not necessary. My experiences are with XC4000. But I think, there should be no difference in slave serial mode. Hope this helps, WernerArticle: 32736
Ben Franchuk schrieb: > > I am using altera's 10k10 FPGA's block ram in asynchronous mode. Iam not very familiar with the Altera stuff. What does asynchronous mode mean? In the Xilinx parts, all write operation to RAM are synchronous, so the solution is simple. How about the Altera parts? -- MFG FalkArticle: 32737
Thank You! I was looking for the manufacturer and board spec. > Ray Andraka wrote: > > have you tried http://www.annapmicro.com? > > What information are you looking for specifically? > > Sandra Nielsen wrote: > > > Hi, > > > > Sorry in advance for a dumb question from a newbie. I'm looking for > > information on the AMS Wildstar board. Can anyone point me in the > > right direction? > > > > Thank you, > > SandraArticle: 32738
hi. i am doing post-route simulation on a design using the virtex block ram. when i probe at the address and clock inputs, and the data output, i see that there is a 14 ns delay from the clock rising edge to the data appearing on the output data bus. i suspect that there is something wrong with the way i configured the block ram, or some setting i did not perform because the switching characteristic is that the clock -> dout is 4.3 ns for the speed grade i have. the clock is on a clock buffer (bufg) so that the slew rate is not a problem (my original suspicion). i don't think it is routing delay because i am probing directly at the inputs and outputs of the block ram instantiation (RAMB4_S16). does anyone have any suggestions or comments on what could be the problem? thank you in advance. chris wangArticle: 32739
The NCO is free. You basically select some confuguration options(bus width, LUT depth, etc.) and hit generate. The generator then creates a *.edn file containing the description of the module for synthesis. Depending on whether you are using schematic entry or hdl it will also create a file describing how to instantiate the block into your design. It only takes a few minutes. "Antonio" <dottavio@ised.it> wrote in message news:fb35ea96.0107052241.38e54d7a@posting.google.com... > I would want to know if the core produced by the core generator of > Xilinx 3.1 Foundation ISE are free or I must to pay to have it, for > example I'm talking about the IQ NCO available. Another question is > how I can insert the cores in my project. > Thank you for your help... > > Antonio D'OttavioArticle: 32740
Ivan Vernot wrote:
>
> Hello FPGA Gurus,
> I've been trolling the Google archives for this news group looking for a
> Logic Analyzer that I may built as a kit (or buy cheaply)
go to www.ebay.com and search for "Logic Analyzer"
Pages of them.
But I must acknowledge that I hate logic analyzers.
Too may little wires and clips and imponderable results.
As I have learned more about simulation, I have also
given away all my logic analyzers to folks here at
Fluke who still like them.
--Mike Treseler
Article: 32741Posted white paper (minerrors.pdf) MINIMIZING DESIGN ERRORS. This paper discusses processes, methodologies, and classes of tools necessary to minimize ASIC and FPGA design errors. http://www.vhdlcohen.com/ -------------------------------------------------------------------------- ------------------------------------------ Ben Cohen Publisher, Trainer, Consultant (310) 721-4830 http://www.vhdlcohen.com/ vhdlcohen@aol.com Author of following textbooks: * Component Design by Example ... a Step-by-Step Process Using VHDL with UART as Vehicle", 2001 isbn 0-9705394-0-1 * VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1 * VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115 -------------------------------------------------------------------------- ------------------------------------------Article: 32742
Hi I've had some bad experiences with dc_shell and Xilinx Virtex/E libraries so I'm trying to use FPGA Expree 3.4 which came with Foundation. Even though it's Windows based and kind of slow, it's giving way better results than dc_shell. I'm stuck using fe_shell instead of the GUI. It seems to recognize format by the filename extension, and my designs have the more common .vs, .vg, .vr extensions. Unlike the GUI, I can specify the format and filename within fe_shell. Only big probelm so far is migrating my scripts. Normally I do a: set search_path "$search_path ../../defines" in dc_shell so it can find everything that I `include in code. I set this variable in fe_shell and it seemed to have no effect; when I add files it was not actually regarding the search path. Is this done differently in fe_shell than dc_shell? -- O..O Arcade machine collection: (----) http://www.science.wayne.edu/~joey/arcade/ ( >__< ) IRC - EFNet #rgvac: demigod2k ^^ ~~ ^^Article: 32743
Hi, Do you believe that an implementation of a FP SQRT using a LogiCORE SQRT function with a post-normalization unit is a real-state efficient implementation? BTW, I will need to change the integer/fix-point format to the mantisa/exponent pair format. Do you have a better idea to determine the exponent rather than look for the first 'one' on the left side of the word using a counter? Thank you, JaviArticle: 32744
Altera has a white paper reference design that describes how to use a US $1 MAX3032 and a standard off-the-shelf flash part to configure an ACEX (or FLEX or APEX) device. Once the device is configured, the MAX3032 gets off the bus so that you can use the rest of the flash device for code storage (if you need that). This can really be a help if your design is cost sensitive. I can't recall the document number, but if you search the Altera site for "configuring with flash", you should be able to find the white paper. -Pete- Marco <curgan@t-online.de> wrote in message news:9i0vbe$v3m$00$1@news.t-online.com... > Hello everybody, > > i am developing with an ACEX EP1K30. > My question: Do anybody know the best configuration device for that device? > i only know the EPC1 and EPC2. Are there some form other manufacturers ? > > Have anyone some schematics with the ACEX ???? > > Thank you very much. > > Best regards > > Marco > > >Article: 32745
Subodh Nijsure wrote: > [ Not certain if this is the most appropriate group to post this message, > could only find this fpga related newsgroup ] > > I have Xlilinx XCV50E for which I have bitstream file (.XBN), that I want to > download. I am using a ALTERA CPLD to send this bitstream to the FPGA. > Platform is running Linux (2.4.2) on Motorola 860 processor. I am writing > a driver to send this file to the FPGA > > The basic quesiton I have is, when I am clocking this bitstream to the > FPGA, as I read the byte from a file, should I be shifting the bits > MSB first or LSB first? LSB first.Article: 32746
hello, could the Foundation tool still able to perform "retiming" even with schematic (not VHDL) entry ? If yes what's the command to use or the option to tick ? thanksArticle: 32747
You could do worse. Binary square root is easily factored by 4, making floating point versions nearly trivial to do from a fixed point core. For fixed to float conversion, all you need is a normalizing barrel shift implemented as an optimal merged tree. It is constructed of layers of 2:1 muxes with each layer either passing the data unshifted or shifting it by a power of two. Arrange the shifts so that the largest shift is done first. To determine whether to shift or not, you look at the top bits to see if shifting will overflow or not (a simple or is all you need if the input is unsigned). Each stage's shift logic should use the previous stage's output for the inputs to its decision. The shift decisions become the exponent, and after all the shifts, the mantissa is normalized. jdiaz_pr wrote: > Hi, > > Do you believe that an implementation of a FP SQRT using a LogiCORE > SQRT function with a post-normalization unit is a real-state efficient > implementation? > > BTW, I will need to change the integer/fix-point format to the > mantisa/exponent pair format. Do you have a better idea to determine > the exponent rather than look for the first 'one' on the left side of > the word using a counter? > > Thank you, > Javi -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.comArticle: 32748
I am having trouble setting up Xilinx Foundation 3.3 on a number of new P4s with windows 2000. I need to have the students operate with restricted permissions so that the machines stay stable. It runs perfectly when I am in the administrator role. I think that I have changed all of the necessary file permissions but I am having a harder time figuring out the regitry permissions. I am presently getting the following errors: REVENGINE-failed to update system registry and m1map.exe has generated errors and will be closed. I am sure that someone has solved this problem already and I would really appreciate any help. Thank you, Mike Lowey
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