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I do not have in my Project Navigator Processess window - Design Entry Utilities Launch HDL Bencher Tool button What I should do to add it there? MaciekArticle: 35426
I do not have in my Project Navigator Proccessess for Current Source Window - Design Entry Utilities section Launch HDL Bencher Tool button. How I can add it there? MaciekArticle: 35427
Rick Filipkiewicz <rick@algor.co.uk> wrote: > The use of VCD is what's put me off XPower so far. It strikes me that any decent > power estimate is going to need a lot longer run than 100usec although that will be > very much design dependent. If so then there are really only 3 options: Very true. In my case, my real simulation took 150us; there's about 50us of simulation, then 100us while it does stuff. After configuration, the chip could run for up to a week doing the same thing, so there wasn't any advantage in running for longer. However, I didn't start the VCD dump until the setup part had completed (after the first 50us), because very little is happening in that time and it was distort the results. The simulation I did was of the mapped design. The XPower instructions tell you to VCD dump everything, which I assumed meant all internal signals, which you can only get by using a mapped or routed design. I agree about VCD.. nearly 500Mb for 100us of simulation isn't good. The ModelSim WLF file for the same time is probably well under 50Mb. Hamish -- Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>Article: 35428
I have Xilinx Foundation 3.3i now, I tried WebPack ISE 4.1 XST seems to be much better than Synopsys FPGA compiler. Question: How can I use the Core Generator, that came with Foundation with WebPack ISE ? Thx alot -- Manfred news102001@cesys.comArticle: 35429
more accurately, it is a sawtooth (modular ramp) sampled at the master
clock frequency and quantized by truncation to one bit.
Allan Herriman wrote:
> On Wed, 03 Oct 2001 06:16:53 -0000, hmurray-nospam@megapathdsl.net
> (Hal Murray) wrote:
>
> >
> >>That is in the nature of DDS.
> >>Max jitter = one clock period.
> >>If that is acceptable, go for it.
> >
> >Somehow, it seems as though I should be able to get close to
> >a half clock period. Closer "just" takes more bits of state.
> >
> >What am I missing?
>
> Another way of looking at this is to think about the output of the NCO
> as being a square wave at some frequency that has been sampled by the
> NCO clock.
>
> If the frequency of the square wave is the NCO clock divided by an
> integer, then the sampling process will produce 0 jitter.
> For most frequencies though, the sampling process produces jitter of
> up to a clock period.
> Please take the time to look at the jitter measurements that I posted
> earlier in this thread.
>
> ***
> There's a simple modification that halves this jitter. It does
> require a 50% duty cycle clock and one falling edge flip flop though.
> Email for code.
>
> Regards,
> Allan.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 35430
You need the virtexII libraries, which were distributed with SP6 and
required a special install. If you did not install or get that, then
SP7 and SP8 do not update your 3.3 tools with the virtexII stuff.
Alternatively, you cna wait till you get your 4.1 software.
viswanath wrote:
> How to use built-in multipliers in virtex-II?
> Do I need to use any libraries from xilinx?
>
> Rgds,
> visu
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 35431Hi all (especially the folks at Xilinx ;o) Does anyone know when the first Spartan2E samples will be available? We plan to replace a VirtexE and would like to plan the design... Thanks in advance -- Nicolas MATRINGE IPricot European Headquarters Conception electronique 10-12 Avenue de Verdun Tel +33 1 46 52 53 11 F-92250 LA GARENNE-COLOMBES - FRANCE Fax +33 1 46 52 53 01 http://www.IPricot.com/Article: 35432
When I look at the rather complicated procedure concerning MaxPlus2 of Altera, which only runs 3 month, I doubt it. The commercial version requires a dongle. Rene -- Ing.Buero R.Tschaggelar - http://www.ibrtses.com Zoltan Kocsi wrote: > > I was away for a while from the NG, is there any word on FPGA > vendors offering (or planning to) Linux toolchains (in the same > config and pricing as their Win tools) ? > > Thanks, > > Zoltan > > -- > +------------------------------------------------------------------+ > | ** To reach me write to zoltan in the domain of bendor com au ** | > +--------------------------------+---------------------------------+ > | Zoltan Kocsi | I don't believe in miracles | > | Bendor Research Pty. Ltd. | but I rely on them. | > +--------------------------------+---------------------------------+Article: 35433
Hello Maciek, Starting with ISE 4.1i, HDL Bencher is now an integrated tool rather than a separately installed application. Therefore, to launch the tool, you need to create a new source with the type 'Test Bench Waveform' Additionally, there is no need to export the testbench to the project directory as the .tbw is automatically added to Sources in Project window upon exiting HDL Bencher. In order to run simulation processes, highlight the testbench waveform and the processes will be shown in the 'Processes for Current Source' Window Note: VHDL and Verilog files are still being created along with the waveforms in the project directory. The extenstions for the files are: VHDL testbench - design_tb.vhw Verilog test fixture - design_tb.tfw I hope this helps. Best regards, Kamal Patel Ignacy Kudla wrote: >I do not have in my Project Navigator >Processess window - Design Entry Utilities >Launch HDL Bencher Tool button >What I should do to add it there? >Maciek > >Article: 35434
Hello I am completely new to this subject, so please excuse me if my question is trivial. I need to count input signal pulses at a frequency up to 500 MHz. The expected gate count of the whole logic to be synthsized is small (<20Kgates) Can someone give me any hints on what devices can support such input frequencies? How much would be the expected cost per device? Please respond on the NG, thank you in advance, Ivana.Article: 35435
Hi everyone, the program will not convert the VHDL text (which is quite in state machine manner) into a state diagram, but creates a flow chart. I also tried a template of a state machine created with Max+plus II, but no success. What are the supplementary requirements for the VHDL text, so that the conversion will work correctly? Thanks, Oliver.Article: 35436
Ivana Raffe schrieb: > > Hello > I am completely new to this subject, so please excuse me if my question > is trivial. > I need to count input signal pulses at a frequency up to 500 MHz. This is a little bit faster than DC. ;-) AFAIK there is no Xilinx part that is official operating on this frequency. There is an App-note from Peter Alfke, who did a 400 MHz frequncy counter in a 4000 device, and Iam sure the chips of today (Virtex-II) can be feed with such a high clock, but I dont think you can drive the whole chip with 500 MHz. Maybe Iam wrong. Maybe you should do some serial-parallel conversion or prescaling (using just a few FFs) and work on the half or quarter frequency for the whole chip. > The expected gate count of the whole logic to be synthsized is small > (<20Kgates) Hmm, depends on the structure of your logic. if it has small logic funtions (just one or two level, short delays, well placed), you can reach the maxim speed (official number for Virtex-II is 420 MHz ??) > Can someone give me any hints on what devices can support such input > frequencies? How much would be the expected cost per device? The small (XC2V40) Virtex-II device should be cheap, something around 10..20 $. -- MFG FalkArticle: 35437
Since I designed and built a frequency counter several years ago ( XC4002XL ) that resolves 420 MHz, here is some advice: If you want to build a complex synchronous design running at 500 MHz global clock, you may have to wait a year or so. If you want to build a frequency counter, you can design a ripple counter the way I did, and the resolution in the XC2V40 is well above 500 MHz. I tried for 1 GHz, but had to use some strange tricks to get there. If you want to measure time with 2 ns resolution, you can actually achieve 500 ps resolution if you have a 250 MHz time base frequency available. Or we can synthesize that frequency for you.. So it all depends on your real requirements... Send me e-mail. Peter Alfke, Xilinx Applications =========================================== Falk Brunner wrote: > Ivana Raffe schrieb: > > > > Hello > > I am completely new to this subject, so please excuse me if my question > > is trivial. > > I need to count input signal pulses at a frequency up to 500 MHz. > > This is a little bit faster than DC. ;-) > AFAIK there is no Xilinx part that is official operating on this > frequency. > There is an App-note from Peter Alfke, who did a 400 MHz frequncy > counter in a 4000 device, and Iam sure the chips of today (Virtex-II) > can be feed with such a high clock, but I dont think you can drive the > whole chip with 500 MHz. > Maybe Iam wrong. Maybe you should do some serial-parallel conversion or > prescaling (using just a few FFs) and work on the half or quarter > frequency for the whole chip. > > > The expected gate count of the whole logic to be synthsized is small > > (<20Kgates) > > Hmm, depends on the structure of your logic. if it has small logic > funtions (just one or two level, short delays, well placed), you can > reach the maxim speed (official number for Virtex-II is 420 MHz ??) > > > Can someone give me any hints on what devices can support such input > > frequencies? How much would be the expected cost per device? > > The small (XC2V40) Virtex-II device should be cheap, something around > 10..20 $. > > -- > MFG > FalkArticle: 35438
Nicolas Matringe wrote: > Hi all (especially the folks at Xilinx ;o) > > Does anyone know when the first Spartan2E samples will be available? We > plan to replace a VirtexE and would like to plan the design... > Thanks in advance > -- > Nicolas MATRINGE IPricot European Headquarters > Conception electronique 10-12 Avenue de Verdun > Tel +33 1 46 52 53 11 F-92250 LA GARENNE-COLOMBES - FRANCE > Fax +33 1 46 52 53 01 http://www.IPricot.com/ There's another thread on this somewhere wherein Austin Lesea said that these parts have not yet arrived at his lab for initial characterisation. I'd guess, apres l'histoire de Spartan2, there will be a fair amount of caution chez Xilinx about release dates for the parts.Article: 35439
sorry, just my first expression. I hope it is wrong... "Noddy" <g9731642@campus.ru.ac.za> schreef in bericht news:1002181956.172189@turtle.ru.ac.za... > So, essentially, what you are saying is that, given I have quite a big > design which I DEFINATELY do not want to lose, it would be wise to hold off > on upgrading > to 4.1 until I have finished with my design? Is there someone here from > Xilinx who could give a definitive answer? > > adrian > > > > > It seems that the schematics are not compatible!!! And as the my local > > application engineer from AVNET says : there is no conversion program > > available, and there will never be a conversion program available. > > > > The thing is, Xilinx wants everyone to use VHDL and/or Verilog. Here is > the > > good point, the XST synthesiser has no 'node locked' and or 'time' > > restrictions. So I think (and I hope) once installed, you never have to > look > > again for new license files, ... as for example for the synopsys stuff. > > > > The bad thing is that I've used synopsys until now and while converting a > > project from foundation to ISE, I saw that the syntax to include > > constraints(like the contents of a RAM block) in HDL (verilog in my case) > is > > different with the XST compiler. So you are fucked anyway, either > schematic > > or HDL is not fully compatible. > > > > On the other hand, you cannot wait to start using the latest software for > > new things, otherwise the gap is getting bigger and bigger. Xilinx wants > to > > sell mare and more bigger components, so the need bigger and bigger > > software. I think Xilinx (and also Altera) wants to go faster to new > > technologies than most of their customers, but everyone is forced to > follow > > them. This is the bat thing about only two really big companys on the top > of > > the programmable logic mountain. > > > > See you, > > > > Stefaan > > > > > > "Richard Dungan" <postmaster@[127.0.0.1]> schreef in bericht > > news:fdgmrt4apvaejfmq3ksgmhracbu5fhj9t4@4ax.com... > > > Hi all. > > > > > > I'm running Xilinx Foundation Base Express (the one with VHDL added on). > > > I've used this for several years and by remembering to pay for support, > > > I've avoided getting drawn into the time-based licence thing. > > > > > > I received a letter recently from Xilinx, telling me that Foundation > > > 4.1i is about to ship. All well and good. > > > > > > The letter goes to some length to extol the virtues of Xilinx' new ISE > > > package, and I'm curious as to the pros and cons of moving over to this. > > > > > > Things that particularly concern me are: > > > > > > 1) What are the licence implications? I understand that Foundation is to > > > be canned in due course. When it becomes ISE *only* will I suddenly > > > be expected to buy a time-based licence? > > > > > > 2) What kind of support does ISE give to schematic entry? I foresee an > > > ongoing need for this (partly driven from outside) for some time to > > > come. This may include updates to Foundation projects. > > > > > > Any opinions would be welcome. > > > > > > Richard > > > > > > ------------Richard Dungan------------- > > > Radix Electronic Designs, Orpington, UK > > > richardATradixDASHdesignDOTcoDOTuk > > > --------------------------------------- > > > > > >Article: 35440
>Does anyone have links to info on prototyping with BGA packages? I'm trying >to figure out what tools to buy and what the PCB layout requirements might >be for the lager BGA FPGA's. > Try Chapter 4 of PCB design considerations of Virtex II Platform FPGA Handbook.. 3M made some nice BGA adapters, check their web site.Article: 35441
> How to use built-in multipliers in virtex-II?
> Do I need to use any libraries from xilinx?
If you are synthesizing with Leonardo Spectrum, you can simply do the=20=
following:
entity mult18 is
port (
b : in std_logic_vector(17 downto 0) );
x : out std_logic_vector(36 downto 0) ;
a : in std_logic_vector(17 downto 0)=20
);
end entity mult_18;
architecture arch of mult_18 is
begin
x <=3D a * b;
end architecture arch;
Good luck,
Tom Dillon
Dillon Engineering, Inc.
www.dilloneng.com
>>>>>>>>>>>>>>>>>> Original Message <<<<<<<<<<<<<<<<<<
On 10/4/2001, 4:30:11 AM, visu_paduchuri@yahoo.com (viswanath) wrote=20=
regarding multipliers in virtex-II:
> How to use built-in multipliers in virtex-II?
> Do I need to use any libraries from xilinx?
> Rgds,
> visu
Article: 35442On Thu, 04 Oct 2001 11:39:54 GMT, Ray Andraka <ray@andraka.com> wrote: >more accurately, it is a sawtooth (modular ramp) sampled at the master >clock frequency and quantized by truncation to one bit. Hi Ray, I wouldn't say "more accurately" as this is just another way of modelling the problem. The phase accumulator output is indeed a sawtooth sampled at the master clock frequency. You can think of the MSB as a 1 bit quantised version of the phase, or you can think of it as a square wave that has been sampled. Both are equivalent, in the sense that you get identical results. Note that the square wave is virtual - there is no unjittered square wave that exists before the sampling operation that you can poke a CRO at. There is a practical difference when you come to work out the spectrum, however. The "square wave" method is much easier IMO: Take the Fourier series representation of the square wave (i.e. odd harmonics) and sample (i.e. alias) them separately. I have a spreadsheet that does this. I have designed systems that have a phase accumulator followed by an analog PLL, and you can use the spreadsheet to apply the filtering effect of the PLL to the aliased harmonics independently, then sum the result to get an estimate of the jitter on the output of the analog PLL. I usually turns out that the jitter components within the loop bandwidth of the PLL are orders of magnitude smaller than the wideband jitter (= approx one period of the master clock frequency). I can provide more details via email. (I recently used this method to design yet another SONET/SDH clock PLL.) Bye, Allan. >Allan Herriman wrote: > >> On Wed, 03 Oct 2001 06:16:53 -0000, hmurray-nospam@megapathdsl.net >> (Hal Murray) wrote: >> >> > >> >>That is in the nature of DDS. >> >>Max jitter = one clock period. >> >>If that is acceptable, go for it. >> > >> >Somehow, it seems as though I should be able to get close to >> >a half clock period. Closer "just" takes more bits of state. >> > >> >What am I missing? >> >> Another way of looking at this is to think about the output of the NCO >> as being a square wave at some frequency that has been sampled by the >> NCO clock. >> >> If the frequency of the square wave is the NCO clock divided by an >> integer, then the sampling process will produce 0 jitter. >> For most frequencies though, the sampling process produces jitter of >> up to a clock period. >> Please take the time to look at the jitter measurements that I posted >> earlier in this thread. >> >> *** >> There's a simple modification that halves this jitter. It does >> require a 50% duty cycle clock and one falling edge flip flop though. >> Email for code. >> >> Regards, >> Allan. > >-- >--Ray Andraka, P.E. >President, the Andraka Consulting Group, Inc. >401/884-7930 Fax 401/884-7950 >email ray@andraka.com >http://www.andraka.com > > "They that give up essential liberty to obtain a little > temporary safety deserve neither liberty nor safety." > -Benjamin Franklin, 1759 > >Article: 35444
"Ray Andraka" <ray@andraka.com> wrote in message news:3BBBA74A.3FE59A88@andraka.com... > You can do RLOCs in VHDL, at least with synplicity and leonardo, and have been > able to for about 2.5 years now. If you couldn't, I wouldn't be using VHDL. > Not only can you put RLOCs in, you can also use user attributes to put in TNMs, > BLKNMs, initial values and whatever else you want. The key for these critical > circuits is to treat the synthesizer as a generator rather than a synthesizer. > Works like a charm. > > By doing this for a hierarchical library, you eventually get a set of commonly > used macros that are optimized RPMs that you can instantiate in your RTL code. > That way you get both fast development AND fast performance. I miss the visual > presentation of schematics, but that is about it. You can do RLOCs and other attributes and constraints in Verilog too. Of course, Verilog lacks 'generate'. That's why my some of my recent designs generate Verilog using Python. Jan Gray, Gray Research LLCArticle: 35445
After trying out the new JTAG programming SW Impact from Xilinx with some of my PCBs, I discovered that it does not work with older CPLDs from type XC9572 and XC95216. Older CPLD means that they return a different version (0000) in their IDCODE, but from outside they look exactly the same, are named the same and behave (hopefully) the same. The answer I got from Xilinx was : FROM: John Blaine ... I have found out that Impact does not support these older XC9500 devices. With this in mind, you must continue to use the JTAG Programmer tool that you already have. ... Whats the usefulness of in system reprogrammability if you have to keep your old programming sw for every older PCB you have around? One has to keep record of all the used CPLDs only to use the right programmer afterwards. This is something I had not expected. Another disturbing point is that this is not documented by Xilinx. It would be nice if they could tell us which devices are not supported anymore and where we have to pay attention. Greetings -- Falser Klaus R&D Electronics Department Company : Durst Phototechnik AG Vittorio Veneto Str. 59 I-39042 Brixen Voice : +0472/810235 : +0472/810111 FAX : +0472/830980 Email : kfalser@IHATESPAMdurst.itArticle: 35446
Manfred Kraus wrote: > > I have Xilinx Foundation 3.3i > now, I tried WebPack ISE 4.1 > > XST seems to be much better > than Synopsys FPGA compiler. > > Question: > > How can I use the Core Generator, that > came with Foundation with WebPack ISE ? > Hi, just use it :-) There are no special issues ! The best seems to be to start the CoreGen while WebPack is running. Select the project that is opened by WebPack when CoreGen starts up. Any core that you create will add an .xco file to your WebPack project. Enjoy. MatthiasArticle: 35447
hello when playing with the Xilinx (ISE) XST synthesis tool i found that the tools names hierarchical signals like this: module/module/signalname but when i did the synthesis again whith a higher effort level, the tool named the signals like this: module_module_signalname This is very annoying if you want to constrain such a signal! does anyone have any idea why this happens?Article: 35448
"Jan Gray" <jsgray@acm.org> wrote > You can do RLOCs and other attributes and constraints in Verilog too. Of > course, Verilog lacks 'generate'. That's why my some of my recent designs > generate Verilog using Python. The more general problem is that Verilog does not recognise the notion of an attribute. Attributes are hidden inside comments, so you cannot use the Verilog language to form the values to assign to attributes. Python sounds like a good solution.Article: 35449
Rick Filipkiewicz a écrit : > There's another thread on this somewhere wherein Austin Lesea > said that these parts have not yet arrived at his lab for > initial characterisation. Yes, I remember reading it too. Anyway I have a meeting with Avnet sales people next week to discuss about that. -- Nicolas MATRINGE IPricot European Headquarters Conception electronique 10-12 Avenue de Verdun Tel +33 1 46 52 53 11 F-92250 LA GARENNE-COLOMBES - FRANCE Fax +33 1 46 52 53 01 http://www.IPricot.com/
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Threads starting:
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