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Hi all, I am searching for a free implementation of an SDRRAM controller. I would like to use SDRRAM instead of SRAM because of the bigger amount of ram per chip. Now to still let it look to the outside world i would like to add in an FPGA which transfers the bus cycles at one end (@50Mhz) to look like SDRRAM at the other end (@100/200 Mhz). Does anyone know if it is difficult to implement such a controller, or if there is any such controller for free? Hope you all can help. Thanks Richard -- Quest Innovations tel: +31 (0) 227 604046 fax: +31 (0) 227 604053 http://www.quest-innovations.comArticle: 35526
Dear Newsgroup Members,
I have been advised that the sharing of benchmark data concerning at
least one of these two products is a violation of the license agreement of
that product, and this may be true of the other product.
Please do not send me any benchmarking data that you may have obtained
in any manner from these products.
Thank you very much.
Simon Ramirez, Consultant
Synchronous Design, Inc.
Oviedo, FL USA
"S. Ramirez" <sramirez@cfl.rr.com> wrote in message
news:mqBv7.298567$8c3.54025873@typhoon.tampabay.rr.com...
> Has anyone done a trade study recently on Synplify vs. Leonardo? If
> yes and you would like to share the results, please do so here or email me
> privately. A client company has asked me to do a trade study of the
several
> products on the market, and I would like to get some preliminary
information
> on these two products. I am particularly interested in actual synthesis
> results of real application test cases. A simple description of the test
> cases along with the results is sufficient. Also, I am interested in any
> outstanding features and/or quirks of the two products.
> Thank you very much.
> Simon Ramirez, Consultant
> Synchronous Design, Inc.
> Oviedo, FL USA
Article: 35527
Dear Newsgroup Members,
I have been advised that the sharing of benchmark data concerning at
least one of these two products is a violation of the license agreement of
that product, and this may be true of the other product.
Earlier, I asked for benchmarking information, but please do not send
me any benchmarking data that you may have obtained
in any manner from these products.
Thank you very much.
Simon Ramirez, Consultant
Synchronous Design, Inc.
Oviedo, FL USA
"S. Ramirez" <sramirez@cfl.rr.com> wrote in message
news:mqBv7.298567$8c3.54025873@typhoon.tampabay.rr.com...
> Has anyone done a trade study recently on Synplify vs. Leonardo? If
> yes and you would like to share the results, please do so here or email me
> privately. A client company has asked me to do a trade study of the
several
> products on the market, and I would like to get some preliminary
information
> on these two products. I am particularly interested in actual synthesis
> results of real application test cases. A simple description of the test
> cases along with the results is sufficient. Also, I am interested in any
> outstanding features and/or quirks of the two products.
> Thank you very much.
> Simon Ramirez, Consultant
> Synchronous Design, Inc.
> Oviedo, FL USA
Article: 35528I don't know about smartmedia but I did the same thing with compact flash (got all the info I need from www.sandisk.com). But CFlash is probably easier as they *can* be put into an ATAPI compatible mode and as I already had made a CDROM controller I just modified that. The socket cost me 40$ though. I didn't use VHDL (i'm too lazy) but it did fit into a 95108 Xilinx thus saving me much wire wrapping. Hope this helps. "Andrew Gray" <s9813479@student.up.ac.za> wrote in message news:3BC3333D.3513CC62@student.up.ac.za... > Hi > > Does anyone know how to read a file from a SmartMedia card? > I would like to read an MP3 file from a SmartMedia card using VHDL. How > do I locate the start of the file, and how do I read a continuous data > stream until the end of the file? > > Thanks > > Andrew >Article: 35529
What I was trying to say was look at the manufactureres web site (ie whoever makes your smartmedia) they might have info there. "Lachlan J Follett" <wokwon@wokwon.com> wrote in message news:hMLw7.140215$bY5.686023@news-server.bigpond.net.au... > I don't know about smartmedia but I did the same thing with compact flash > (got all the info I need from www.sandisk.com). But CFlash is probably > easier as they *can* be put into an ATAPI compatible mode and as I already > had made a CDROM controller I just modified that. The socket cost me 40$ > though. I didn't use VHDL (i'm too lazy) but it did fit into a 95108 Xilinx > thus saving me much wire wrapping. > > Hope this helps. > > "Andrew Gray" <s9813479@student.up.ac.za> wrote in message > news:3BC3333D.3513CC62@student.up.ac.za... > > Hi > > > > Does anyone know how to read a file from a SmartMedia card? > > I would like to read an MP3 file from a SmartMedia card using VHDL. How > > do I locate the start of the file, and how do I read a continuous data > > stream until the end of the file? > > > > Thanks > > > > Andrew > > > >Article: 35530
Michael, We have done many image processing algorithms on high resolution and hig= h=20 frame rate images. Including a 4M two dimensional FFT at 120 fps. We can help. Check out our web site, specifically our FFT and Convolution IP Cores. We are currently working on what will the the fastest JPEG2000 Core=20 available. Regards, Tom Dillon Dillon Engineering, Inc. http://www.dilloneng.com >>>>>>>>>>>>>>>>>> Original Message <<<<<<<<<<<<<<<<<< On 10/9/01, 12:19:20 PM, "Michael Feygin" <Mfeygin@cubictechnologies.com= >=20 wrote regarding Help in speeding up image processing: > Dear list, > We have an application where we need to generate and send to a digital= > projector and capture by a megapixel digital camera up to 40 images pe= r > second. Each image should be digitally processed in a real time. The > operations will be relatively simple mostly logical commands applied t= o > every pixel of each image. We would like to know what hardware would = be > most advantageous for this project (DSP? FPGA? or other?). > We would be interested in a consulting help in this area. Proximity t= o=20 Los > Angeles area is prefered. > Michael Feygin > 310-965-0129 > e-mail: Mfeygin@cubictechnologies.comArticle: 35531
420 MHz. It says so ( and has said so for a long time ) on line 4 on the front page of the data sheet. We never miss an opportunity to brag about such numbers :-) What could possibly be gained by dividing the frequency down? The frequency stability is determined by the clock input, provided by the user, not by Xilinx. Most likely this is at a much lower frequency, which the Xilinx device then multiplies up. Most users prefer an oscillator in the 50 MHz region, many want an even lower frequency. Peter Alfke, Xilinx Applications Speedy Zero Two wrote: > Do they not provide that in the datasheet? > > "himanshu" <himan_2000@indiatimes.com> wrote in message > news:adf7cebe.0110080015.832fe8d@posting.google.com... > > Hi, > > can any body tell me what is the maximum clock speed at which xilinx > > virtex-2 fpga can work?? It has got 8 DLLs..what is the maximum clock > > rate they can provide. do i have to divide that frequency for clock > > stability? > > Thanks in advance > > HimanshuArticle: 35532
Did you make the recommended connection: INIT driving the SPROM Reset ? Xilinx has promoted this as the only reasonable and safe method for at least the past eight years, way back in the XC3000 data sheet. ( I remember, I was the one putting it in, and even explaining the reason why ). Without that connection you can encounter all sorts of grief... With this connection, you would only have a problem if the power-on reset is longer in the SPROM than it is in the FPGA. To the best of my knowledge, that has been the case only in certain Atmel SPROMs. But I am listening...One never stops learning. Peter Alfke, Xilinx Applications =============================== Tom Seim wrote: > My greatest grief with Xilinx (right after the blunder Xilinx made > switching suppliers of the serial proms - the new supplier couldn't > deliver as scheduled and the old one had been axed) has been the > power-up sequencing. The FPGAs and serial proms have internal power-up > sequencing circuitry so you think: "I'm ok using that". Wrong. > I have seen the serial prom & FPGA get out of sync due to either too > fast/slow Vcc rise time and/or a small spike on Vcc at the wrong > moment. The serial prom's address counter will keep going & eventually > recycle, but this takes forever! I've ALWAYS used a seperate power > reset circuit after that. > > "Austin Franklin" <austin@darkroom88.com> wrote in message news:<ts62seat66qg87@corp.supernews.com>... > > Just a note on using GSR-not using GSR with synthesis. GSR routing is free, > > it is dedicated copper...and can be used for nothing else. If you do NOT > > use GSR, and have a reset in your design (as you probably should) you are > > using regular routing resources for this possibly very prolific global net. > > In order for synthesis to use GSR (at least Synplicity) EVERY flop must be > > attached to GSR, or it will use regular routing resources. > > > > Why are using regular routing resources bad? If your design is quite full, > > it can significantly impact timing and tool run time. One design I had in > > an XCV300 went from 45 minutes to 9 minutes PAR time when I used GSR. > > > > As Philip's post suggests (hell, says), it is VERY easy to still use the GSR > > and design such that this does not create any problems with your design. It > > just takes a little understanding of how your design works, and a bit of > > engineering. > > > > "jas" <jasjasjasjas@hotmail.com> wrote in message > > news:fe3da0d7.0110082249.42642566@posting.google.com... > > > Hi, > > > > > > Are there timing issues on a Spartan device if the reset is > > > asynchronous to the system clock, i.e could a problem occur where by > > > the device is taken out of reset on the active clock edge, hence > > > certain registers in the device remain in reset and the others are > > > not. If so how is this solved, by registering the reset and not > > > reseting that register?. > > > > > > Thanks > > > > > > jonArticle: 35533
"S. Ramirez" <sramirez@cfl.rr.com> writes: > Dear Newsgroup Members, > I have been advised that the sharing of benchmark data concerning at > least one of these two products is a violation of the license agreement of > that product, and this may be true of the other product. Just out of curiosity, which one ? Zoltan -- +------------------------------------------------------------------+ | ** To reach me write to zoltan in the domain of bendor com au ** | +--------------------------------+---------------------------------+ | Zoltan Kocsi | I don't believe in miracles | | Bendor Research Pty. Ltd. | but I rely on them. | +--------------------------------+---------------------------------+Article: 35534
I know this is "controversial" but this kind of crap just really "irks" me... > I have been advised that the sharing of benchmark data concerning at > least one of these two products is a violation of the license agreement of > that product, and this may be true of the other product. I am curious who "advised" you? I'm also curious as to the actual enforceable legality of such an inclusion into the license agreement. An agreement can contain anything it wants (they can even ask you to agree to not pick your nose while using their tools), but whether it's legally enforceable is another matter entirely. This is my take on it...and is only my opinion. If this purported violation even has any legal grounds... It's certainly not a criminal activity...and not being such, it has to fall into civil litigation. In civil cases, you have to prove damages...and as far as I know, stating something that is factually true, unless done maliciously, does not give grounds for damages. Can you imagine a company suing someone because they published a benchmark that showed that their product actually sucked? Anyone know anything about this...aside from that it's childish to even put such a clause in a license agreement in the first place... Imagine buying a car (or a pencil for that matter) that came with a "license agreement" that you could not "share" the comparison of your car (or pencil) with any other car...think about how, well, just plain silly (and pathetic) that is.Article: 35535
Andrew Gray <s9813479@student.up.ac.za> wrote in message news:<3BC3333D.3513CC62@student.up.ac.za>... Hi Andrew, you can check at http://www.ssfdc.or.jp/english/smil/index.htm here you can find both the hardware and the software specification for the SmartMedia, which was disclosed last year to the general public. I agree with the other guy when he says that it will not be an easy task, though, since with a SmartMedia you have to implement all those stuff which, in a FlashCard with a microcontroller on board, is done by the microcontroller itself... good luck! Hope that helps SteveArticle: 35536
Richard Meester <rme@quest-innovations.com> writes: > Hi all, > > I am searching for a free implementation of an SDRRAM controller. I > would like to use SDRRAM instead of SRAM because of the bigger amount > of ram per chip. Now to still let it look to the outside world i would > like to add in an FPGA which transfers the bus cycles at one end > (@50Mhz) to look like SDRRAM at the other end (@100/200 Mhz). > > Does anyone know if it is difficult to implement such a controller, or > if there is any such controller for free? > Altera have an SDRAM controller (one 'R', unless you're talking about something different - in which case ignore me :-) which is available for free. Opencores also have a verilog core at http://www.opencores.org/ . I have experience of neither - I wrote my own, it wasn't too hard. You won't be able to achieve continuous 50MHz SRAM emulation for random access I wouldn't imagine - there are limits on how quickly you can strobe RAS. According to the datasheet I have in front of me, which is for a Micron PC133 part, tRC is 60ns. If you are bursting then you can transfer higher data rates, but you still have the latency issue to deal with. Going to 200MHz, I assume you mean double-data rate (DDR) which speeds up the burst, so you have a higher peak burst data rate, but AFAIK the setup and such like are much the same as on SDR. > Hope you all can help. > Hope I did! Cheers, Martin -- martin.j.thompson@trw.com TRW Automotive Technical Centre, Solihull, UKArticle: 35537
"Rad=F3 Zolt=E1n" wrote:
> Hey, Listers!
> =
> I've got two questions:
> =
> 1.
> How do you simplify this so that only one PORT MAP section left?
> =
> out_fifo_a: fifo128x8 port map (
> clk =3D> clk, sinit =3D> not_reset, din =3D> wsample(0), wr_en =3D> =
WE_Sample(0),
> rd_en =3D> frame_clk_oc, dout =3D> Sin_a1, full =3D> open, empty =3D=
> open);
> =
> out_fifo_b: fifo128x8 port map (
> clk =3D> clk, sinit =3D> not_reset, din =3D> wsample(1), wr_en =3D> =
WE_Sample(1),
> rd_en =3D> frame_clk_oc, dout =3D> Sin_b1, full =3D> open, empty =3D=
> open);
> =
> out_fifo_c: fifo128x8 port map (
> clk =3D> clk, sinit =3D> not_reset, din =3D> wsample(2), wr_en =3D> =
WE_Sample(2),
> rd_en =3D> frame_clk_oc, dout =3D> Sin_a2, full =3D> open, empty =3D=
> open);
I hope your synthesis tool supports the following:
FIFO : for I in ( generic_value - 1 ) downto 0 generate
out_fifo : fifo128x8
port map (
clk =3D> clk,
sinit =3D> not_reset, =
din =3D> wsample(2), =
wr_en =3D> WE_Sample(2),
rd_en =3D> frame_clk_oc, =
dout =3D> Sin_a2, =
full =3D> open, =
empty =3D> open);
end generate FIFO;
Unfortunately the instantiation names for each fifos are the same(here ou=
t_fifo),
but only in the VHDL code. The synthese tool should normally enumerate th=
em one by
one.
> 2.
> How do you simplify this so that only one data_out line left at the=
end?
> =
> data <=3D data_out(0) when read_fifo(0) =3D '1' or read_status(0) =3D '=
1' else
> data_out(1) when read_fifo(1) =3D '1' or read_status(1) =3D '1' el=
se
> data_out(2) when read_fifo(2) =3D '1' or read_status(2) =3D '1' el=
se
> data_out(3) when read_fifo(3) =3D '1' or read_status(3) =3D '1' el=
se
> data_out(4) when read_fifo(4) =3D '1' or read_status(4) =3D '1' el=
se
> data_out(5) when read_fifo(5) =3D '1' or read_status(5) =3D '1' el=
se
> "00000000" & data_out_spi when read_spi_status =3D '1' or
> read_spi_datareg =3D '1' else
> msg_data when msg_rd_stat =3D '1' else
> "ZZZZZZZZZZZZZZZZ";
For this I would define a bigger array, which consists
the following:
(data_out(0..5),"00000000" & data_out_spi,"ZZZZZZZZZZZZZZZZ")
Furthermore 1 control vector having the values you have to
use for your input selection for 'data':
(read_fifo(0..5) & read_status(0..5),read_spi_status & read_spi_datareg,
msg_rd_stat & '1')
Don't forget to use the generic also for the previously declared =
vectors!
Then you write a simple for-loop or for-generate cycle to replace the =
long when-else statement. =
> The aim is to have a constant defined in GENERIC that tells how much PO=
RT
> MAP and DATA OUT section is needed.
> =
> Thanks for all...
Szivesen:-) =
_____
Tamas
Article: 35538--------------46A2A865667AF24F3E106CFA Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Hi can anyone help me with the following problem. I have an input into an entity, this input is called Data_Train. I tried to link it to an LPM shift register generated by the Maxplus wizard. I used a port map to map Data_Train to the shiftin input of the shift register. When I compile the project Maxplus generates the error: Warning: Ignored unneccessary INPUT pin 'Data_Train' Can anyone help me? Thanks Andrew --------------46A2A865667AF24F3E106CFA Content-Type: text/html; charset=us-ascii Content-Transfer-Encoding: 7bit <!doctype html public "-//w3c//dtd html 4.0 transitional//en"> <html> Hi can anyone help me with the following problem. <p>I have an input into an entity, this input is called Data_Train. <p>I tried to link it to an LPM shift register generated by the Maxplus wizard. <p>I used a port map to map Data_Train to the shiftin input of the shift register. <p>When I compile the project Maxplus generates the error: <br><i>Warning: Ignored unneccessary INPUT pin 'Data_Train'</i> <p>Can anyone help me? <p>Thanks <br>Andrew</html> --------------46A2A865667AF24F3E106CFA--Article: 35539
hi,
Who knows the news server of synplicity?
Sincerely,
Justin
Article: 35540Justin Cui wrote: > hi, > Who knows the news server of synplicity? > > Sincerely, > Justin server DNS address is news:news.synplicity.com UtkuArticle: 35541
This is a multi-part message in MIME format. --------------C16173A989D758F6C6410C79 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Hi all, I'm working on an fpga project which should include a 'the keyboard part' of the good old 8279 keyboard/display controller. The design should be sw-compatible to the keyboard part. So the question is : Is there anybody out there who has the vhdl-code available for this device, other then a costly IP-core. Kind regards, Please reply to Rini_van_Dijk@hotmail.com --------------C16173A989D758F6C6410C79 Content-Type: text/x-vcard; charset=us-ascii; name="Rini.vDijk.vcf" Content-Transfer-Encoding: 7bit Content-Description: Card for Rini.vDijk Content-Disposition: attachment; filename="Rini.vDijk.vcf" begin:vcard n:Dijk;Rini van x-mozilla-html:FALSE org:Philips Medical Systems Nederland BV version:2.1 email;internet:Rini.vDijk@best.ms.philips.com tel;fax:031-(0)40 2762601 tel;work:031-(0)40 2763271 adr;quoted-printable:;;Development Surgery=0D=0AQP2420;Best;;;Nederland x-mozilla-cpt:;0 fn:Rini van Dijk end:vcard --------------C16173A989D758F6C6410C79--Article: 35542
Hello, does anybody use this Handel-C stuff from Celoxica / Oxford University ? Where can one find some detailed information about the language? Does a specification exist? The info on Celoxica website is not very detailed (or my look was not detailed enough...) and the info on Oxford homepage seem to be outdated, since Ian Page resigned from the institute. I need to implement some high level 3D image processing algorithms as fast as possible and thought this Handel-C stuff could be suitable or at least more comfortable then VHDL encoding (argl...). What about floating point? It was mentioned, that it is supported. Do they really have floating point libs for their compiler ? Would be cool! Thanks in advance, ER!K -- Posted from dialin-145-254-194-052.arcor-ip.net [145.254.194.52] via Mailgate.ORG Server - http://www.Mailgate.ORGArticle: 35543
Ben wrote: try www.snelwilcox.com, www.tandbergtv.com these 2 companies produce lots of video "boxes". they have links to appropriate literature (some of it downloadable). Ahmed... > Hi, > I'm doing a literature search for my university project. This is based on > real-time digital video processing using FPGA technology. > > Does anyone out there have any recommendations for book, papers, websites > or magazine articles worth reading, or people worth speaking to on the > subject? > I've been to Xilix, Altera etc, but want to get as much information as > possible. > > Any information greatly appreciated, > Ben. > > >Article: 35544
I have seen previous discussion concerning frequency synthesis with DCM. As far as I remember there are restrictions on the combinations of M/D. M is the multiplication factor and D is the division factor of the input frequency. I am working now on a design for a XCV2 2000 that uses an internal clock of 100 MHz. This clock is generated by a DCM from an external clock source of 27 MHz. Therefore, my M/D is 100/27. Does the DCM support M/D=100/27 ? Hermann WinklerArticle: 35545
Dear All, I have obtained the I and Q signals using a qpsk demodulator IC. What I need is to derive the clock from the I Q data. This must be a simple task, but could not find any examples. The data rate is >10Mbps. What kind of DSP-FPGA combination is needed? Are there any DSP or VHDL sources? ThanksArticle: 35546
The low level interface of a smart media card is identical to a standard nand flash chip. Information on this can be found for example on the AMD web page. This tells you how to read and write bytes from the device. The easiest way to use this would be to write your own VHDL to write the MP3 bitstream continuously into the flash using some simple interface to communicate with the source of the date. (Presumeably a PC) If on the other hand you want to read data that got onto the card in some standard way, you must implement the file system that is used by these cards. This could be quite complex. I would suggest you implement a small CPU on you FPGA (www.fpgacpu.org) and then port an existing open source implementation of the file system to the CPU. There are for example PIC clones available for FPGA and I am pretty sure that code to access SmartMedia file systems exists for PICs. Kolja Sulimma Lachlan J Follett wrote: > What I was trying to say was look at the manufactureres web site (ie whoever > makes your smartmedia) they might have info there. > > "Lachlan J Follett" <wokwon@wokwon.com> wrote in message > news:hMLw7.140215$bY5.686023@news-server.bigpond.net.au... > > I don't know about smartmedia but I did the same thing with compact flash > > (got all the info I need from www.sandisk.com). But CFlash is probably > > easier as they *can* be put into an ATAPI compatible mode and as I already > > had made a CDROM controller I just modified that. The socket cost me 40$ > > though. I didn't use VHDL (i'm too lazy) but it did fit into a 95108 > Xilinx > > thus saving me much wire wrapping. > > > > Hope this helps. > > > > "Andrew Gray" <s9813479@student.up.ac.za> wrote in message > > news:3BC3333D.3513CC62@student.up.ac.za... > > > Hi > > > > > > Does anyone know how to read a file from a SmartMedia card? > > > I would like to read an MP3 file from a SmartMedia card using VHDL. How > > > do I locate the start of the file, and how do I read a continuous data > > > stream until the end of the file? > > > > > > Thanks > > > > > > Andrew > > > > > > >Article: 35547
"Erik Lins" <erik@lins.de> wrote > The info on Celoxica website is not very detailed (or my > look was not detailed enough...) and the info on Oxford homepage seem to be > outdated, since Ian Page resigned from the institute. What became of Ian?Article: 35548
Can anyone recomend a contract assembler for a few small printed
circuit boards that will contain a BGA based package? The production
quantities will be quite small (10 pieces for the first run, no more
than 50 pieces for subsequent runs) but I cannot assemble or inspect BGA
packages. I am especially interested in manufacturers in the midwestern
USA and especially in Michigan.
Thanks,
Theron Hicks
Article: 35549
You need to basically do a digital phase lock loop that will fill in
missing pulses, then have it lock to synchronous edge detects of your
data. A DPLL is basically counters running from a higher master clock,
with the count modulus adjusted by the error when the next edge comes
along. I prefer to use a direct digital synthesizer (phase accumulator)
to generate the frequency, and adjust the increment value to reduce the
error. The error feedback is where it can get tricky, especially if you
need to capture over a wide range.
eas wrote:
> Dear All,
> I have obtained the I and Q signals using a qpsk demodulator IC.
> What I need is to derive the clock from the I Q data. This must be a
> simple task, but could not find any examples. The data rate is
> >10Mbps. What kind of DSP-FPGA combination is needed? Are there any
> DSP or VHDL sources?
>
> Thanks
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
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