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I have their evaluation version but my design exceeds the memory limitation. Arthur Sharp <arthur@nospam.com> wrote in message news:3bf98132$0$21711$afc38c87@news.optusnet.com.au... > > "Andrew Gray" <andrewgray@iafrica.com> wrote in message > news:3bf946c4.0@news1.mweb.co.za... > > Hi > > > > Does anyone know where I can get hold of a full-version licence for > > Modelsim? I only need it for 2 or 3 days. > > You should be able to get an evaluation license for Modelsim for 20-30 days > from their site. > > > > > Is there any alternative VHDL simulator like modelsim that is freely > > available? > > As good as Modelsim, for free, not really. > > > > > Thanks > > > > Andrew > > A.S. > >Article: 36776
Andy Peters wrote: > > Russell Shaw wrote: > > > I traced from the clock input pin to the clock divider, and looked at > > the fanout from the last flip-flop. I found there were a few counters > > implemented as scattered logic, not being recognized as counter > > templates. I found just one or two extra lines in a process can prevent > > recognition by the compiler as a counter. > > I noticed that about Leonardo -- it's VERY picky about what it considers > a counter. > > What's bizarre is that I ran Leonardo on two different machines (one a > Sparc running Solaris 7, the other running Solaris 2.5) and I got > different results (the 2.5 machine did the right thing for a counter; > the S7 machine didn't!) for identical code with identical scripts. I > haven't gotten to the bottom of that one yet. > > Moral: pay attention to the report and log files. Maybe there's an option for time-limiting the optimizations. Did the faster machine optimize better?Article: 36777
--------------C3B9749BDAE72B58F3470A77 Content-Type: text/plain; charset=us-ascii; x-mac-type="54455854"; x-mac-creator="4D4F5353" Content-Transfer-Encoding: 7bit rickman wrote: > Are the DCM on the Virtex II chips fully functional? I have heard > through the grapevine that there are problems. I have not heard anything > specific, just that I should check with Xilinx before planning to use > the DCM. Virtex-II production devices ( the ones not marked ES ) do everything the data sheet promises ( see http://www.xilinx.com/partinfo/ds031.htm ). Engineering samples ( marked ES ) have the following restrictions: The frequency synthesis output FX can have values of M and D up to 32, but the M/D quotient may not exceed 4. (This limits the min input frequency to about 6 MHz min) In ES devices, the vatiable phase shift function ( increment or decrement by clock period divided by 256 ) does not work. This is fixed in 3000ES, and of course in all production ( non-ES ) devices. Peter Alfke, Xilinx Applications --------------C3B9749BDAE72B58F3470A77 Content-Type: text/html; charset=us-ascii Content-Transfer-Encoding: 7bit <!doctype html public "-//w3c//dtd html 4.0 transitional//en"> <html> <p>rickman wrote: <blockquote TYPE=CITE>Are the DCM on the Virtex II chips fully functional? I have heard <br>through the grapevine that there are problems. I have not heard anything <br>specific, just that I should check with Xilinx before planning to use <br>the DCM.</blockquote> Virtex-II production devices ( the ones not marked ES ) do everything the data sheet promises ( see <u><A HREF="http://www.xilinx.com/partinfo/ds031.htm">http://www.xilinx.com/partinfo/ds031.htm</A></u> ). <p>Engineering samples ( marked ES ) have the following restrictions: <p>The frequency synthesis output FX can have values of M and D up to 32, <br>but the M/D quotient may not exceed 4. (This limits the min input frequency to about 6 MHz min) <p>In ES devices, the vatiable phase shift function ( increment or decrement by clock period divided by 256 ) does not work. This is fixed in 3000ES, and of course in all production ( non-ES ) devices. <p>Peter Alfke, Xilinx Applications</html> --------------C3B9749BDAE72B58F3470A77--Article: 36778
Hello all, I'm new to the newsgroup and am curious if anyone has VHDL code for a 16 bit full ISA interface. Everything seems to PCI from what I can see, and I don't require that level of complexity. If you could help me out or point me to a source I would be most appreciative. ThanksArticle: 36779
Talk to the sales droid. If you can convince him that you are a serious
prospect, you can get him to turn off the memory limitation for the 20-30 day
eval.
Andrew Gray wrote:
> I have their evaluation version but my design exceeds the memory limitation.
>
> Arthur Sharp <arthur@nospam.com> wrote in message
> news:3bf98132$0$21711$afc38c87@news.optusnet.com.au...
> >
> > "Andrew Gray" <andrewgray@iafrica.com> wrote in message
> > news:3bf946c4.0@news1.mweb.co.za...
> > > Hi
> > >
> > > Does anyone know where I can get hold of a full-version licence for
> > > Modelsim? I only need it for 2 or 3 days.
> >
> > You should be able to get an evaluation license for Modelsim for 20-30
> days
> > from their site.
> >
> > >
> > > Is there any alternative VHDL simulator like modelsim that is freely
> > > available?
> >
> > As good as Modelsim, for free, not really.
> >
> > >
> > > Thanks
> > >
> > > Andrew
> >
> > A.S.
> >
> >
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 36780Hi all tools come from FPGA vendor are very slow, include ISE and quartus, I synthesis my design(nnARM at about 150,000 gate) in ISE and Quartus, both took me about 4 hours(in Athlon 1G), but with synplicity pro, synthesis take only 44 minites, and another 2 hour to fit in Quartus II But Synplicity's synthesis result sometimes is very bad, it generate a very long cascade chain in my APEX20K400E, so I must divide the chain into tree like structure in RTL code. I think it is better to use Synplicity Pro to syn and then use Quartus or ISE to place and route, but you must write your RTL code more carefully khtsoi@cse.cuhk.edu.hk wrote in message news:<9sqnh1$j6u$1@eng-ser1.erg.cuhk.edu.hk>... > Hi, > > Someone told me that tools from Synplicity is better than the Synopsys > Xilinx combination in FPGA place and route process. I am sick with the > bad routing design in Alliance3.1i. Also, it takes me more than 1 day > to par a design using only 45% slices of a XCV1000E (on a Sun E4500). > > I really hope someone can give me some advices about the performance > of the Synplicity tools. I will use it on either or both Sun E4500 with > SunOS and P4 1.4GHz PC with Win/Linux. Does anyone has experience on > implementing a design in similar size under these environment? Also, > most of my current design is developed under Synopsys Design Compiler > which cannot be synthsised directly on FPGA Express. Can the Synplicity > tools under the synopsys coding style? Last, is there any performance > differences between the commercial version and evaluation version? > > ---- Brittle > > PS I am now downloading the evaluation version of Synplify.Article: 36781
the free or evalueation version have limit on the size of the design, my design(nnARM,150,000 gate after syn) can not sim in Modelsim eva version, it kill modelsim immediately, and the ActiveHDL still live, but become a dumb stupid "Seb" <someone@microsoft.com> wrote in message news:<P9bK7.8929$98.1458446@zwoll1.home.nl>... > Hello all. > > With our ISE tools, we got Modelsim Xilinx edition, but no license. > We installed the free version, it runs fine, also with the Xilinx > components. > > My question: what is the difference (what are the nags) between the three > Modelsim versions on the cd: > - full version > - evaluation version > - free version > > thanx > cheers, > SebArticle: 36782
I have APEX20k400E prototype board, but the doc say only SPEX20KE/KC can imply CAM, fow can I deal with thisArticle: 36783
Hi www.opencores.org have prototype board that hold Virtex, and maybe they also have spartan version, and I think you can search some research group of univ on web and Xess(www.xess.com) sell fpga board at very low price for education purpose tt889@163.net (apple88888) wrote in message news:<c99f3d6.0111171400.20ad425e@posting.google.com>... > It may like Spartan-II PCI develop board(DS-PCI32S-KIT2) or something like this. > > remail me : tt889@163.netArticle: 36784
I need such a device to mply my design, but I must decide on its price, but I can not find its price on xilinx site.and further about XC2V10000.Article: 36785
6K is biggest part in production. Prices on www.findchips.com "ssy" <shengyu_shen@hotmail.com> wrote in message news:f4a5f64f.0111192004.7adf8716@posting.google.com... > I need such a device to mply my design, but I must decide on its > price, but I can not find its price on xilinx site.and further about > XC2V10000.Article: 36786
Can anyone help in getting a VHDL Design (done in Active-VHDL) synthesised? Is any extra software necessary to do that? Thanks in advance.Article: 36787
"Andrew Gray" <andrewgray@iafrica.com> wrote in message news:3bf9932d.0@news1.mweb.co.za... > I have their evaluation version but my design exceeds the memory limitation. You could try downloading the Xilinx version from the Xilinx web site. I've a feeling it might be the full version, but only for Xilinx chips. I haven't noticed any mention of restrictions. Leon -- Leon Heller, G1HSM leon_heller@hotmail.con http://www.geocities.com/leon_heller Low-cost Altera Flex design kit: http://www.leonheller.comArticle: 36788
Sorry, I've just checked the Xilinx version. It is only for small designs. -- Leon Heller, G1HSM leon_heller@hotmail.con http://www.geocities.com/leon_heller Low-cost Altera Flex design kit: http://www.leonheller.comArticle: 36789
Good Morning,
I've the following counter divider 3 , my problem is that it works
only at a maximum of 150MHz while I need to keep it working to 165 MHz
at least on a Xilinx XCV1000 BG560 -4 . I try to use Synplify Pro that
tells that to speed up I've to "changing pad type from OBUF to
OBUF_F_24 for pad clk_div_3_obuf to improve timing" and the same for
"count_3_obuf" but how I could do this ??
Following is the counter, by the way do you have in mind another way
to speed it up (other than buy another device !!!). Ciao
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity counter_divider_3 is
port (
clk : in STD_LOGIC;
reset : in STD_LOGIC;
count_3 : out STD_LOGIC_VECTOR (2 downto 0);
clk_div_3 : out STD_LOGIC
);
end counter_divider_3;
architecture counter_divider_3_arch of counter_divider_3 is
signal int_count_3 : STD_LOGIC_VECTOR (1 downto 0) ;
signal reset_clk_a_b : STD_LOGIC_VECTOR (3 downto 0) ;
signal count_0_delayed : STD_LOGIC;
begin
process (clk, reset)
begin
if reset='1' then
int_count_3 <= "01";
elsif rising_edge(clk) then
-- & funziona come aggregatore di bit non un and logico !!
int_count_3 <= int_count_3(0) & not(int_count_3(0) or
int_count_3(1));
end if;
end process;
process(clk)
begin
if falling_edge(clk) then
count_0_delayed <= int_count_3(0);
end if;
end process;
clk_div_3 <= int_count_3(0) nor count_0_delayed;
with int_count_3 select
count_3 <= "010" when "00" ,
"001" when "10" ,
"000" when "01" ,
"XXX" when others;
end counter_divider_3_arch;
Article: 36792Andy Peters <andy@exponentmedia.deletethis.com> wrote in message news:<3BF96DA4.B8172C4C@exponentmedia.deletethis.com>... > Assaf Sarfati wrote: > > > > Hi everyone, > > > > I am trying to simulate the gate-level VHDL file generated by Xilinx > > P&R tools. My test design is a bunch of counters connected to an > > inferred distributed-RAM. The target device is a Virtex-2 chip. > > > > When I simulate the gate-level VHDL by itself, I get timing violation > > warnings (sometimes) when writing to the distributed-RAM; watching the > > simulator waveforms, it appears that the clock to the RAM has a 100-pS > > phase difference to the counters' clock (the clock is routed as a > > global clock net). > > That sounds like one of Xilinx' bad models. I've looked through the > Xilinx functional models, and there's all sorts of things like: > > foo_i <= foo after 1 ps; > > and such. I've ranted before: there should be NO timing information in > a FUNCTIONAL model. Check the archives of comp.lang.vhdl for more on > that subject. Summary: the Xilinx people oughta learn how to write > proper models. > > > When I add the gate-level SDF file to the simulation, all the timing > > violation warnings disappear (for all cases: min, max and typ). > > Right, because the post-route delay information is "real." > > > Trying to trace the generated VHDL code, I see that signals are routed > > through buffer entities, with built-in delays; apparently the VHDL > > design itself contains all required delays. > > Again: why does a functional model have timing info? > > --a What I'd really like is the ability to generate two gate-level models: one with full timing info (which would be accurate and slowwww) and one which is good for cycle-based simulations; I would use the first model for checking timing problems which hadn't been caught in static timing analysis; I'd use the second for functional verification. I think that Xilinx (and others) don't like to generate a functional-only model because it may be synthesizable; it may then allow me to re-target and synthesize IPs to which I don't have the source (e.g. Xilinx PCI core). Regards Assaf SarfatiArticle: 36793
Hey all. For a project in VHDL, it was suggested by a colleague of mine for doing RAM intensive applications, that it is easier to instantiate a small RAM as opposed to creating an array of std_logic_vector. I was passed on this code, however when synthesizing for an XCV-800 (Virtex I) using Synplicity Synplify Pro 7.0, it for some odd reason uses 1024 tri-buffs! (BUFFT). The same code works fine in Spectrum (I checked) and I told works with XSV synthesis. Neither use BUFFTs or an inordinate amount. I can't get this simple code to even P&R in Foundation (after being synthesized by Synplicity), I am told that I cannot have more than 86 BUFFTs on a net and that I actually have 4 sets of 256 BUFFTs. Any ideas on how to correct? Code is as follows: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity ram is port (clk : in std_logic; we : in std_logic; a : in std_logic_vector(11 downto 0); di : in std_logic_vector(3 downto 0); do : out std_logic_vector(3 downto 0)); end ram; architecture syn of ram is type ram_type is array (4095 downto 0) of std_logic_vector (3 downto 0); signal RAM : ram_type; signal read_a : std_logic_vector(11 downto 0); begin process (clk) begin if (clk'event and clk = '1') then if (we = '1') then RAM(conv_integer(a)) <= di; end if; read_a <= a; end if; end process; do <= RAM(conv_integer(read_a)); end syn; Thanks! VR.Article: 36794
Austin Franklin <austin@da22rkroom.com> wrote: > I thought I had a full installation of the latest 3.x tools...and brought up > the FPGA Editor...but it doesn't seem to allow me to select any of the > Virtex 2 parts... Does anyone know if this is supposed to be available in > FPGA Editor with the 3.x tools? If not, then is it available with the 4.x > tools? You need 3.1i, plus the Virtex-II device update, plus service pack 8, installed in that order. The device update includes service pack 6, but if you install it after SP8, you need to reinstall SP8. I don't know if you can download the device update. I have it on CD-ROM. I'd stick with 4.1i SP2 anyway -- much better for new designs IMHO. Hamish -- Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>Article: 36795
The EP20K400E device is part of the APEX 20KE family and so it supports the implementation of CAM in it's ESBs (Embedded System Block). - Wolfgang http://www.elca.de "ssy" <shengyu_shen@hotmail.com> schrieb im Newsbeitrag news:f4a5f64f.0111191945.bb9c30d@posting.google.com... > I have APEX20k400E prototype board, but the doc say only SPEX20KE/KC > can imply CAM, fow can I deal with thisArticle: 36796
A recursive approach is preferred in a synthesis environment here. As suggested, check google for details that I gave already. Russell Shaw wrote: > > Hi all, > > There's an exponent operator (**), but no log-base-2 (from what > i could see). Such a function (with integer result) would be useful > would it not?: > > constant MAXADDR: natural:=1000; > . > . > . > signal addrcntr:unsigned(LOG2(MAXADDR) downto 0); > > LOG2 should round upwards. > > Could a function be written to do it?Article: 36797
Hi, Bharathi wrote: > Can anyone help in getting a VHDL Design (done in Active-VHDL) synthesised? > Is any extra software necessary to do that? > Thanks in advance. > You need a synthesis tool. You may check out section 4.3 (part 1) of the VHDL FAQ: http://www.vhdl.org/comp.lang.vhdl/FAQ1.html#4.3 Xilinx provides a free tool chain (WebPack) including a synthesis tool. See http://www.xilinx.com -- EdwinArticle: 36798
Subject explains: What is the most obvious difference between MAX3000A and MAX7000A (3.3 V) devices? Everything seems to be same: speed grade, I/O support, JTAG. The only difference I can find so far is that MAX7000A is a family of wider gate-count spectrum. UtkuArticle: 36799
That is the exact code that Exemplar Leonardo will turn into a=20 "write_first" block RAM. Tom Dillon Dillon Engineering, Inc. http://www.dilloneng.com >>>>>>>>>>>>>>>>>> Original Message <<<<<<<<<<<<<<<<<< On 11/20/01, 3:57:02 AM, VR <thisisntvalid@invaldireturn.co> wrote=20 regarding Synplicity and BlockRAM?: > Hey all. > For a project in VHDL, it was suggested by a colleague of mine for doi= ng > RAM intensive applications, that it is easier to instantiate a small R= AM > as opposed to creating an array of std_logic_vector. > I was passed on this code, however when synthesizing for an XCV-800 > (Virtex I) using Synplicity Synplify Pro 7.0, it for some odd reason u= ses > 1024 tri-buffs! (BUFFT). > The same code works fine in Spectrum (I checked) and I told works with= =20 XSV > synthesis. Neither use BUFFTs or an inordinate amount. > I can't get this simple code to even P&R in Foundation (after being > synthesized by Synplicity), I am told that I cannot have more than 86= > BUFFTs on a net and that I actually have 4 sets of 256 BUFFTs. > Any ideas on how to correct? Code is as follows: > library IEEE; > use IEEE.STD_LOGIC_1164.ALL; > use IEEE.STD_LOGIC_ARITH.ALL; > use IEEE.STD_LOGIC_UNSIGNED.ALL; > entity ram is > port (clk : in std_logic; > we : in std_logic; > a : in std_logic_vector(11 downto 0); > di : in std_logic_vector(3 downto 0); > do : out std_logic_vector(3 downto 0)); > end ram; > architecture syn of ram is > type ram_type is array (4095 downto 0) of std_logic_vector (3 downto = 0); > signal RAM : ram_type; > signal read_a : std_logic_vector(11 downto 0); > begin > process (clk) > begin > if (clk'event and clk =3D '1') then > if (we =3D '1') then > RAM(conv_integer(a)) <=3D di; > end if; > read_a <=3D a; > end if; > end process; > do <=3D RAM(conv_integer(read_a)); > end syn; > Thanks! > VR.
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