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"Philippe Robert" <PhilippeR@sundance.com> schrieb im Newsbeitrag news:3bebb7ef$1@peer1.news.newnet.co.uk... > Hi there, > > I found an application note on the Xilinx website (xapp158) about decoupling > capacitors. It is explained that high frequency and mid-frequency capacitors > are required. > > For the high frequency capacitor, I will use 100nF. It says in that app to > fit 1 100nF cap per Vcc. (I have counted as Vcc pins Vccio, Vccaux and 100nF isnt that good at HIGH frequencys. Remember, the higher the capacitance, the higher the (parasitic) inductance of a cap. And since the Virtex-II are damm fast devices, I would use 10nF caps. Not 10x10nF, but lets say at least 4 10nF caps to decouple the core. Also remember, the higher the value of a decoupling cap, you can place them more far away from the VCC pins. Usually, you have a cascade of caps, 10nF, 100nF, 10uF 1000uF. > Vccint pins). I end up with 64 cpas for a XC2V1000-FG456 !! Hmm, try redestributiing the capacitance into less caps, but dont forget to use small ones (10nF or lower) for the "really" high frequencys. In microwave engineering they use sometimes even 100pF instead of 1nF because of the lower inductance. And dont forget a good ground-VCC planes. In your layer stacking, the GND-VCC planes should be close together, forming a superb high frequncy capacitor. -- MfG FalkArticle: 36476
"JianYong Niu" <cop00jn@shef.ac.uk> schrieb im Newsbeitrag news:9sgvf4$ofm$1@hermes.shef.ac.uk... > > The synthesizer I used is Synplify Pro. I assume the standard pakage > "ieee.std_logic_arith" could support the convert function > "conv_std_logic_vector()", but unfortunately synthesizer generated an error > that "No matching overload for conv_std_logic_vector". use ieee.std_logic_unsigned.all; -- MfG FalkArticle: 36477
"Michael Boehnel" <boehnel@iti.tu-graz.ac.at> schrieb im Newsbeitrag news:3BEBA17D.E01099C0@iti.tu-graz.ac.at... > Hello! > > During a timing simulation with Foundation Timing Simulator I get the > following messages: > > "undetermined input pin state" This should be clear. Some of your input signals are not defined in the simulation. E.G. if the data input of a FF isnt defined and a clock impulse arrives, what should we see at the output?? Go and assign a valid value. > "undetectable clock pulse" Hmm, never seen this, but should be similar. -- MfG FalkArticle: 36478
"Petter Gustad" <newsmailcomp1@gustad.com> schrieb im Newsbeitrag news:87668ke9a3.fsf@filestore.home.gustad.com... > > Unfortunately(?) I have no Windows and no Excel, so I need ASCII or > It would be great if partinfo (or a similar) could generate most of > the information found in the NPH file in a well documented and easily > parsed ASCII format. Hmm, I got an Xilinx CD from our FAE, which contains the pin tables in nice ASCII. They should be also on the Website. Somewhere . . . -- MfG FalkArticle: 36479
Just wanted to make sure that was not the problem :o) Thanks a lot -- Nicolas MATRINGE IPricot European Headquarters Conception electronique 10-12 Avenue de Verdun Tel +33 1 46 52 53 11 F-92250 LA GARENNE-COLOMBES - FRANCE Fax +33 1 46 52 53 01 http://www.IPricot.com/Article: 36480
"Pallek, Andrew [CAR:CN34:EXCH]" wrote: > > First invert the clock > > assign clkn = ~clk; > > then use the positive edges of each clock > > always @ (posedge clk or posedge clkn) > counter <= counter +1; I'm not a Verilog user so I don't know if this is legal Verilog or not but I'm pretty sure it will not be synthesizable. What the synthesizer will create (if it doesn't barf on it immediately) is one of the classic identity functions from Boolean logic: A or not A = 1 See other posts in this thread for other ways to do this that will work. > dfx2001 wrote: > > > who knows how to detect both edges (rising and falling edge) of clock in > > verilog? > > > > always @(posedge clk or negedge clk) > > counter <= counter + 1; //only count 1, not 2 -- Tim Hubberstey, P.Eng. . . . . . . . . . . . . . . Marmot Engineering Vancouver, BC, Canada . . . . . Hardware/Software Consulting EngineerArticle: 36481
Rick, Folks are really getting in trouble with inadequate decoupling. Howard Johnson states that as the frequency doubles, the bypassing increases by 8 times (cube of frequency). If the method used to figure out how to bypass is the "brute force" method used by Howard Johnson (ie use all 0.1 uF and just use lots of them) (and many others, including our own App 158 to some extent), the requirements get ridiculous, as you well note. In fact I have a document for our FAE's called: "Bypass, How???" that outlines the situation. Ask your FAE for it if you are interested, or email me directly. It is a text file. Lately we have decided to go to a more advanced bypassing approach, used by Intel and others on their motherboards. The first app note that will use this information will apply to Virtex II, and newer chips. I would call it the "take advantage of the series resonance" approach. This is where you match up the minimum impedance points of three of four values of capacitors with the frequency peaks in your design. This requires an a priori knowledge of where the peaks will occur, or measurement of the board after it is built with a spectrum analyzer. You then pick and choose specific cap values from specific manufacturers that are most effective at the frequencies of interest. There are simulation tools that can help in the design of a frequency selective bypassing arrangement as well. We have used this method, and shown the number of bypass caps may be reduced from ~ 100 0.1uF's on the board, to ~64 total of four separate values, with a reduction of the p-p noise on the supplies. Obviously, this requires that you know what your design is going to do in the frequency domain, which makes it impossible for us to recommend anything at all, except to follow a procedure to get the answer that is unique to your design. There are also some exciting advances in pcb laminate materials for buried bypass (high K inner layers -- Zycon(tm?r?) by Hadco for example) that provide a great deal of decoupling without all of the discrete devices. As a distributed capacitor array, you almost don't care about frequency content, until you get to the lower frequencies the material can not deal with. At 3 nF/sq inch, a 100 sq inch board is 0.3uF for all of the devices, so a number of larger value caps are probably required. I suspect the basic "general purpose do everything for everyone non-serializer/deserializer" IO's are going to hit the ceiling at 1 Gb/s (they already have), so the bypassing we are looking at will not change radically as it did when we went from Virtex E to Virtex II (with a doubling or quadrupling of all speeds). Thus the bypassing solutions now have a chance to catch up with the technology. The core logic has always been intrinsically self-bypassed for the highest frequencies (which may explain why the industry never seems to change the bypass solution for the core after 20 years!), so the lower frequencies will always remain the ones that require the external caps. These may be chosen in exactly the same way as the IO caps, based on frequency of the current to the core. Some other common mistakes are running traces to the caps (makes them useless), having a single via from the plane to the end of the pad (not as good as two vias, or via in pad), and locating the caps too far from the chip, and having a good bypass solution for the fpga, and forgetting all of the other really new high speed chips on the board that no one told you also need even better bypass solutions. As to how many 10uF, or 47 uF (whatever your favorite value is) you need, we use one 47uF per Vcco bank on our general purpose break out boards. I have seen customer boards with as many as two 47 uF per bank, and an additional 470 uF per bank. It all depends on their data patterns, and the frequency content of those data patterns. If you change from all 1's to all 0's every millisecond, then you have a real 'thump' of current at a 1KHz rate. That may require a fairly large capacitor. Austin rickman wrote: > Philippe Robert wrote: > > > > Hi there, > > > > I found an application note on the Xilinx website (xapp158) about decoupling > > capacitors. It is explained that high frequency and mid-frequency capacitors > > are required. > > > > For the high frequency capacitor, I will use 100nF. It says in that app to > > fit 1 100nF cap per Vcc. (I have counted as Vcc pins Vccio, Vccaux and > > Vccint pins). I end up with 64 cpas for a XC2V1000-FG456 !! > > Can someone tell me of my calculation is right ? > > > > For mid-frequency caps, I will use 10uF tant, but the app note does not say > > how many of them to fit. > > Does anyone know ? > > > > Thanks for your help. > > Philippe. > > I personally think that Xilinx is using a lot of overkill in their goal > of 1 cap per vcc. This is a noble goal, but rather impractical on the > packages with very fine pitch balls. When there are two or three pins > together, I would use one 100 nF cap per clump of pins. > > How many 10 uF caps to use is not really the right question. With the > bulk medium freq caps, you only need one per board. That is because they > have high impedance at high frequencies. The cap impedance is much > higher than the circuit impedance even when at the other side of the > board from the chip. So you can get by with a single bulk cap per board. > Just use one that is large enough and has a low ESR. > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAXArticle: 36482
"Dave Brown" <dbrown@novatel.ca> schrieb im Newsbeitrag news:9sh2m7$lak$1@pallas.novatel.ca... > I've checked, and PIN 74 is the configuration CCLK, but according to the > data sheet, I should be able to use this as an input after configuration. Hmm, AFAIK CCLK is NOT reusable as a user IO. -- MfG FalkArticle: 36483
Can someone suggest ideas what FPGA can be used for? -SamArticle: 36484
JianYong Niu wrote: > > Hi, All, > > In a signal assignment I have to convert an unsigned integer into > std_logic_vector. Is there any convert function that can be used to achieve > that? http://www.vhdl.org/comp.lang.vhdl/FAQ1.html#vec_conversion --Mike TreselerArticle: 36485
Hi group(s)
regarding any JPEG standard (JPEG, JPEG2000, JPEG-LS,...) what bitrates can
be obtained with current implementation technologies (DSP, FPGA, ASIC)?
Indications and estimations are also welcome.
cheers
Seb
Article: 36486
RLOCs are not legal on RAMB4's. You have to use LOC constraints, which means
that you can only place them absolutely. refer to the the libraries guide.
attribute LOC of U4:label is "RAMB4_R2C2";
khtsoi@cse.cuhk.edu.hk wrote:
> Hi,
>
> Could someone please shows how to place a block ram? The situation is:
>
> There is a RAM4_Sn_Sn components in the design as well as some other
> simple logics. All these will be a cell which will be used in a larger
> design. I can use RLOC attribute to fix the location of the CLB components.
> But the map process keep prompting error about RLOC on the block RAM.
> All I want is to place the CLB logics closer to the block RAM. I am using
> Synopsys Design Compiler to synthsis and Xilinx Alliance3.1i to implement.
> The lines of RLOC are listed below:
> --synopsys dc_script_begin
> --set_attribute J_UNIT0 RLOC "R27C10" -type string
> --set_attribute T_UNIT0 RLOC "R27C11" -type string
> --set_attribute KEY_REG RLOC "R7C2" -type string
> --synopsys dc_script_end
> I have tried to use "RAMB4_R7C2" instead, but no different.
> Please help me! Thanks in advance!
>
> ---- Brittle
>
> PS I am using Xilinx XCV1000E-HQ240-6
> PPS Is a single route (fanout=1) between 2 close CLBs (R0C0 to R0C1 through
> the fast horizontal lines) cost 0.601R(ns) is normal?
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 36487
The virtex families have keepers on the lut inputs (I believe they pull to '1' if
there is no connection), so the tie is not necessary. Your unused logic isn't
the source of your problems. Check static timing, make sure your clock is
clean. If you are using DLLs to produce 1x and either 2x or 1/2x clock, be
careful about data crossing clock domains. The edges are not necessarily aligned
well, especially if there is jitter on the input clock. Make sure the VCC is
decoupled well.
Nicolas Matringe wrote:
> Hi all
>
> I was wondering what was done with all the unused logic in Xilinx Virte-E. We
> have some strange instability problems and some engineers blem internal
> oscillations of unused logic inside the chip.
> With the 4000 families, there was an option that allowed to tie all unused
> interconnect so that it wouldn't mess but this option is no longer there.
> I'm puzzled... Any help welcome :o)
>
> Thanks in advance
> --
> Nicolas MATRINGE IPricot European Headquarters
> Conception electronique 10-12 Avenue de Verdun
> Tel +33 1 46 52 53 11 F-92250 LA GARENNE-COLOMBES - FRANCE
> Fax +33 1 46 52 53 01 http://www.IPricot.com/
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 36488People here in Albuquerque are receiving their XC2V6000CES parts but forget about the XC2V10,000 parts. I think Xilinx has given up on doing them until the next process shrink. -- Pete Dudley Arroyo Grande Systems "Austin Franklin" <austin@dark98room.com> wrote in message news:tuo027tbr1fn64@corp.supernews.com... > Hi, > > What is the largest Virtex 2 part that anyone physically has in hand? > > What promises have you received for delivery of parts? > > I have a client who wants to use the large V2 parts (6000), but we can't get > a consistent answer from the distributor WRT delivery. I got VERY badly > burnt last year with promises for V3200 delivery that never > materialized...so I am leery of making any commitments to clients about > parts that I don't have in hand. > > Any info would be appreciated. > > Thanks! > > >Article: 36489
Pete, http://www.support.xilinx.com/partinfo/ds031-1.pdf tells the whole story. A lot depends on those early adopters (the 2V6000CES you refer to). How many orders do we get for 2V10000's? There is always a price/size trade off, and customers tend to pick favorites. Interesting to note, is that only the 10000 was dropped from the list (for now, it could always come back as there is nothing to prevent it) -- the demand was too great to drop anyone else off the list, and in these times that would have been the proper business thing to do with any part that was not projected to be a real winner. Really nice to have those kinds of problems. Austin pete dudley wrote: > People here in Albuquerque are receiving their XC2V6000CES parts but forget > about the XC2V10,000 parts. I think Xilinx has given up on doing them until > the next process shrink. > > -- > Pete Dudley > > Arroyo Grande Systems > > "Austin Franklin" <austin@dark98room.com> wrote in message > news:tuo027tbr1fn64@corp.supernews.com... > > Hi, > > > > What is the largest Virtex 2 part that anyone physically has in hand? > > > > What promises have you received for delivery of parts? > > > > I have a client who wants to use the large V2 parts (6000), but we can't > get > > a consistent answer from the distributor WRT delivery. I got VERY badly > > burnt last year with promises for V3200 delivery that never > > materialized...so I am leery of making any commitments to clients about > > parts that I don't have in hand. > > > > Any info would be appreciated. > > > > Thanks! > > > > > >Article: 36490
Our bread and butter decoupling cap is .01uF (10nF) 0805 surface mount, like 1 per 4 VCC on fpga's, and we back them up with a few larger caps up to 10uF tantalums. We use terminated differential signalling for the high speed stuff if possible to cancel the ground bounce and use slew rate control on the rest. On the highest end of the switching spectrum the ground/power planes help you and my guess is that 100pF or smaller chip caps do nothing for you. Once we built some multiprocessor boards that ran about 150MHz but the caps were bad so we removed all of them. The boards ran fine without any decoupling. I'd like to try that experiment again with high speed fpga's. I like Austin's idea of tuning the caps to the operating frequency. -- Pete Dudley Arroyo Grande Systems "Philippe Robert" <PhilippeR@sundance.com> wrote in message news:3bebb7ef$1@peer1.news.newnet.co.uk... > Hi there, > > I found an application note on the Xilinx website (xapp158) about decoupling > capacitors. It is explained that high frequency and mid-frequency capacitors > are required. > > For the high frequency capacitor, I will use 100nF. It says in that app to > fit 1 100nF cap per Vcc. (I have counted as Vcc pins Vccio, Vccaux and > Vccint pins). I end up with 64 cpas for a XC2V1000-FG456 !! > Can someone tell me of my calculation is right ? > > For mid-frequency caps, I will use 10uF tant, but the app note does not say > how many of them to fit. > Does anyone know ? > > Thanks for your help. > Philippe. > > >Article: 36491
Better yet, use ieee.numeric_std.all. Unlike the std_logic libraries
(which are somewhat vendor specific), it is a standard and is supported by
all the major simulators and synthesizers. The big advantage to using
numeric_std, is that you avoid the overload conflicts you get if you use
both std_logic_signed and std_logic_unsigned.
If you do use numeric_std, then the conversion is:
std_logic_vector(to_unsigned(my_integer,number of bits));
if you wanted to convert to signed format then:
std_logic_vector(to_signed(my_integer,number of bits));
see, no ambiguities.
Falk Brunner wrote:
> "JianYong Niu" <cop00jn@shef.ac.uk> schrieb im Newsbeitrag
> news:9sgvf4$ofm$1@hermes.shef.ac.uk...
> >
> > The synthesizer I used is Synplify Pro. I assume the standard pakage
> > "ieee.std_logic_arith" could support the convert function
> > "conv_std_logic_vector()", but unfortunately synthesizer generated an
> error
> > that "No matching overload for conv_std_logic_vector".
>
> use ieee.std_logic_unsigned.all;
>
> --
> MfG
> Falk
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 36492Steven Derrien <sderrien@irisa.fr> writes: > Hello, > > I was wondering if someone had been playing with the new XPoxer tool. As > far as I understood form the documentation, getting precise power > estimations requires the design beeing simulated to produce a VCD report > file (for toggle rates). I have two question regarding this : > > 1) I guess that one has to simulate the VHDL model of the annotated > placed & routed design; and trace all primitives activity for a while to > get a good idea of the circuit behavior, however, for large design, this > is likely to be VERY time consuming, if not impossible due to the tool > stability or PC memory limits. Can someone give his opinion about this ? This method is quite common in the ASIC world. They are less time consuming than most other gate level simulations since you don't have to run for very long. The tricky part is make a good set of test vectors to cause a high toggle rate. > 2) Xilinx support says one has to use Modelsim to guarantee proper work > of the tool > Alas, we only have Synopsys VHDL simulator, which can also produce VCD > report file, but which is not 'officilially' supported by the tool. Has > anybody experienced Xpower/VSS compatibilty problems ? I haven't yet used Xpower, but I've used Cadence Verilog XL and Chronologic (sorry Synopsys) VCS for this in the past. I seem to remember that LSI logic provided their own slightly modified VCD task for this purpose. It seems odd that you can't use a different simulator since VCD is an ASCII format which is quite well documented. However if they have modified it like LSI did they might not want to go through the hassle of documenting and supporting how to link in a separate PLI library into all available simulators on all different platforms. Petter -- ________________________________________________________________________ Petter Gustad 8'h2B | (~8'h2B) - Hamlet in Verilog http://gustad.comArticle: 36493
"Seb" <someone@microsoft.com> schrieb im Newsbeitrag news:E5VG7.47306$88.5467995@zwoll1.home.nl... > Hi group(s) > > regarding any JPEG standard (JPEG, JPEG2000, JPEG-LS,...) what bitrates can > be obtained with current implementation technologies (DSP, FPGA, ASIC)? There is an app-note from Xilinx about DCT/IDCT, AFAIK the reached something around 70 MHz (= 70 Mbytes/s ??). I dont know how well the design was done and how much it can be improved (pipelining, parallel approaches ) Maximum speed is defenitely achived by using ASICs, but at the expense of high development costs/time. FPGAs are slower by a factor of maybe 2..10 ???, but development time is superb compared to ASICs. DSPs are the slowest parts I think, but also have short development times (should be similar with FPGAs ) And inbetween way would be to make a prototype using an FPGA and converting it afterwards into an ASIC (the normal way of ASIC design today ??) -- MfG FalkArticle: 36494
I double checked, and you are right, my mistake. Pin74 is an input after configuration, but not a user input, it's a dedicated pin. Thanks, Dave "Falk Brunner" <Falk.Brunner@gmx.de> wrote in message news:9shc5l$13jq2k$1@ID-84877.news.dfncis.de... > "Dave Brown" <dbrown@novatel.ca> schrieb im Newsbeitrag > news:9sh2m7$lak$1@pallas.novatel.ca... > > > I've checked, and PIN 74 is the configuration CCLK, but according to the > > data sheet, I should be able to use this as an input after configuration. > > Hmm, AFAIK CCLK is NOT reusable as a user IO. > > -- > MfG > Falk > > > >Article: 36495
Dies ist eine mehrteilige Nachricht im MIME-Format. --------------D61C1C6305B659F6F624A33F Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit yyyy is an unsigned integer and xxx is a (9 downto 0) std_logic_vector you have to write: xxxx <= conv_std_logic(yyyy,10); I used it every day.. J.O. JianYong Niu schrieb: > Hi, All, > > In a signal assignment I have to convert an unsigned integer into > std_logic_vector. Is there any convert function that can be used to achieve > that? > > The synthesizer I used is Synplify Pro. I assume the standard pakage > "ieee.std_logic_arith" could support the convert function > "conv_std_logic_vector()", but unfortunately synthesizer generated an error > that "No matching overload for conv_std_logic_vector". > > Any suggestions? > > Thanks a lot in advance!!! > > -- > Jianyong Niu > --------------------------- > Rolls-Royce UTC > ACSE, Univ of Sheffield > B20 Amy Johnson Building > Mappin St. > Sheffield S1 3JD, UK > Tel: +44 (0)114 2225236 > Fax: +44 (0)114 2225138 > Email: jyniu@acse.shef.ac.uk --------------D61C1C6305B659F6F624A33F Content-Type: text/x-vcard; charset=us-ascii; name="juergen.otterbach.vcf" Content-Transfer-Encoding: 7bit Content-Description: Visitenkarte für Juergen Otterbach Content-Disposition: attachment; filename="juergen.otterbach.vcf" begin:vcard n:;Juergen Otterbach x-mozilla-html:FALSE version:2.1 email;internet:juergen.otterbach@t-online.de x-mozilla-cpt:;65535 fn:Juergen Otterbach end:vcard --------------D61C1C6305B659F6F624A33F--Article: 36496
So, Austin (I always wanted to say that), if I tell my client that the XC2V6000 IS available, and we CAN get 10 parts by January, that would be reasonable? The parts ARE being made, there are more than a handful of engineering samples out there? I REALLY don't want to get my ass burned like I did last year on the XCV3200. Austin "Austin Lesea" <austin.lesea@xilinx.com> wrote in message news:3BEC2D87.6B4439F7@xilinx.com... > Pete, > > http://www.support.xilinx.com/partinfo/ds031-1.pdf > > tells the whole story. > > A lot depends on those early adopters (the 2V6000CES you refer to). How many > orders do we get for 2V10000's? There is always a price/size trade off, and > customers tend to pick favorites. > > Interesting to note, is that only the 10000 was dropped from the list (for now, > it could always come back as there is nothing to prevent it) -- the demand was > too great to drop anyone else off the list, and in these times that would have > been the proper business thing to do with any part that was not projected to be > a real winner. > > Really nice to have those kinds of problems. > > Austin > > pete dudley wrote: > > > People here in Albuquerque are receiving their XC2V6000CES parts but forget > > about the XC2V10,000 parts. I think Xilinx has given up on doing them until > > the next process shrink. > > > > -- > > Pete Dudley > > > > Arroyo Grande Systems > > > > "Austin Franklin" <austin@dark98room.com> wrote in message > > news:tuo027tbr1fn64@corp.supernews.com... > > > Hi, > > > > > > What is the largest Virtex 2 part that anyone physically has in hand? > > > > > > What promises have you received for delivery of parts? > > > > > > I have a client who wants to use the large V2 parts (6000), but we can't > > get > > > a consistent answer from the distributor WRT delivery. I got VERY badly > > > burnt last year with promises for V3200 delivery that never > > > materialized...so I am leery of making any commitments to clients about > > > parts that I don't have in hand. > > > > > > Any info would be appreciated. > > > > > > Thanks! > > > > > > > > > >Article: 36497
Peter, what EXACTLY do you mean by "people are receiving"??? Could you please elaborate? "pete dudley" <padudle@spinn.net> wrote in message news:tuoaa680e35ocb@corp.supernews.com... > People here in Albuquerque are receiving their XC2V6000CES parts but forget > about the XC2V10,000 parts. I think Xilinx has given up on doing them until > the next process shrink. > > -- > Pete Dudley > > Arroyo Grande Systems > > "Austin Franklin" <austin@dark98room.com> wrote in message > news:tuo027tbr1fn64@corp.supernews.com... > > Hi, > > > > What is the largest Virtex 2 part that anyone physically has in hand? > > > > What promises have you received for delivery of parts? > > > > I have a client who wants to use the large V2 parts (6000), but we can't > get > > a consistent answer from the distributor WRT delivery. I got VERY badly > > burnt last year with promises for V3200 delivery that never > > materialized...so I am leery of making any commitments to clients about > > parts that I don't have in hand. > > > > Any info would be appreciated. > > > > Thanks! > > > > > > > >Article: 36498
I have a file that was written for Philips SNAP compiler that I would like to modify. The file was written for the 18V8Z35N, which apparently is now obsolete. The ICT 18CV8 PEEL device is supposedly a direct replacement but seems I now have to learn a new compiler (i.e., ICT's WinPLACE). The quickest solution would be to obtain a copy of SNAP since I do have some 18V8Z35N's left. Anyone know where I can get a copy of SNAP? Thanks in advance, TimArticle: 36499
"Austin Lesea" <austin.lesea@...inx.com> wrote > Some other common mistakes are running traces to the caps (makes them useless), > having a single via from the plane to the end of the pad (not as good as two vias, > or via in pad), and locating the caps too far from the chip, and having a good > bypass solution for the fpga, and forgetting all of the other really new high > speed chips on the board that no one told you also need even better bypass > solutions. Also choose the lowest inductance package/via combination and max the cap within that setup. And replace 0805, etc types by 0508, etc types.
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