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Hello Tadesa, For information regarding using CAMs in Virtex devices you may want to see Xilinx Application Notes 201-204 found here: http://support.xilinx.com/apps/virtexapp.htm Note that you are also able to build CAMs using the Xilinx Core Generator. Regards, Kamal Tadesa wrote: > I see what CAM is, but if you are using xilinx-Virtex family fpga (I > read the documentation) how can i use it? do i have to build the CAM? > If it is already there how can i use it? (in VHDL) > > Many Thanks > -Tadesa > > Peter Alfke <peter.alfke@xilinx.com> wrote in message news:<3BF419D0.1156DD19@xilinx.com>... > > CAM stands for Content Addressable Memory. > > When you read from it, you specify the stored data, and the CAM outputs the > > location where such data is stored. ( that's opposite from a normal RAM) > > CAMs are much more complicated to design and build than "ordinary" RAMs, > > especially if you include the "don't care" option for the data that you present, > > and also when you have to deal with the fact that the requested data may be > > stored in more than one location. > > Peter Alfke > > ======================== > > Tadesa wrote: > > > > > Where can i find what CAM is and how to implement it? Can I write to it? > > > > > > regards, > > > TadesaArticle: 36701
Peter Alfke wrote: > Strange world. > First you sign with initials only, plus a fake e-mail address, > then you receive several friendly and constructive answers. > But then you find it necessary to tell us it's not homework... > Makes one wonder... > Peter Alfke > ======================== > VR wrote: > > > VR <fastpwm@isfastpwmpossible.com> wrote: > > > Hey all. > > > > > I'm dealing with an interesting problem -- something I'm sure a lot of > > > other people have come across... > > > > > The issue is how to get a high speed (>=200kHz) 10-bit PWM signal. That is > > > 200kHz is the frequency of the PWM waveform, and 10-bit resolution is what > > > I am seeking for the duty cycle control. > > > > BTW, for those who are wondering, THIS IS NOT A HOMEWORK ASSIGNMENT. > > > > This is actually for a personal project and for the record, all questions > > I post in this newsgroup & other groups are related to one or more > > personal projects, not school work. > > > > Thanks, > > VR. One does wonder... However, not all of us who use an _edu_ email address are students or even professors. Some of us are doing research associated designs. Some of us are even doing designs targeted to production systems. (For example, myself.) However, some of the postings here are _obvious_ classroom assignments. Theron HicksArticle: 36702
Dear all, I need your suggestion. In my design, I need several clock rate that is : 6 Mhz, 9 Mhz, 12 Mhz, 18 Mhz, 24 Mhz, 36 MHz, 48 Mhz, and 54 Mhz. I think in most of the cases the people using one clock source only (XTAL) instead of multiple XTAL. If I am using one clock source, how to make it support several clock rate ? btw: I heard, I need to use Xilinx DLL, is that useful for this cases ? Thanks. Rgds, BasukiArticle: 36703
Hi, I need OrCAD footprint for Xilinx XCR3128 VQ100. Does anybody knows how to abtain it? Thanks ZdravkoArticle: 36704
Hello to everyone A simple question Are Spartan2 dedicated configuration pins (CCLK, /PROGRAM, TDI, TDO,...) 5 volt tolerant? From documentation I guess that non dedicated configuration pins are LVTTL and so 5 V tolerant if VCCo is 3.3 V, but I am unsure about the dedicated ones. Thank you indeed Javier Diaz SpainArticle: 36708
"Maf" <maf.gg@wanadoo.fr> wrote in message news:<9t010h$1gu$1@wanadoo.fr>... > Check out www.datacube.com for their MaxRevolution product. > > > David Eadie <david.eadie@cs.tcd.ie> a écrit dans le message : > a0ce2abd.0111140648.1f92ae6b@posting.google.com... > > Hi, > > > > I'm interested in exploring the image processing potential of using > > FPGAs within high-speed video cameras. Initially I would like to get > > an FPGA prototyping/development/evaluation kit working within the PC > > itself. > > > > Features I would like: > > > > -PCI-card-based, to allow easy I/O to/from PC memory. > > -on-card memory to store image data and results. At least 8 MB, > > preferably more. > > -Virtex II device (2 million gates, or more). > > -Some FPGA I/O pins accessible through a header/connector on the > > PCI-card. > > > > Does anyone know if such a card, or similar, exists? > > Are there any other important features I should look for? > > > > Thanks > > > > David Eadie, > > Computer Vision and Robotics Research Group, > > Dept. of Computer Science, > > Trinity College Dublin. Datacube looks like an interesting solution to video, never heard of them before. Also right across the Irish sea in Glasgow is Nallatech, they have a range of high end boards with many PCI fpga video apps off the shelf. Nots so far away is Alpha Data with similar products in Edinburgh. Also Sundance in Chesham. There are a couple of other companies in UK, Germany as well. Search google for "pci fpga boards". Also try http://www.optimagic.com/ & XIlinx 3rd party PCI board lists. http://www.xilinx.com/xlnx/xil_prodcat_product.jsp?title=protoboards_protoboards_page Regards John JaksonArticle: 36709
Tadesa, The Altera APEX 20KE/C, APEX II, and Mercury devices' memory blocks support CAM implementations natively. You'll get very high performance (relative to implementing the CAMs with regular memory and using general-purpose logic for control) by using these. Here's a pointer to some notes on CAMs in Altera devices: http://www.altera.com/literature/an/an119.pdf http://www.altera.com/products/devices/apex/apx-cam_ram_comp.html http://www.altera.com/products/devices/apex/apx-cam.html http://www.altera.com/products/devices/apex/apx-cam_comp2.html The Altera MegaWizard will automatically cascade or link the memory blocks in parallel to implement deeper/wider CAMs. There are even more information on CAMs on the Altera web site. Just do a search on "CAM" at http://www.altera.com Good luck. -Pete- Tadesa <tadesa@hotmail.com> wrote in message news:8cc84053.0111160625.57960139@posting.google.com... > I see what CAM is, but if you are using xilinx-Virtex family fpga (I > read the documentation) how can i use it? do i have to build the CAM? > If it is already there how can i use it? (in VHDL) > > Many Thanks > -Tadesa > > > Peter Alfke <peter.alfke@xilinx.com> wrote in message news:<3BF419D0.1156DD19@xilinx.com>... > > CAM stands for Content Addressable Memory. > > When you read from it, you specify the stored data, and the CAM outputs the > > location where such data is stored. ( that's opposite from a normal RAM) > > CAMs are much more complicated to design and build than "ordinary" RAMs, > > especially if you include the "don't care" option for the data that you present, > > and also when you have to deal with the fact that the requested data may be > > stored in more than one location. > > Peter Alfke > > ======================== > > Tadesa wrote: > > > > > Where can i find what CAM is and how to implement it? Can I write to it? > > > > > > regards, > > > TadesaArticle: 36710
Hello Javier, >From Answer Record 2098 found here: http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=2098 we know that all banks are in the LVTTL standard until they are configured otherwise. Therefore, I believe that the configuration pins are 5V tolerant. Regards, Kamal Javi Diaz wrote: > Hello to everyone > > A simple question > > Are Spartan2 dedicated configuration pins (CCLK, /PROGRAM, TDI, TDO,...) 5 > volt tolerant? > > From documentation I guess that non dedicated configuration pins are LVTTL > and so 5 V tolerant if VCCo is 3.3 V, but I am unsure about the dedicated > ones. > > Thank you indeed > > Javier Diaz > SpainArticle: 36711
This is cool! which CAM solution can i use for ip packet filter with the following tuple (srcaddr, destaddr, srcport, destport, protocol) which the CAM will have 10 entries each of which will have 104-bits. what do i need to do to implement this filter? -Thanks On Fri, 16 Nov 2001, Peter Ormsby wrote: > Tadesa, > > The Altera APEX 20KE/C, APEX II, and Mercury devices' memory blocks support > CAM implementations natively. You'll get very high performance (relative to > implementing the CAMs with regular memory and using general-purpose logic > for control) by using these. Here's a pointer to some notes on CAMs in > Altera devices: > > http://www.altera.com/literature/an/an119.pdf > http://www.altera.com/products/devices/apex/apx-cam_ram_comp.html > http://www.altera.com/products/devices/apex/apx-cam.html > http://www.altera.com/products/devices/apex/apx-cam_comp2.html > > The Altera MegaWizard will automatically cascade or link the memory blocks > in parallel to implement deeper/wider CAMs. There are even more information > on CAMs on the Altera web site. Just do a search on "CAM" at > http://www.altera.com > > Good luck. > > -Pete- > > > Tadesa <tadesa@hotmail.com> wrote in message > news:8cc84053.0111160625.57960139@posting.google.com... > > I see what CAM is, but if you are using xilinx-Virtex family fpga (I > > read the documentation) how can i use it? do i have to build the CAM? > > If it is already there how can i use it? (in VHDL) > > > > Many Thanks > > -Tadesa > > > > > > Peter Alfke <peter.alfke@xilinx.com> wrote in message > news:<3BF419D0.1156DD19@xilinx.com>... > > > CAM stands for Content Addressable Memory. > > > When you read from it, you specify the stored data, and the CAM outputs > the > > > location where such data is stored. ( that's opposite from a normal RAM) > > > CAMs are much more complicated to design and build than "ordinary" RAMs, > > > especially if you include the "don't care" option for the data that you > present, > > > and also when you have to deal with the fact that the requested data may > be > > > stored in more than one location. > > > Peter Alfke > > > ======================== > > > Tadesa wrote: > > > > > > > Where can i find what CAM is and how to implement it? Can I write to > it? > > > > > > > > regards, > > > > Tadesa > > > >Article: 36712
Yes, Spartan-II ( and Virtex ) dedicated config pins are also 5-V tolerant. Peter Alfke ========================= Javi Diaz wrote: > Hello to everyone > > A simple question > > Are Spartan2 dedicated configuration pins (CCLK, /PROGRAM, TDI, TDO,...) 5 > volt tolerant? > > From documentation I guess that non dedicated configuration pins are LVTTL > and so 5 V tolerant if VCCo is 3.3 V, but I am unsure about the dedicated > ones. > > Thank you indeed > > Javier Diaz > SpainArticle: 36713
Peter Alfke <@xilinx> wrote: > Strange world. > First you sign with initials only, plus a fake e-mail address, > then you receive several friendly and constructive answers. > But then you find it necessary to tell us it's not homework... > Makes one wonder... > Peter Alfke First, many thanks to all who responded! Secondly, I really appreciate the helpful answers, but I did get an e-mail from someone saying I should do my homework on my own. I'm not sure at what point my news server synchs up, but when I posted my message(not a homework assignment), I didn't see any responses. I did of course tell this particular person it was not a homework assignment, but that didn't seem to go anywhere. Sorry if I offended any of the kind and "un-assuming" posters ;). Also, Peter, if I may ask, how is the fine phase shifting done in the Virtex-IIs? Is it done purely digitally, or does it make use of some particular VLSI tricks (if you can comment without breaching patents, etc)? I only "ruled Virtex-II out" because this particular gentlemen said he was not using such a powerful (and expensive) part. Thanks! VR.Article: 36715
for removing some warnings,i run unsetenv LANG on Solaris.but som EDA softwares cann't run. why?how do i?Article: 36716
VR wrote: > Also, Peter, if I may ask, how is the fine phase shifting done in the > Virtex-IIs? Is it done purely digitally, or does it make use of some > particular VLSI tricks (if you can comment without breaching patents, etc)? > > I only "ruled Virtex-II out" because this particular gentlemen said he was not > using such a powerful (and expensive) part. > Virtex-II40, the smallest member, is not really expensive... The phase shifting is done by pulsing the DCM module inside the chip. It's all described in the data sheet, and the Virtex-II Handbook, and is on the web. It is digital to the extend that you ask it to step in integer increments, clock period divided by 256. It may look analog, since the DCM executes by calculating the appropriate number of tape settings, but it is digital anyhow, since the DCM updates the tap setting continuously, to assure the right digital fraction of a clock period. No secrets, it's all documented. PA ( but MY e-mail address is correct, albeit at home )Article: 36717
James C. Schwalbe <schwalbe@compuserve.com> wrote: > I have heard that Xilinx is having difficulty yielding on the 6000 parts and > will not be able to deliver on any parts larger than this. They do not have > the redundancy built into the dye that Altera has therefore making it more > difficult to get reasonable yields on the larger parts. So Altera says in a marketing bulletin, anyway. Hamish -- Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>Article: 36718
Falk Brunner <Falk.Brunner@gmx.de> wrote: > So just use a 80 MHz clock and generate a clock enable with 3/4 duty cycle. > This gives you 60 Mhz too. It gives you 60 MHz throughput but your logic still needs to run at 80. Hamish -- Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>Article: 36719
#BASUKI ENDAH PRIYANTO# wrote: > > Dear all, > > I need your suggestion. > In my design, I need several clock rate that is : 6 Mhz, 9 Mhz, 12 Mhz, > 18 Mhz, 24 Mhz, 36 MHz, 48 Mhz, and 54 Mhz. > > I think in most of the cases the people using one clock source only > (XTAL) instead of multiple XTAL. > > If I am using one clock source, how to make it support several clock > rate ? if the frequency has a nice relationship as yours have, you could just input the highest frequencies and divide it i.e. 48Mhz,48MHz/2,48MHz/4,48MHz/8 = 48,24,12,6 MHz 54MHz,54MHz/1.5,54MHz/3,54MHz/6 = 54,36,18,9 MHz With as many clocks as you need you'd probably run out of dedicated clock nets so you could use clock enables to get the same result without having to distribute as many clocks on the chip > > btw: I heard, I need to use Xilinx DLL, is that useful for this cases ? The DLL can correct the duty cycle, so it's a nice 50-50 for the uneven dividers, it can also be used to divide a clock or multiply it by two So I guess you could take a 54MHz use two DLLs to get it to 216MHz and then divide that to get all you other frequencies > > Thanks. > > Rgds, > > Basuki -Lasse -- Lasse Langwadt Christensen, -- A Dane in Phoenix, ArizonaArticle: 36720
Well, challenge us. Give us a big order and watch us deliver.... Always treat with a hand-full of salt what one competitor says about the inner workings of the other :-) Peter Alfke ============================= hamish@cloud.net.au wrote: > James C. Schwalbe <schwalbe@compuserve.com> wrote: > > I have heard that Xilinx is having difficulty yielding on the 6000 parts and > > will not be able to deliver on any parts larger than this. They do not have > > the redundancy built into the dye that Altera has therefore making it more > > difficult to get reasonable yields on the larger parts. > > So Altera says in a marketing bulletin, anyway. > > Hamish > -- > Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>Article: 36721
Is 80 MHz a challenge these days? That's 12.5 ns. Seems like an eternity for modern chips. We are presently haggling over shaving an extra 100 picoseconds off the input set-up time... Peter Alfke hamish@cloud.net.au wrote: > Falk Brunner <Falk.Brunner@gmx.de> wrote: > > So just use a 80 MHz clock and generate a clock enable with 3/4 duty cycle. > > This gives you 60 Mhz too. > > It gives you 60 MHz throughput but your logic still needs to run at 80. > > Hamish > -- > Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>Article: 36722
Lasse Langwadt Christensen wrote: > The DLL can correct the duty cycle, so it's a nice 50-50 for the uneven > dividers, it can also be used to divide a clock or multiply it by two > > So I guess you could take a 54MHz use two DLLs to get it to 216MHz and > then divide that to get all you other frequencies > > That statment is true for Virtex and Spartan-II. In the newer Virtex-II the DLL can do more, it can also, on its frequency synthesis output, provide any frequency that is M/D time the input frequency. M is the multiplier and can be any integer up to 32, D is the divider and can also be any integer up to 32. So you can multiply and divide simultaneously. You can drive the DLL with 90 MHz, pick M=31 and D=9, and get 310 MHz out. ( just to illustrate that the output is valid although the multiplication itself seems to create an excessively high frequency) And the Virtex-II Digital Clock Manager also has fine-grain phase adjustment. Clever circuit! Peter AlfkeArticle: 36723
How can you view the gates and latches that are inferred from vhdl code. I am trying to find a way to see a gate level schematic of my vhdl modules. Thanks for any help you can give.Article: 36724
Hey there, My environment is the following: Windows NT (SP 6) Xilinx Foundation ISE 4.1i (ELITE) - Service Pack 2 ModelSIM SE 5.5e I've set up a VHDL library in the Xilinx environment called 'uog', which consists of a few VHDL entities and functions. Some of the VHDL entities in the 'uog' library are dependent on each other, so I made sure to add the VHDL entity sources without dependencies first. Unfortunately, when I try to use the XST sythesizer on a top-level design that uses the 'uog' library, I get the following error: ERROR:HDL Parsers:3014 - G:/knichols/41i_projects/fp_library/uog_fp_arith.vhd Line 48. Library unit uog_fp_exp not available in library uog. It turns out that 'uog_fp_exp' is one of the entities in my 'uog' library, but XST synthesizer can't find it for some reason. I have a feeling that XST isn't synthesizing the contents of my library correctly. Ironically I've been able to synthesize this same top-level design and library using FPGA Express synthesizer in the 4.1i environment, and XST synthesizer in the 3.1i environment (so I know this problem is not my fault). When I check out the Xilinx Answers Database, it turns out that Record Number 12895 is the most similar problem found. Anybody else encounter this problem? Any suggestions?? Thanks. Kris Nichols
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