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"Peter Alfke" <palfke@earthlink.net> schrieb im Newsbeitrag news:3BF69776.A9E6B9A0@earthlink.net... > Is 80 MHz a challenge these days? ;-)) Dont know,. > That's 12.5 ns. Seems like an eternity for modern chips. Almost. But also think about, not everyone is pushing >800 Mbit/s through the inputs to build a terabit IP switch. There are also plenty of guys around (including me) that eat humble pie (Thanks to dict.leo.org for the phrase ;-) So why wasting time to make your circuit run @80 MHz when you have a easy way (Virtex-II DCM) to generate a "real" 60 Mhz clock. I wouldnt. > We are presently haggling over shaving an extra 100 picoseconds off the input > set-up time... And this is very appreciated. -- MfG FalkArticle: 36726
Is Xilinx Student edition F1.5 compatible with Webpack 4.1 ? I'm trying to update an older design using Student Edition F1.5 and am getting strange results. I've installed Webpack 4.1 since I last used the student edition. I tried my original design in F1.5 and it's now telling me it's 4x (1800CLB's) too big for the part an XC4010XL It used to fit no problem. If I try it in Webpack 4.1 the result is only 400 LUTs (= about 200 CLBs). Thanks RobArticle: 36727
It may like Spartan-II PCI develop board(DS-PCI32S-KIT2) or something like this. remail me : tt889@163.netArticle: 36728
Dear colleagues, I am trying to use XILINX .bit-file as an input for a self-made FPGA configuration load program. The question is: - What is contained in the header of the .bit-file, before actual configuration data? - How to skip the header? Yes, I know, that I can use ASCII .rbt file as an input for my program (and actually do that). But .rbt files are very large, compared to .bit files. It is very unconvenient to distribute several megabytes of firmware codes ... Of course, I can invent my own binary format, derived from .rbt-files. But why to do that, if there is a standard .bit-file? Thanks, Alex SherstukArticle: 36729
Alex Sherstuk wrote: > > Dear colleagues, > > I am trying to use XILINX .bit-file as an input for a self-made FPGA > configuration load program. > > The question is: > - What is contained in the header of the .bit-file, before actual > configuration data? > - How to skip the header? > > Yes, I know, that I can use ASCII .rbt file as an input for my program (and > actually do that). > But .rbt files are very large, compared to .bit files. It is very > unconvenient to distribute several megabytes of firmware codes ... > > Of course, I can invent my own binary format, derived from .rbt-files. But > why to do that, if there is a standard .bit-file? > > Thanks, > Alex Sherstuk looking at the rbt and the bit files it looks like the firste 72 bytes of the .bit file is header the rest of it looks the same as the .rbt file -Lasse -- Lasse Langwadt Christensen, -- A Dane in Phoenix, ArizonaArticle: 36730
The answer is in the FAQ:
http://www.fpga-faq.com/FAQ_Pages/0026_Tell_me_about_bit_files.htm
Philip
On Sat, 17 Nov 2001 22:43:01 GMT, "Alex Sherstuk" <sherstuk@iname.com> wrote:
>Dear colleagues,
>
> I am trying to use XILINX .bit-file as an input for a self-made FPGA
>configuration load program.
>
>The question is:
>- What is contained in the header of the .bit-file, before actual
>configuration data?
>- How to skip the header?
>
>Yes, I know, that I can use ASCII .rbt file as an input for my program (and
>actually do that).
>But .rbt files are very large, compared to .bit files. It is very
>unconvenient to distribute several megabytes of firmware codes ...
>
>Of course, I can invent my own binary format, derived from .rbt-files. But
>why to do that, if there is a standard .bit-file?
>
>Thanks,
> Alex Sherstuk
>
>
Philip Freidin
Fliptronics
Article: 36731I have written a program on Linux to download the bit file to XCV100E through the Xilinx Parallel Cabel III. You may be intreset in that. http://www.cse.cuhk.edu.hk/~khtsoi/project/Xilinux/index.htm May people in this news group help me to build that. But it's now using raw inb(), outb() and must be setuid as root. If you (or anyone) can modify it to have nicer security, please let me know. Thanks! ---- BrittleArticle: 36732
You could use an array of arrays. Multi-dimensional types are not supported
by some synthesis tools (eg. Synopsys DC), but an array of arrays usually
is.
So you would get:
type t_Array is array(0 to something) of integer;
type t_ArrayOfArray is array(0 to 9) of t_Array;
output_sig <= myArray(cntr2)(cntr);
BTW, while I think it should be ok, I am not 100% sure that the last line
is syntactically correct. If not, you can do:
v_ActArray : t_Array;
v_ActArray := myArray(cntr2);
output_sig <= v_ActArray(cntr);
To answer the original question: I am a bit surprised that the case
statement gives worse results than the IF-ELSE case. I don't really see who
the IF-ELSE case can have less fanout than the CASE case.
And the IF-ELSE case will likely have a higher number of levels of logic.
Tom
Sul Weh wrote:
> Yes, but if I have *10* roms, each each 10 integers in them then it would
> be if (cntr2 = 0) then
> output_sig <= array_of_int0(cntr)
>
> so I have 10 arrays of 10 integers
> "Russell Shaw" <rjshaw@iprimus.com.au> wrote in message
> news:3BF06C0F.32B632D2@iprimus.com.au...
>>
>>
>> Sul Weh wrote:
>> >
>> > What is the advantages/disadvantages of using a CASE statement or an if
>> > statement?
>> > For example, if I have 10 arrays of 10 integers (array0, array1,...)
>> > and
> I
>> > want to sequentially output each array I can either use a CASE statment
> or a
>> > 10 separate IF statements.
>> > e.g. if (counter = 0) then ... end if
>> > if (counter = 1) then ... end if
>> >
>> > What I have seen is the clk is slower in a CASE statement than an IF
>> > statement because the counter has a huge fanout.
>> >
>> > any advice or comments?
>>
>> I'd do it this way (less code): Declare an array of 10 items with 10-bit
>> integers, and initialize them. The synthesizer should see this
>> hard-coding,
>> and make a small rom. Now all you need to do is have a counter index the
>> pointer of this array: output_sig<=array_of_int(cntr);
Article: 36733Hi! We recently updated WebPACK 3.3 to the latest 4.1 version. The nice thing is that now, in our Win95 machines, WebPACK fails to start. The pthread shared library needs some threading functions not present in the Win95 Kernel32 library (TryEnterCriticalSection, for example -- it seems the libpthread.dll library that Xilinx is using is not very robust). Has anybody solved this problem? We can't switch to other Windoze versions in these machines because we have other software/hardware that depends on it... Best wishes.Article: 36734
Pablo Bleyer Kocik wrote: > > Hi! > > We recently updated WebPACK 3.3 to the latest 4.1 version. The nice > thing is that now, in our Win95 machines, WebPACK fails to start. The > pthread shared library needs some threading functions not present in > the Win95 Kernel32 library (TryEnterCriticalSection, for example -- it > seems the libpthread.dll library that Xilinx is using is not very > robust). > > Has anybody solved this problem? We can't switch to other Windoze > versions in these machines because we have other software/hardware > that depends on it... It says in the release notes that 4.1 will not work under Win95. Win95 and POSIX-compliance (pthreads) are after all rareley mentioned in the same sentence, unless there's a NOT! in there as well :-) ATB, Simon.Article: 36735
Hi all : I am trying to instantiate a fft16 core (created using coregen) in a bigger project. It starts off ok and then gives the following warnings : <===================================================> WARNING:NgdBuild:454 - logical net 'FFT16/done' has no load WARNING:NgdBuild:454 - logical net 'FFT16/ovflo' has no load .... <===================================================> 120 of them !!!! Then it carries on to mapping which it does with no errors/warnings. Then it goes on to routing and then gives the following warnings ... <===================================================> WARNING:Route:49 - The signal "FFT16/dfly/xmul/pi_add/COUT16_NET_O" has no loads so was not routed. WARNING:Route:49 - The signal "FFT16/dfly_i_2comp/TWOS_COMP_SUB/COUT_NET_16" has no loads so was not routed. <===================================================> Quite surprisingly - it then says .. <===================================================> All signals are completely routed. Total REAL time to PAR completion: 43 secs Total CPU time to PAR completion: 42 secs Placement: Completed - No errors found. Routing: Completed - No errors found. PAR done. <===================================================> Then it goes on to timing .. goes pretty smoothly until when it says <===================================================> WARNING:Anno:197 - NGDAnno found 8 physical component(s) for which 100 percent back-annotation is not possible. Simulation models for these components will be constructed from the NCD. Rerun NGDAnno with the -report option for additional details, including any net and instance names which are lost in this process. <===================================================> and then aborts with a fatal error : FATAL_ERROR:NetListWriters:basnewrite.c:709:1.5.6.1 - No block bus info found for bus d(3:0). Process will terminate. To resolve this error, please consult the Answers Database and other online resources at http://support.xilinx.com <===================================================> And ofcourse support.xilinx.com didnt have the answer :(( and that is why i am writing here. If someone could help me out , it would be great ! I am using Foundation tools 3.11. I have included the vff16.edn to the project. I am instantiating the core in my vhd file the exact same way, the coregen manual tells me to .. I dont quite understand why this error comes up. Would really appreciate it, if you could also copy replies to cgopalak@csee.usf.edu Thanks in advance. ... --MouliArticle: 36736
"Pablo Bleyer Kocik" <pbleyer@embedded.cl> wrote in message news:d26ba1a8.0111172254.75e620d5@posting.google.com... > Hi! > > We recently updated WebPACK 3.3 to the latest 4.1 version. The nice > thing is that now, in our Win95 machines, WebPACK fails to start. The > pthread shared library needs some threading functions not present in > the Win95 Kernel32 library (TryEnterCriticalSection, for example -- it > seems the libpthread.dll library that Xilinx is using is not very > robust). > > Has anybody solved this problem? We can't switch to other Windoze > versions in these machines because we have other software/hardware > that depends on it... You should be able to upgrade to Win98 without any problems, I'd have thought. The new Webpack work fine with that, of course. Leon -- Leon Heller, G1HSM leon_heller@hotmail.con http://www.geocities.com/leon_heller Low-cost Altera Flex design kit: http://www.leonheller.comArticle: 36737
I thought I had a full installation of the latest 3.x tools...and brought up the FPGA Editor...but it doesn't seem to allow me to select any of the Virtex 2 parts... Does anyone know if this is supposed to be available in FPGA Editor with the 3.x tools? If not, then is it available with the 4.x tools?Article: 36738
Austin Lesea wrote: > More to consider than just bypassing.... > > http://www.xilinx.com/xlnx/xil_prodcat_product.jsp?title=si_pcbcheck > > Austin > Nice checklist although the "simulation" rqeuirements presuppose access to a SPICE engine. Is there a freeware/opensource/public-domain implemetation ? Only one quibble on TI (= TextIntegrity): Are you really recommending milliFarad (e.g. 4.7mF) caps ? Perhaps its a misprint for 4.7MF :-).Article: 36739
Falk Brunner wrote: > "Peter Alfke" <palfke@earthlink.net> schrieb im Newsbeitrag > news:3BF69776.A9E6B9A0@earthlink.net... > > Is 80 MHz a challenge these days? > > > > We are presently haggling over shaving an extra 100 picoseconds off the > input > > set-up time... > > And this is very appreciated. > > -- > MfG > Falk Even more appreciated would be some extra -ve hold time. Sometime soon I've got to deal with a chip that has a 0.5nsec -ve min Tco. This is unloaded so the 10pF of trace + input capacitance should get me within the Virtex-E's = -0.4 BUT .... PALs & GALs had fairly large -ve hold requirements that were quoted in the early data sheets but then the manufacturers stopped giving this info & reverted to type in only saying 0. AFAIK Xilinx are the only ones willing to stick their necks out these days - at least for FPGA's IOB FFs.Article: 36740
Austin Franklin wrote: > > Hey there, > > It seems I have another challange to overcome in attempting 'timing' > > simulations in ModelSIM. > > Kris, > > Why are you doing timing simulations in the first place? > > Austin Post P&R simulation is the only way to find NGDBUILD/MAP/PAR bugs [BITGEN bugs = you are basically stuffed]. Particularly in the early days of MX.Y there were a lot of issues with timing contraints. Even as recently as 2.1i you couldn't separate the 2 parts of a BlockRAM if they were on different clocks - lead to some interesting problems. Found a new 2.1iSP6 MAP bug just the other day when re-building an old release with the same toolset as the original build. Needed post PAR simulation to find it.Article: 36741
I loaded 4, and the XC2V3000 FF1152 is supported in FPGA Editor... Still curious about if any version of 3 supports the XC2V3000 in FPGA Editor. "Austin Franklin" <austin@da22rkroom.com> wrote in message news:tvfsrtqmn2hk52@corp.supernews.com... > I thought I had a full installation of the latest 3.x tools...and brought up > the FPGA Editor...but it doesn't seem to allow me to select any of the > Virtex 2 parts... Does anyone know if this is supposed to be available in > FPGA Editor with the 3.x tools? If not, then is it available with the 4.x > tools? > > >Article: 36742
Ok, I solved the problem -- at least the technical aspects of it. I replaced the libpthread.dll library that comes with Xilinx WebPACK (origin unknown) with GNU's pthread-win32 library (pthreadGCE.dll - GCC + exceptions compiled natively with Mingw). And voilą, I have been using 4.1 smoothly since yesterday -- however I have not programmed any devices yet. The pthread-win32 library (http://sources.redhat.com/pthreads-win32/) is released under the LGPL. I don't know which *legal* consequences these may have under Xilinx WebPACK ISE legal terms. However... should I suggest that Xilinx uses this well supported & tested library instead of the one it is using now? Ideas? Suggestions? Flames? Software guys from Xilinx here? (or worse -- Xilinx lawyers ;^) Cheers!Article: 36743
Hi. I've managed to read some sort of IDCODE out of my XC9572 pc44 cpld, and I wonder if someone using webpack or similar software could tell me a valid 32-bit IDCODE from such a chip, so I have something to compare with. The reason I'm asking this is that I dont have microsoft windows installed. /Daniel Nilsson M.Sc.EE studentArticle: 36744
Based on xc9572_pc44.bsd, it is
attribute IDCODE_REGISTER of xc9572_pc44 : entity is
"XXXX" & -- version
"1001010100000100" & -- part number
"00001001001" & -- manufacturer's id
"1"; -- required by standard
Hope this helps,
Jim
"Daniel Nilsson" <e9danne@etek.chalmers.se> wrote in message
news:3BF87410.438BF1F7@etek.chalmers.se...
> Hi.
> I've managed to read some sort of IDCODE out of my XC9572 pc44 cpld, and
> I wonder if someone using webpack or similar software could tell me a
> valid 32-bit IDCODE from such a chip, so I have something to compare
> with.
> The reason I'm asking this is that I dont have microsoft windows
> installed.
>
> /Daniel Nilsson M.Sc.EE student
Article: 36745Now I'm studying Modular Design using Amplify of Synplicity. However, now I encountered some problems. I have thought them for about three days. But, till now, I cannot fix them yet. Therefore, I query them on Internet. Could you kindly help me on these problems? 1. I study this design flow following the tutorial guide of Amplify. However, after I completed the design budget in Design leader project, I was informed to "Use the top-level .edf and .ncf files to run Initial Design Budgeting in the place-and-route tool". At this point, I was confused. There are all abstract sub-modules in the EDIF netlist, which were treated by Amplify as black box. How could ngdbuild expand the design? 2. When I try to run the .edf and .ncf files in the place-and-route tool (I use the Design Compiler in ISE 4.1, Service Pack II), the tool reported the error as follows: The entry: E:\..\.edf contains spaces. Currently spaces are not supported. But the .edf file in this format (I mean the file contain spaces) is outputed by Amplify. If such a format could not be supported by the P&R tool, why does Amplify output such a file? 3. In Amplify, how can I expand a bus when I would like to do some constraints by pesudo port region. In the example design in Amplify, a bus has been expanded into bits. The bus port in bit is draged&droped from the RTL view to the pesudo port region. But, I cannot find a way to expand the bus in my design. How can I make this? 4. After I complete the design of team leader, I need distribute the source code, SCOPE files and physical constraint file to the team members to begin the implementation of their respective P&R regions. At this point, I wonder in what way should I distribute these files, by sending a copy of my whole project to each member or in other way? Judging from the specification of the guide, I regard I should forward a copy of my whole project to every member, right? If it's right, every member just cares the design that is allcated to himself or herself and doesn't care others although his project file includes other P&R region information. Is it right? ThanksArticle: 36746
I'm working on a design using either two XC2V1000 (FG456 package) or XC2V3000 (FG676 package). As the board is part of a prototype system we wanted to start with the small devices and if necessary up grade to the 3000s later. First we discovered that roughly half of the LVDS channels can not be used because the differential pairs on one package do not correspond to the pairs on the other package (what an inconvenience). Running a place and route yielded that of the pins I thought would match, there are still pairs with inversed polarity between the packages...which was confirmed by a look at the data sheet. :-( Namely: 3000 1000 M22->N K20->P M21->P K19->N N21->P L19->N N22->N L20->P L21->P J19->N L22->N J20->P I remember having seen a nice Xilinx brochure with a transparent print of one package which fits perfectly over the drawing of the next bigger package...how misleading. If anybody knows of any other hidden obstacles I might struggle over, any comments will be appreciated very much. Thanks JonasArticle: 36747
It seems that you have connected combinational logic to the clock input of a flop (you have implemented a not recommended "gated clock" structure which can cause problems because of skew on clock signals). Synplify provides you with that warning message because it assumes that any signal which is connected to the clock input of a flop is a "real"clock signal. Synplify is not able to calculate the frequency of that gated clock signal and, therefore, assumes that the frequency of the incoming clock signal is also applied to all the flopswhich are connected to the gated clock. To anwer your questions: Yes, that warning message is important because it provides you with information on potential problems with your design. You can resolve it by either resolving the gated clock structure of your design or applying a clock constraint on the flops driven by the gated clockArticle: 36748
Hi everyone I use a sinplify pro to synthesis, and the target device is APEX20K400E, but the sinplify pro do not allow me to specify the max fanout, and after the synthesis, some net(not clock) have fanout as large as 500. how to deal with this? thank youArticle: 36749
The design is being targetted to VirtexE family. For the gate level simulation, I require VHDL netlist. If I generate that through dc_shell, the INIT generic for the LUT's are not being associated with the LUT's. So it gives warning during the compilation. So the netlist has to be given to FC2 to have these INIT parameters. Now those parameters are associated with the LUT's. But now the warning is given for the RAM's..RAMB4_S*.. The xnf files for these can not be opened for analyze. can u suggest some solution for this?
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