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In article <3BD9A861.A8845FDC@gmx.de>,
Falk Brunner <Falk.Brunner@gmx.de> writes:
|> Right, but that was not quite the point here. It was about driving a DAC
|> with a jittery clock, which cases FM and so distortions. In the HIGH-end
|> HIFI voodoo scene, this is heavyly discussed ;-)
|> I dont know how serious this problem is, and I also didnt make any
|> investigation about the theoretical aspects.
|> Anyone got some basic numbers?
There were good numbers in a paper in an older Crystal data book, it covered
delta-sigma converters and their sensitivity to jitter (Harris Jitter AES
paper, should be in the AES journal of July 1990).
In the end it showed, that a sinusodial jitter of 230ps can be audible (above the
quantisation noise floor) for a 16bit ADC, independent of the sampling technique.
My personal experience with a weird running 74HC4046 is similar. A bad loop
filter caused a jitter of about 15ns, the noise was easily audible, I would
estimate a SNR of 60db for a 16bit DAC :-/
--
Georg Acher, acher@in.tum.de
http://www.in.tum.de/~acher/
"Oh no, not again !" The bowl of petunias
Article: 36051
How long is *really long* ? As I pointed out, 1 CLB worth of LFSRs gets you a
period of over 2000 years with a 100 MHz clock. The single LFSR actually gets more
efficient as you increase its length, since the termnal count only grows at log2(N)
and the LFSR grows at a little less than 1/17 that rate. Cascading 2 identical
LFSRs gets you the same effect as doubling the length of a single LFSR, so it is
more expensive. Cascading different lenght LFSRs, however may give you better
granularity in your selection of period.
John H. mentioned preloading the LFSR. That gives a precise control over the
period, but as he points out, it involves some Galois field math to come up with
the preload value. You also incur a fair amount of extra logic to effect the
preload, and as many luts as there are in your shift register to hold your reload
value. I think if you were clever in the design you could use the terminal count
detect counter to time the reload, and you could also store the reload value in a
recirculating SRL16 to avoid having to address a CLB ROM. That at least would keep
the extra logic associated with the reload to a minimum. The hard part would be
the GF math. As long as the time interval was not outrageously long, a probably
faster way to come up with the reload value would be to brute force a reversed
sequence LFSR through the desired number of steps (less the reload time) starting
at zero and then reading the value.
glen herrmannsfeldt wrote:
> John_H <johnhandwork@mail.com> writes:
>
> >Very nicely commented. The terminal count detector is sometimes overlooked
> >until implementation.
>
> >There's way to provide *any* delay that would add a little overhead, but not a
> >huge amount. Use CLB ROMs to establish an initial value in the shift register
> >that corresponds to the shift register value at your precise time delay before
> >terminal count. There's a little extra work to figure out the preload value
> >but it's very doable. The math isn't 5 minutes of work (unless you're an
> >expert on this stuff) but one can produce what the nth shift register value is
> >after any shift register value in the sequence mathematically to avoid waiting
> >over 924 years to find what the right value is to preload the 2^63-1 counter
> >for precisely 2000 years delay.
>
> If you want a really really long count you could do this recursively.
> Use an LFSR based counter to count the successive zeroes of the first
> LFSR counter.
>
> -- glen
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 36052Answering your last question first, there are several methods to implement your filter. Altera has a FIR Compiler which can generate coefficients, show the effects of coefficient quantization, estimate resource usage (for a PLD) across several architectures, provide high performance throughput (pushbutton 200 MHz performance), generate simulation models in Verilog and VHDL, etc. This is all available at : http://www.altera.com/products/ip/altera/m-alt-fir-compiler.html One of the key aspects in your design is that you have an I and a Q channel. This can best be implemented in a multi-channel interpolating filter using the FIR Compiler. Hope this helps, Tony "Antonio D'Ottavio" <etantonio@jumpy.it> wrote in message news:<9qu103$s82$3@serv1.albacom.net>... > Good Morning, > I'm arranging a QPSK bandpass modulator having f_clk = 165MHz and > f_IF = f_clk/4 = 41,25MHz > this means that for the I use : > cosine = 1 , 0 , -1 , 0 , ... > sine = 0 , -1 , 0 , 1 , ... > these arrive to the multipliers at a rate of 165MHz, on the other inputs of > the multipliers there are the output > of two SRRC filters interpolating by 6 a symbol rate of 27,5MSpS to 165MHz. > Until now this work fine, now there is a change in the project, it must be > possible to serve also a Symbol rate > of 13,75MSpS this seems possible using the zeroes in the sine and cosine so > the idea is to use : > cosine = 1 , -1 , 1 , -1 , ... > sine = -1 , 1 , -1 , 1 , ... > that always arrive at the multipliers at a rate of 165MHz while the SRRC > always interpolate 6. > My question is : > 1) Do you think that this is correct especially regarding the fact that for > example the 1 arrive to the multiplier > of the cosine in the same istant that the -1 arrive to the multiplier of > the sine, in fact I think that sine and > cosine form an orthogonal base but not in this latest form, what do you > think about ??? > > 2) If you think that this is correct do you think that I must use 2 filters > following the 2 multipliers to take in > account that an interpolator is formed by an upsampler and a filter, in > this case how you suggest me to > design this filter ?? > > Thanks for your interest .. > > Antonio D'OttavioArticle: 36053
Ray Andraka wrote: > John H. mentioned preloading the LFSR. That gives a precise control over the > period, but as he points out, it involves some Galois field math to come up with > the preload value. Just inserting my 2bits [hahaha funny pun] of crypto knowledge into the discussion. A LFSR is basically made upon a field GF(2)[x]/p(x) where p(x) is an irreducible polynomial in GF(2)[x]. The stepping is identical to multiplying by the polynomial "x" in the field. So if you want to figure out what preload value for N delays just step back N steps.... i.e if you want the polynomial "1" to represent the end value just do z(x) = x g(x) = z(x)^(-N+1) = x^(-N) preload g(x) and step it N times... so say N=2 then g(x)*x = x^-2*x = x^-1, x^-2*x = x^-1, x^-1 * x = x^0 = 1 You can find g(x) in a L-bit LFSR by doing x^(2^L - N) mod p(x) Where you use the multiply and square algorithm to find it. Hope thats of help to anyone :-) TomArticle: 36054
Tom St Denis wrote: > z(x) = x > g(x) = z(x)^(-N+1) = x^(-N) That's suppose to be g(x) = z(x)^(-N) = x^(-N) > preload g(x) and step it N times... so say N=2 then > > g(x)*x = x^-2*x = x^-1, x^-2*x = x^-1, x^-1 * x = x^0 = 1 > > You can find g(x) in a L-bit LFSR by doing > > x^(2^L - N) mod p(x) That should be x^(2^L - (1 + N)) mod p(x) since there are only 2^L - 1 elements. TomArticle: 36055
"Ulf Samuelsson" <ulf@atmel.REMOVE.com> writes: > Some people think that a serial protocol which needs a copyright notice > from the legal vendor to work would be hard to copy since it violates > some original authors rights. Sega tried such an approach with the later versions of their Genesis game console. It looked for a Sega copyright notice at a fixed location in game cartridges, without which it would not execute code from the cartridge. In Sega vs. Accolade, it was determined that this practice constituded unlawful restraint of trade, and that Accolade was not enjoined from putting such a copyright notice in their cartridges. I've heard rumors to the effect that X10 claims to have a copyright on their power line signalling, and sics their lawyers on anyone making X10-compatible equipment without a license. This seems to me to be equivalent to my claiming to have a copyright on the nonsense words glorbenplatz and zedtubligpan, and developing a protocol that communicates using those words (in ASCII) to encode zeros and ones, then suing anyone who develops an interoperable program. Anyhow, I don't have any firsthand knowledge of such actions on the part of X10, so there may be no truth to it.Article: 36056
Knowing the Altera architecture and it's limitations, these numbers sounded a bit high. Looking
at the link you provided confirms it. While the linked page indicates "over 200 MHz
performance", checking the chart at the bottom shows that there is only one case out of 8 or so
examples that breaks 200 MHz...... that is the bit rate, not the sample rate. These examples
are for a 97 tap filter with 14 bit coefs and 8 bit inputs. That fastest filter example is 3100
LEs. A 97 tap non-symmetric serial filter with 14 bit coefficients and 8 bit data in a Xilinx
Virtex will occupy approximately 475 slices (950 LEs), and if floorplanned can be run at a bit
rate limited by the SRL16 minimum pulse width, which for a VirtexE-7 is about 235 MHzor around
255 Mhz in a -8 part. (we have done a number of filters this way) If you make it a symmetric
filter, the size reduces to about 275 slices, with no speed penalty. Additionally, the input
width in the Xilinx implementation can be expanded to as many as 17 bits with no change in the
LUT count because the delays are implemented in SRL16s. The Virtex architecture also makes it
possible to reprogam the filter coefficients without reprogramming the device for a modest cost
of about 75 additional logic slices. VirtexII speeds are considerably higher, although I do not
know the numbers off hand yet.
Tony San wrote:
> Altera's FIR compiler automatically generates serial, and multi-bit
> serial fir filters which run at 240 MHz on 20KC silicon and over
> 300MHz on Altera's Mercury devices.
>
> Here is the link :
> http://www.altera.com/products/ip/altera/m-alt-fir-compiler.html
>
> Tony
>
> renaux <renaux.jacky@wanadoo.fr> wrote in message news:<2001929-165035-699438@foorum.com>...
> > just posting a message sent to kuldeep
> >
> >
> > Hi
> > Personnally I think this architecture is a very easy one for
> > building files
> > updating coefficients ( during debug and later updating )
> > as not routing is needed just reload a new set
> >
> > serial arithmetic
> > for your case I undestand 12bits * 16Mhz is = 192 Mhz
> > why not to build up 2 RAMs one for odd bits , the second for
> > even bits and add the 2 results : means running 2 sets in parrallel
> > at 6*16 => 96Mhz this is not a big deal any more . The 2 tables will
> > have the same content , just a matter on how you feed the addresses
> > In case you want to run slower .... use 4 RAMS and running 1/4 the speed
> > and add the results ....... you might go down to have 1 RAM per bit running
> > at 16 Mhz each but you will need 12 RAMS this is not what obviously I would
> > recommand as every today ASIC can run 100Mhz systemm clock
> > take care
> > just be be sure you run least significant bit first, you must add succesivelly
> > the partial product (from the ram) and add it to the accumulated product
> > divided
> > by 2 (right shift ) but on the last cycle you must substract as the MSB is
> > addressing the ram ( 2's complement )
> > as you right shift the accumulated result you can the feed a shift register in
> > order to end up with a full scale result
> >
> > coefficients (5 in this exemple )
> >
> > non symetrical
> > you need 5 shift registers ( which can also be a RAM)
> > reg5 <= (reg4(0) & reg5(11 downto 1));
> > reg4 <= (reg3(0) & reg4(11 downto 1));
> > reg3 <= (reg2(0) & reg3(11 downto 1));
> > reg2 <= (reg1(0) & reg2(11 downto 1));
> > reg1 <= (data_in & reg1(11 downto 1));
> > address_ram <= (reg5(0) & reg4(0) & reg3(0) & reg2(0) & reg1(0) );
> >
> > symetrical
> >
> > usually ( coeff 1 = coeff 5 , coeff2 = coeff 4)
> > you still need 5 shift registers and group the coefficients by
> > coefficients value
> >
> >
> > reg5 <= (reg4(0) & reg5(11 downto 1));
> > reg4 <= (reg3(0) & reg4(11 downto 1));
> > reg3 <= (reg2(0) & reg3(11 downto 1));
> > reg2 <= (reg1(0) & reg2(11 downto 1));
> > reg1 <= (data_in & reg1(11 downto 1));
> >
> > add1 <= reg5(0) + reg1(0) + carry1;
> > add2 <= reg4(0) + reg2(0) + carry2;
> >
> > -- this is a carry save type adder
> > -- carry1 and carry2 are saved from the previous cycle try to
> > -- configure add1 and add2 as 2 bits lsb is the add result
> > -- and msb is carry
> >
> > address_ram <= ( reg3(0) & add2 & add1 );
> >
> > -- which requires half bits addresses (in case odd coefficients )
> >
> > but you must take in account the 13nd carry ( add1 and add2 ) then
> > requiring 1 more cycle ( you should consider 14 bits and then running at
> > 14/2 * 16 Mhz
> >
> > 14 bits is fine as if you run one more cycle and pad zero as 13 and 14 bits into
> > the shift registers , you will not have to reset carries at each new cycles
> >
> > RAMS
> >
> > as you have 65 coefficients you'll need 32 bits addresses RAM which is very
> > large
> > even in ASIC , you must split into smaller blocs ( if you only have 1K* Y RAM ,
> > then
> > you'll need 4 of them )
> > How about Y ( RAM output bus ) it depends on number of coefficients inputs and
> >
> > coefficients size ( if you have 11 bits coefficients , and 10 bits addresses
> > the largest value is when all addresses are '1' in theory the output is
> > 10+11=21 bits
> > BUT ..... is it the largest partial products ? not necessary it depends the
> > values
> > some might be negative ... try to calculate the largest value ( excel is fine
> > for )
> > and then optimize the RAM size sometime it is not necessary as it is design
> > dependant
> >
> > Speed
> >
> > at 100Mhz you must take care of initialisations and the accumulator must be
> > cleared
> > every cycle . There is 3 options (at least for me )
> > 1- add one more cycle to clear the accumulator
> > 2- add one more cycle and add the ram content + zero ( this is not an
> > accumulation
> > cycle )
> > 3- using one more register . The last cycle instead to store the adder output
> > you store it to a register which keep the cycle result while you clear
> > the
> > accumulator
> >
> > Squeleton
> >
> > reg5 <= (reg4(0) & reg5(11 downto 1));
> > reg4 <= (reg3(0) & reg4(11 downto 1));
> > reg3 <= (reg2(0) & reg3(11 downto 1));
> > reg2 <= (reg1(0) & reg2(11 downto 1));
> > reg1 <= (data_in & reg1(11 downto 1));
> >
> > add1 <= reg5(0) + reg1(0) + carry1;
> > add2 <= reg4(0) + reg2(0) + carry2;
> >
> > address_ram <= ( reg3(0) & add2 & add1 );
> >
> > from 1 to last_cycle_clock-1
> > adder_out <= accumulator/2 + ram_out;
> > accumulator <= adder_out;
> > last_cycle_clock
> > adder_out <= accumulator/2 - ram_out;
> > result <= adder_out;
> > accumulator <= '0';
> >
> >
> > I hope its help do not hesitate to contact me
> >
> > regards
> >
> >
> >
> > -----Message d'origine-----
> > De : Kuldeep [mailto:kkdeep@lycos.com]
> > Envoyé : jeudi 27 septembre 2001 15:52
> > À : renaux.jacky@wanadoo.fr
> > Objet : RE: fir filter
> >
> >
> > Hi jacky ,
> > Thanx for reply. This seems to be good architecture as i can tradeoff
> > throughput with hardware . Fully serial approach will not work for me as my
> > input data is coming at 16Mhz, 12-bit wide. That means i need clock of 192MHz
> > (16x12) which i can't afford .correct me ..so i will go for some mix of serial -
> > parllel approach.
> > i have two doubts:
> > quoting a line from ur reply :
> > 1."you better add coefficient before feeding the partial products table"
> > Here do u mean adding inputs (for which coeffcient happen to be same) before
> > feeding the partial product table? Plese elaborate further how can i take
> > advantage of symmetrical coeffcients.
> > 2. i have odd number (65) coeffcients. Each LUT take 4 coeff. so where will the
> > last coeff go?? should i use 1 LUT for this single coeff.
> >
> > thanx and regds
> > Kuldeep
> >
> > renaux <renaux.jacky@wanadoo.fr> wrote in message news:<2001925-184146-
> > 543341@foorum.com>...
> > > Hi
> > >
> > > I would suggest you read an excellent paper on distributed arithmetic
> > > where part of the calculation is done before running while the remaining
> > > is done during the run
> > >
> > > go to http://www.andraka.com/ , DSP with FPGA and distributed arith
> > >
> > > this is intended to fpga , but using a case statement it can be targetted to
> > > any technology . in addittion , using a ram as table would simplify the
> > > FIR filter implementation : a tap per add line , and output bus is as wide as
> > > sum of coefficients values ( if 16 12 bits coefficients => 4+12 bits bus )
> > > do not miss the fact which is coefficients are symetrical you better add
> > > coefficient before feeding the partial products table )
> > >
> > > do not hesitate to drop me a mail in case it is not clear enough
> > >
> > > regards , jacky
> > >
> > > ------
> > > User of http://www.foorum.com/. The best tools for usenet searching.
> >
> >
> >
> >
> > Make a difference, help support the relief efforts in the U.S.
> > http://clubs.lycos.com/live/events/september11.asp
> >
> > ------
> > User of http://www.foorum.com/. The best tools for usenet searching.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 36057Confusion of Macro! In Macro construction of FPGA Editor, there are two terminologies. 1. Pre-placed Component: A component that is placed in the macro library file 2. Pre-routed Net: A net that is completely routed in the file. And, Xilinx recommends allowing PAR to route the macro with the design, which means that Pre-routed Net Macro is discouraged in practice. However, the above two concepts are so confused to me. If a designer cann't fix the placement and routing when he or she make a macro cell with FPGA Editor, how does he or she fix the logic funtion of the design? In my view, we often make a macro cell when there are some very strict timing constraints. In the macro, we can fix the placement of components and the delay of the net connect these components. If we can make a macro without pre-place and pre-routing process, why we need such a macro. Is there anybody can clarify my puzzle? Thank you! Please address your email to slash11@163.netArticle: 36058
Hi, I'm trying to initialize a small group of ROMs (ROM32x1) in my design. So far I have managed to initialize a RAM block (RAMB4_S8_S8) for both synthesis and simulation. When I searched the Xilinx database I got answer #10073 that answers exactly what I want. Problem is, it does not work on FPGA Express 3.5 . Answer #10073 does say "tested on FPGA express 3.4". The annoying thing is that the mechanism suggested is identical to the one for the RAMB4_S8_S8 block which works fine. It works fine in simulation, but when it is synthesized, I get the following warning message: "This message indicates that either the referenced design cannot not be found, or the referenced design is found but cannot be properly linked to the cell due to mismatched pins on the cell and the referenced design. The the later case, there are more detailed messages preceding this message to indicate the exact reasons for the linking failure. " No messages precede this one. If I go ahead, NGbuild then complaints that ROM32x1 has not been initialized. The code I use is based on the one suggested on the Xilinx site(see below). I have Foundation 3.3i +SP8. Neither ROM16x1 nor ROM32x1 work -- VHDL Example for ROM library IEEE; use IEEE.std_logic_1164.all; entity DROM is port ( ROM0_IN, ROM1_IN, ROM2_IN, ROM3_IN: in STD_LOGIC; ROM_OUT: out STD_LOGIC ); end DROM; architecture XILINX of DROM is -- Distributed ROM component ROM16X1 port (A0 : in std_ulogic; A1 : in std_ulogic; A2 : in std_ulogic; A3 : in std_ulogic; O : out std_ulogic ); end component; attribute INIT: string; attribute INIT of ROM_EXAMPLE: label is "10A7"; begin ROM_EXAMPLE : ROM16X1 port map( O => ROM_OUT, A0 => ROM0_IN, A1 => ROM1_IN, A2 => ROM2_IN, A3 => ROM3_IN ); end XILINX; Any help appreciated. A.S.Article: 36061
To all: thoses are very good questions. Could you post your answer on the newsgroup, so we could all benefit? Thanks. -- > * How many DSP on FPGA designs you have done > * Why you chose to use FPGAs instead of standard DSP chips > * What tools are you using and how well they are working > * How current tools could be improvedArticle: 36062
I would like to simulate digital video or image stills to an FPGA design using Altera MAX+plus II software. My plan is to convert a graphics file like a bitmap into a *.vec vector waveform file. Can anyone tell me if this has been done before? And does anyone know a simple graphics file format that will be easy to extract the image data? I need it in 8-bit RGB format. (24-bits total). Thanks.Article: 36063
I've used a program called Scion Image to convert various image formats to ascii
text files that can be easily read by VHDL
DaveG wrote:
> I would like to simulate digital video or image stills to an FPGA design
> using Altera MAX+plus II software. My plan is to convert a graphics file
> like a bitmap into a *.vec vector waveform file. Can anyone tell me if this
> has been done before? And does anyone know a simple graphics file format
> that will be easy to extract the image data? I need it in 8-bit RGB format.
> (24-bits total). Thanks.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 36064
OK
-- wrote:
> To all:
> thoses are very good questions.
> Could you post your answer on the newsgroup, so we could all benefit?
> Thanks.
> --
>
> > * How many DSP on FPGA designs you have done
Lots. More than I care to count up right now.
>
> > * Why you chose to use FPGAs instead of standard DSP chips
This is our market segment. FPGAs typically outperform DSPs by factors
of around 100:1 in the applications we have been doing
>
> > * What tools are you using and how well they are working
Matlab for system modeling, Aldec for VHDL capture, Synplicity for
synthesis. They work OK.
>
> > * How current tools could be improved
Better support for dataflow designs throughout the tool flow, especially
in place and route. better integration of Hardware DSP into Matlab.
>
>
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 36065Hi, Currently, I am looking for Xilinx Virtex 2 or Virtex E evaluation board. Basically, ,my requirement is the FPGA which has at least 3 Million System gate. Anybody can help me ? Thanks ! BasukiArticle: 36066
Neil Franklin <neil@franklin.ch.remove> writes: >gah@ugcs.caltech.edu (glen herrmannsfeldt) writes: >> >> It might be, as one reply says, it is like RISC, where the time came >> and, after looking for a while in disbelief, everyone finally jumped on. >Everyone except Intel, who makes 90% of all PC-sized processors :-). who also makes the i860. (snip) >> I used to hear stories that the PDP-10 was asynchronous, but I have >> now found that other PDP-10 stories were false, so that one may be also. >The earlier PDP-10s CPU models (166, KA-10) were hardwired async, they >then switched to hardwired sync (KI-10) and later to microcoded sync >(KL-10 and KS-10). Thanks. It was a KA-10 that I used to use. >Data from: >http://www.inwap.com/pdp10/models.txt (snip) -- glenArticle: 36067
Thanks to everyone who replied to the posting I made.
Here are more details I will like to throw in.
Looking at Xilinx IP Evaluation license, does this evaluation license
stop someone from cloning Xilinx's IP cores?
http://www.xilinx.com/ipcenter/ipevaluation/ipevaluation_license.htm
************************* (C) Xilinx *******************************
Xilinx IP Evaluation License Agreement
Xilinx Evaluation IP is owned and controlled by Xilinx and
must be used solely for design, simulation, implementation and
creation of design files limited to Xilinx devices or technologies.
Use with non-Xilinx devices or technologies is expressly prohibited
and immediately terminates your license.
Xilinx products are not intended for use in life support appliances,
devices, or systems.
Use in such applications are expressly prohibited
********************************************************************
Let's say that someone sign up for their IP evaluation, and use
Xilinx's technical documents like user's guide, design guide, and
reference design contained inside the evaluation zip file from Xilinx
to derive that person's original, but compatible implementation.
After someone is done cloning the IP core, release it to the public
(of course, without the files that came with the IP evaluation,
because I don't have the right to redistribute it) as a synthesizable
vendor neutral HDL implementation with constraint files for multiple
vendors' devices.
Since that work was derived from the original evaluation version of
the IP core, will that person have the right to implement it with any
vendor's device?
Again, the method used here design that person's original
implementation compatible with the original will be:
1) Studying the bus protocol listed in the user guide, design guide,
or reference design
2) Entering waveform stimulus into the evaluation IP core, and analyze
how it behaves
3) Attach a user module that tests the evaluation IP core, and analyze
how it behaves
4) Study third party literature (IEEE, trade groups, or books related
that can be purchased at a book store)
5) Will not reverse engineer the netlist or any encrypted design
information (i.e., convert the netlist to gate-level symbols. Sort of
like disassembler software VCommunications used to have (maybe they
still have) that spit out .ASM file from .EXE file which can be
assembled again).
The thing I guess I am trying to describe here is that is it possible
to clone Xilinx's IP core or any other IP core in a way Cyrix cloned
Intel's x86 implementation?
What I have to say about Cyrix is that Cyrix didn't copy Intel's
microcode unlike AMD's 386 and 486 implementation.
Cyrix analyzed Intel's implementation through testing, and created
their own implementation.
I am aware that since K5, AMD started its own implementation of x86
processor.
Xilinx also has a separate LogiCORE license, but from what I
see here, it looks like it doesn't take effect until someone purchases
an IP core from Xilinx.
http://www.xilinx.com/ipcenter/doc/xilinx_click_core_project_license.pdf
Here is the legal stuff about Xilinx's website.
http://www.xilinx.com/legal.htm#tm
I will like to know how people think about Altera's licensing
agreement.
This URL is about Altera's OpenCore licensing agreement.
http://www.altera.com/products/ip/megacore-lic.html?function=viterbi-compiler
This part is I think is the most important in the case I am talking
about.
************************* (C) Altera *******************************
2. MegaCore License Restrictions:
YOU MAY NOT USE THE MEGACORE LOGIC FUNCTION EXCEPT AS EXPRESSLY
PROVIDED FOR IN THIS AGREEMENT OR SUBLICENSE OR TRANSFER THE MEGACORE
LOGIC FUNCTION OR RIGHTS WITH RESPECT THERETO.
YOU MAY NOT DECOMPILE, DISASSEMBLE, OR OTHERWISE REVERSE ENGINEER THE
MEGACORE LOGIC FUNCTION OR ATTEMPT TO ACCESS OR DERIVE THE SOURCE CODE
OF THE MEGACORE LOGIC FUNCTION OR ANY ALGORITHMS, CONCEPTS,
TECHNIQUES, METHODS OR PROCESSES EMBODIED THEREIN; PROVIDED, HOWEVER,
THAT IF YOU ARE LOCATED IN A MEMBER NATION OF THE EUROPEAN UNION OR
OTHER NATION THAT PERMITS LIMITED REVERSE ENGINEERING NOTWITHSTANDING
A CONTRACTUAL PROHIBITION TO THE CONTRARY, YOU MAY PERFORM LIMITED
REVERSE ENGINEERING, BUT ONLY AFTER GIVING NOTICE TO ALTERA AND ONLY
TO THE EXTENT PERMITTED BY THE APPLICABLE LAW IMPLEMENTING THE EU
SOFTWARE DIRECTIVE OR OTHER APPLICABLE LAW NOTWITHSTANDING A
CONTRACTUAL PROHIBITION TO THE CONTRARY.
********************************************************************
Does this part of the license ban someone from designing their own
original implementation of Altera's IP core through the analysis
methods I have mentioned above when I was talking about Xilinx's IP
cores?
This URL mentions the how to handle information obtained from
Altera's website.
http://www.altera.com/literature/gn/legal.pdf
(5) under the fourth paragraph states, "(5) You may not use the
materials in any way that may be adverse to Altera's interests."
Is such statement legally enforceable if someone uses the information
obtained from Altera's website, and used that information to clone
their devices or IP cores?
Will cloning Altera's IP core be called "use the materials in any way
that may be adverse to Altera's interests."?
Another legal stuff is also written in a file generated by
Altera's MegaWizard (I have never used that feature).
************************* (C) Altera *******************************
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
// ************************************************************
// Copyright (C) 1991-2001 Altera Corporation
// Any megafunction design, and related net list (encrypted or
decrypted),
// support information, device programming or simulation file, and any
other
// associated documentation or information provided by Altera or a
partner
// under Altera's Megafunction Partnership Program may be used only to
// program PLD devices (but not masked PLD devices) from Altera. Any
other
// use of such megafunction design, net list, support information,
device
// programming or simulation file, or any other related documentation
or
// information is prohibited for any other purpose, including, but not
// limited to modification, reverse engineering, de-compiling, or use
with
// any other silicon devices, unless such use is explicitly licensed
under
// a separate agreement with Altera or a megafunction partner. Title
to
// the intellectual property, including patents, copyrights,
trademarks,
// trade secrets, or maskworks, embodied in any such megafunction
design,
// net list, support information, device programming or simulation
file, or
// any other related documentation or information provided by Altera
or a
// megafunction partner, remains with Altera, the megafunction
partner, or
// their respective licensors. No other licenses, including any
licenses
// needed under any third party's intellectual property, are provided
herein.
********************************************************************
Does this mean that if I use a MegaCore Function through OpenCore, I
cannot design my original implementation through analysis methods I
already mentioned? (I guess I already asked a similar question like
this.)
Here is the legal stuff about Altera's website.
http://www.altera.com/common/legal.html
They seem to repeat the same, "may be adverse to Altera's interests"
argument again.
Is such a thing enforceable?
It sounds like the Synplicity/Leonardo License Agreement discussion
that was going on at comp.arch.fpga a little while ago about the
issue of banning the licensee from disclosing benchmark information
about their products.
After saying all of this, what is the definition of reverse
engineering, and are the methods I have mentioned called reverse
engineering, and will it violate Xilinx's or Altera's evaluation
licensing agreements?
I know this is a pretty long posting, but I will appreciate if you can
let me know how you think about this topic.
Regards,
Kevin Brace (don't respond to me directly, respond within the
newsgroup)
kevinbraceusenet@hotmail.com (Kevin Brace) wrote in message news:<cc7b0b5f.0110261344.42cd95bf@posting.google.com>...
> I will like to know what happens when someone designs a compatible IP
> core of someone else's IP core?
> The design techniques used for designing such a compatible IP core
> will not be analysing a netlist, but designing a compatible IP through
> publically available information like a third party specification
> (IEEE or a trade group specification), the vendor's (the vendor who
> made the original IP core you are trying to clone) manual, or other
> files or data that can be obtained publically (say, without hacking
> into the vendor's computer) through vendor's website.
> The reason I am asking this question is because various PLD companies
> have IP cores available for trial with fairly detailed technical
> information made available upon signing up for their trial program
> (which is free).
> Isn't it possible that someone might try to clone their IP cores?
> If so, does the PLD vendors have a way to stop it?
> It looks like already a company called AMI Semiconductor
> cloned Xilinx's LogiCORE PCI IP core according to this EE Times
> article.
>
> http://www.eetimes.com/story/OEG20010907S0103
>
>
> Here is the actual product page for AMI Semiconductor's Xilinx
> compatible PCI IP core.
>
> http://www.amis.com/trans/xilinx-pci.cfm
>
>
> Despite the fact the AMI Semiconductor cloned Xilinx's PCI IP core, it
> looks like Xilinx hasn't taken any legal action against AMI
> Semiconductor.
> Does that mean that the IP core vendor has no way from stopping
> someone from cloning their IP cores?
>
>
>
> Regards,
>
>
>
> Kevin Brace (don't respond to me directly, respond within the
> newsgroup)
Article: 36068Ray Andraka <ray@andraka.com> writes: >How long is *really long* ? As I pointed out, 1 CLB worth of LFSRs >gets you a period of over 2000 years with a 100 MHz clock. >The single LFSR actually gets more efficient as you increase its >length, since the termnal count only grows at log2(N) and the LFSR >grows at a little less than 1/17 that rate. Cascading 2 identical >LFSRs gets you the same effect as doubling the length of a single >LFSR, so it is more expensive. Cascading different lenght LFSRs, >however may give you better granularity in your selection of period. Well, I said really really long. I don't know Virtex so well, so I don't know which mode you use to do this. Does it include the feedback taps in that one CLB? Can you select any feedback taps that you want? So you have a 64 bit LFSR to count your 2000 years, and need a 6 bit counter to count the 64 successive zeroes. The suggestion was to use a LFSR counter to count those zeroes, though, yes, there might be better ways to count to 64. As you mention, two LFSR's with different periods could be run in parallel and then detect the simultaneous zero of the two. With only one more CLB you could get a 128 bit counter, and count for 3e22 years. How many CLB's does it take to make a complete LFSR counter? (Inlcuding the preset ROM and load logic for arbitrary counts?) -- glenArticle: 36069
kevinbraceusenet@hotmail.com (Kevin Brace) writes: >Thanks to everyone who replied to the posting I made. >Here are more details I will like to throw in. >Looking at Xilinx IP Evaluation license, does this evaluation license >stop someone from cloning Xilinx's IP cores? (snip, including snip of the Xilinx license.) I would presume that the usual rules regarding derived works would apply. Not being a lawyer, I won't try to say anything about those laws. -- glenArticle: 36070
A small LFSR can be done in one slice (2 LUTs, or half a CLB). The key
is using the SRL16, which lets you put a shift register of 1 to 16 clocks
into the LUT. You can't get at intermediate registers in Virtex, but you
can get at 1 variable tap plus the 16th with VirtexII. You also get a
register after the LUT, so you can get 17 taps of delay in a single
lut/ff pair. In one CLB, you get up to 68 taps, and by careful
arrangement you can usually get an arrangement that gets you access to
the taps you need for feedback. If you want to be able to preload the
LFSR, you'd have to have a parallel recirculated shift register of the
same length, plus a bit of logic and a bit counter. As I mentioned
before, you could use your zero detect as a bit counter for loading too,
so that comes pretty much free. The extra control is a couple of LUTs.
You can use the SRL16's as a shift register to count up to 17 clocks, but
not if you need to be able to reset the count.
glen herrmannsfeldt wrote:
> Ray Andraka <ray@andraka.com> writes:
>
> >How long is *really long* ? As I pointed out, 1 CLB worth of LFSRs
> >gets you a period of over 2000 years with a 100 MHz clock.
> >The single LFSR actually gets more efficient as you increase its
> >length, since the termnal count only grows at log2(N) and the LFSR
> >grows at a little less than 1/17 that rate. Cascading 2 identical
> >LFSRs gets you the same effect as doubling the length of a single
> >LFSR, so it is more expensive. Cascading different lenght LFSRs,
> >however may give you better granularity in your selection of period.
>
> Well, I said really really long.
>
> I don't know Virtex so well, so I don't know which mode you use
> to do this. Does it include the feedback taps in that one CLB?
> Can you select any feedback taps that you want?
>
> So you have a 64 bit LFSR to count your 2000 years, and need
> a 6 bit counter to count the 64 successive zeroes. The suggestion
> was to use a LFSR counter to count those zeroes, though, yes,
> there might be better ways to count to 64.
>
> As you mention, two LFSR's with different periods could be run
> in parallel and then detect the simultaneous zero of the two.
> With only one more CLB you could get a 128 bit counter, and count
> for 3e22 years.
>
> How many CLB's does it take to make a complete LFSR counter?
> (Inlcuding the preset ROM and load logic for arbitrary counts?)
>
> -- glen
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 36071hello, I am looking for a real-application FIR of more than 14 taps, symmetric or no it does not matter. This is typically for comparaison purposes . The target is FPGA thanksArticle: 36072
Hi Folks,
I have Jbits 2.0.1 installed on my machine. I have the constraint that I have to use this version and not the latest.
I want to use BoardScope.
But when I run java BoardScope I get the error message saying,
C:\JBits2.0.1\com\xilinx\BoardScope\Virtex>java BoardScope
Exception in thread "main" java.lang.NoClassDefFoundError: BoardScope (wrong nam
e: com/xilinx/BoardScope/Virtex/BoardScope)
at java.lang.ClassLoader.defineClass0(Native Method)
at java.lang.ClassLoader.defineClass(Unknown Source)
at java.security.SecureClassLoader.defineClass(Unknown Source)
at java.net.URLClassLoader.defineClass(Unknown Source)
at java.net.URLClassLoader.access$100(Unknown Source)
at java.net.URLClassLoader$1.run(Unknown Source)
at java.security.AccessController.doPrivileged(Native Method)
at java.net.URLClassLoader.findClass(Unknown Source)
at java.lang.ClassLoader.loadClass(Unknown Source)
at sun.misc.Launcher$AppClassLoader.loadClass(Unknown Source)
at java.lang.ClassLoader.loadClass(Unknown Source)
at java.lang.ClassLoader.loadClassInternal(Unknown Source)
My ClassPath looks like this:
SET CLASSPATH=C:\JDK1.3\LIB;C:\jdk1.3\jre\lib;c:\jdk1.3;c:\JBits2.0.1;c:\JBits2.0.1\demo;c:\JBits2.0.1\com;C:\JBits2.0.1\com\xilinx\BoardScope\Virtex
SET PATH=C:\MATLAB\BIN;C:\FABIUS\BIN;C:\FABIUS\BIN;C:\PERL\BIN;C:\WINDOWS;C:\WINDOWS\COMMAND;C:\SILOS3;C:\JDK1.3\BIN;c:\JBits2.0.1;C:\JBits2.0.1\com\xilinx\BoardScope\Virtex
BITTRA~1 CLA 6,283 06-05-01 10:45p BitTrace.class
BOARDS~1 CLA 24,385 06-05-01 10:45p BoardScope.class
BOARDS~2 CLA 1,603 06-05-01 10:45p BoardScope$MenuListener.class
BOARDS~3 CLA 3,111 06-05-01 10:45p BoardScope$CommandLineListener.class
BOARDS~4 CLA 922 06-05-01 10:45p BoardScope$WindowListener.class
BOARDS~5 CLA 2,888 06-05-01 10:45p BoardScope$ButtonListener.class
BOARDS~6 CLA 2,052 06-05-01 10:45p BoardScope$StateListener.class
BOARDS~7 CLA 1,646 06-05-01 10:45p BoardScope$WaveformListener.class
BOARDS~8 CLA 1,846 06-05-01 10:45p BoardScope$CoreListener.class
BUSTRA~1 CLA 2,352 06-05-01 10:45p BusTrace.class
CLBDET~1 CLA 4,554 06-05-01 10:45p ClbDetail.class
COLORS~1 CLA 1,123 06-05-01 10:45p Colors.class
COREMA~1 CLA 4,159 06-05-01 10:45p CoreMatrix.class
COREVI~1 CLA 8,155 06-05-01 10:45p CoreViewer.class
IMAGES <DIR> 06-05-01 10:45p images
COREVI~2 CLA 2,285 06-05-01 10:45p CoreViewer$IDListener.class
BITTRA~1 CLA 6,283 06-05-01 10:45p BitTrace.class
BOARDS~1 CLA 24,385 06-05-01 10:45p BoardScope.class
BOARDS~2 CLA 1,603 06-05-01 10:45p BoardScope$MenuListener.class
BOARDS~3 CLA 3,111 06-05-01 10:45p BoardScope$CommandLineListener.class
BOARDS~4 CLA 922 06-05-01 10:45p BoardScope$WindowListener.class
BOARDS~5 CLA 2,888 06-05-01 10:45p BoardScope$ButtonListener.class
BOARDS~6 CLA 2,052 06-05-01 10:45p BoardScope$StateListener.class
BOARDS~7 CLA 1,646 06-05-01 10:45p BoardScope$WaveformListener.class
BOARDS~8 CLA 1,846 06-05-01 10:45p BoardScope$CoreListener.class
BUSTRA~1 CLA 2,352 06-05-01 10:45p BusTrace.class
CLBDET~1 CLA 4,554 06-05-01 10:45p ClbDetail.class
COLORS~1 CLA 1,123 06-05-01 10:45p Colors.class
COREMA~1 CLA 4,159 06-05-01 10:45p CoreMatrix.class
COREVI~1 CLA 8,155 06-05-01 10:45p CoreViewer.class
IMAGES <DIR> 06-05-01 10:45p images
COREVI~2 CLA 2,285 06-05-01 10:45p CoreViewer$IDListener.class
BITTRA~1 CLA 6,283 06-05-01 10:45p BitTrace.class
BOARDS~1 CLA 24,385 06-05-01 10:45p BoardScope.class
BOARDS~2 CLA 1,603 06-05-01 10:45p BoardScope$MenuListener.class
BOARDS~3 CLA 3,111 06-05-01 10:45p BoardScope$CommandLineListe
Article: 36073I think this discussion has gone too abstract. What is a reasonable max counter length? 64 bits, 80 bits, 100 bits, 140 bits? Who wants to count 100 MHz until the universe has frozen over a thousand times? There has to be some reason for all this. LFSRs are great as random number generators. Detecting zero is reasonably easy, but adds junk. So does arbitrary presetting... The conventional binary ripple-carry structure supported in good FPGAs is sufficiently compact and fast for all but the most exotic purposes. Peter Alfke glen herrmannsfeldt wrote: > Ray Andraka <ray@andraka.com> writes: > > >How long is *really long* ? As I pointed out, 1 CLB worth of LFSRs > >gets you a period of over 2000 years with a 100 MHz clock. > >The single LFSR actually gets more efficient as you increase its > >length, since the termnal count only grows at log2(N) and the LFSR > >grows at a little less than 1/17 that rate. Cascading 2 identical > >LFSRs gets you the same effect as doubling the length of a single > >LFSR, so it is more expensive. Cascading different lenght LFSRs, > >however may give you better granularity in your selection of period. > > Well, I said really really long. > > I don't know Virtex so well, so I don't know which mode you use > to do this. Does it include the feedback taps in that one CLB? > Can you select any feedback taps that you want? > > So you have a 64 bit LFSR to count your 2000 years, and need > a 6 bit counter to count the 64 successive zeroes. The suggestion > was to use a LFSR counter to count those zeroes, though, yes, > there might be better ways to count to 64. > > As you mention, two LFSR's with different periods could be run > in parallel and then detect the simultaneous zero of the two. > With only one more CLB you could get a 128 bit counter, and count > for 3e22 years. > > How many CLB's does it take to make a complete LFSR counter? > (Inlcuding the preset ROM and load logic for arbitrary counts?) > > -- glenArticle: 36074
> Does anyone have any reccomendations for physical layer interfaces and link > layer controller devices? I've found the > Altera IP for FPGA-based LLCs, but would prefer to have an external device > if possible, as I need all the logic resources for other things. I have used TI 1394 silicon in the past and found it to be pretty good. I am in the middle of a design using the Philips L40 link chip. It would be good for your a video application because of the AV support for streaming data. They have an eval kit called the "RDK" with headers for the streaming video that you could connect to your FPGA board. The other nice thing about the RDK is that it comes with a royalty free embedded 1394 stack running on an 8031 varient, that you can take and port to whatever processor you want. Jeff
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