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"Kolja Sulimma" <kolja@sulimma.de> wrote in message news:3BDC4A97.9505F214@sulimma.de... > > > Kevin Brace wrote: > > > Thanks to everyone who replied to the posting I made. > > Here are more details I will like to throw in. > > Looking at Xilinx IP Evaluation license, does this evaluation license > > stop someone from cloning Xilinx's IP cores? I think the the code is encrypted, so it would be difficult to use them on something else, anyway. Leon -- Leon Heller, G1HSM leon_heller@hotmail.con http://www.geocities.com/leon_heller Low-cost Altera Flex design kit: http://www.leonheller.comArticle: 36101
AME wrote: > > > And somehow, I think I am also quite new to the stuff, but > > until now I never had the feeling that I need to learn both VHDL AND > Verilog. > > I have a feeling that in the US it might be useful to have command of one > and a good familiarity with the other. Also, if you plan on using any IP it > might be important to not be locked into any one language. > > -Martin I would agree that it is useful to know both, but even if you don't plan to use IP. If you ever plan to switch jobs you have an even chance of needing to learn the other language. I am finding that most of the telecom companies in the Wash, DC area like Verilog. But nearly all of the DOD companies use VHDL. The former is likely because engineers move from one telecom job to another and take their preferences with them, the DOD community are "required" to use VHDL, I expect. But to be conversent in both languages is not so hard. I learned VHDL first and found it workable but always had trouble with type changes. I then learned Verilog and found few "trouble spots" that were unique. So now going back and forth is not hard as long as I keep a cheat sheet and example code nearby. I still can't remember details of procedure definitions, etc. in either language and like to code by copying rather than writing from scratch. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 36102
deerlux wrote: > I want to implement a bideriction bus buffer controlled by "DIR". But I > don't want to use 3-state gate.Can I do it? No, you cannot. What's wrong with 3-state? It has served us well for 35 years... Peter AlfkeArticle: 36103
"Leon Heller" <leon_heller@hotmail.com> wrote in message news:<9rk67c$gt2$2@uranium.btinternet.com>...
> > Kevin Brace wrote:
> > > Thanks to everyone who replied to the posting I made.
> > > Here are more details I will like to throw in.
> > > Looking at Xilinx IP Evaluation license, does this evaluation license
> > > stop someone from cloning Xilinx's IP cores?
>
> I think the the code is encrypted, so it would be difficult to use them on
> something else, anyway.
>
> Leon
It looks like Xilinx's LogiCORE PCI IP core is not encrypted, but they
don't provide a constraint file (user or physical) with the evaluation
version, so even if someone tries to synthesize it, it probably won't
meet PCI's timings (for 33MHz PCI, Tsu = 7ns and Tval = 11ns).
To tell you the truth, I have never synthesized Xilinx's PCI IP core,
so I don't know what will happen.
I am sure that it depends on the skill of the designer, but from my
experience trying to meeting timings with my own PCI IP core, I think
meeting 33MHz PCI timings with a synthesizable (HDL based) PCI IP core
with only automatic P&R is very challenging to say the least.
So, even with the Xilinx one which is supposedly done in schematics
(not HDL), without a physical constraint file, it probably won't
meeting PCI timings.
In Altera's case, their IP core is encrypted, and without getting a
license, the user cannot place the IP core onto the chip.
So, what I am thinking of doing (currently studying the
feasibility) is to create a clone (replica) in HDL that to large
extent behaves like the original, but the design was created from
reading user guide, analyzing the behavior, and not try to figure out
what is going on inside the netlist.
Regards,
Kevin Brace (don't respond to me directly, respond within the
newsgroup)
Article: 36104Hi Johann The most suitable devices for your project are: 1) Xilinx/CoolRunner family 2) Altera/MAX7000S family These devices are supported by free software: Xilinx/WebPACK Altera/MAX+PlusII BASELINE Also these devices support ISP - they can be easily reprogrammed via simple cables. If you'd like to have very little power consumption, choose CoolRunner device. Free VHDL & Verilog tutorials - see www.aldec.com best regardsArticle: 36105
I have a xcv600E design that is fairly well populated (82% utilization) and the P&R time (starting from scratch) on our best Sun workstation is ~ 2 hours (using Alliance s/w version 3.1i, though it says 'v3.3.08i' in the "About" dialog box). I've been reading up on the concept of 'guided design', which is supposed to let the software leverage the last P&R in doing the next P&R, which presumably produces a new bitstream in much less time. ...... my problem: I can see from the messages scrolling by in the Flow Engine's window, that yes the switches are activated for guided design, but it still takes in excess of 2 hours to do the P&R. This isn't the efficiency gain I was hoping for. I tried this for a design that had a small change (INIT contents of a Block RAM) and no change (same EDIF netlist), and there was no difference. What are the trick(s) to making this guided design thing actually work (faster)? Do I need to move up to the 4.1i release? Special patches? Does it even work at all (i.e., produce small design changes in less time)? Thanks in advance for any suggestions. -- ============================== William Lenihan lenihan3weNOSPAM@earthlink.net .... remove "NOSPAM" when replying ==============================Article: 36106
AME wrote: > > Can you provide a link to this document? A search for "the jtag primer" > returns nothing. It's called "Testability Primer" and can be found here: http://www-s.ti.com/sc/psheets/ssya002c/ssya002c.pdf Cheers, ER!KArticle: 36107
Hi all,
I'm using leonardo-spectrum from the altera site:
Version: v2001_1d.24_OEM_Altera
(Release OEM Altera Candidate, compiled Jul 5 2001 at 23:42:12)
When i modify vhdl code in a file and save it within leonardo, a
new "run flow" compilation frequently doesn't read the new file.
Is there a way around this problem?
--
___ ___
/ /\ / /\
/ /__\ Russell Shaw, B.Eng, M.Eng(Research) / /\/\
/__/ / Victoria, Australia, Down-Under /__/\/\/
\ \ / \ \/\/
\__\/ \__\/
Article: 36108Don Husby wrote: > > Mike Treseler <mike.treseler@flukenetworks.com> wrote in message news:<3BDF4799.A379AA16@flukenetworks.com>... > > Russell Shaw wrote: > > > ... > > > most of the > > > device settings you do in the flow tabs don't get > > > saved with the project. > > > > Haven't seen anything like that. > > Leonardo is full of things like that: project settings > flip around like a bad politician. Constraints evaporate. > Constraints are added. Flags appear to be set, but really > aren't. File names are changed. My favorite is when > each source file is added twice to the compile list. I found that too:( > The most consistently annoying is when the output file > name is silently changed - sometimes you don't discover > it until you've done a complete place and route, and find > that nothing changed. And that :(( > At some point, you just have to delete all of the Leonardo > project files (*.lsp *.scr *.xdb ...) and start over. > > It's amazing to me that the Leonardo user interface has > been so crappy for so many years. At some point, you > just have to delete Leonardo and start over. ...and i thought it was just meArticle: 36109
Greetings I'm using a Spartan XCS40XL part in a design which has several shift registers of various lengths and I'm using schematic entry. I'm confused as to how to specify the timing. I don't have enough clock buffers to use one for each shift register and I need obviously to ensure that a clock edge arrives at shift register flip-flop N before data has been shifted by flip-flop N-1, and it seems that this is a problem with my longer shift registers. Sometimes the problem goes away as the result of some other change, sometimes it reappears on another register so I'm sure it's a timing problem. I find the explanations of timing constraints pretty confusing and yet I'm sure this must be a common query. I'm unable to find any help which I can understand on the Xilinx website. How do I do this? I know it must be easy. Thanks -- ArthurArticle: 36110
I didn't see this question answered, so I'm posting under a slightly different subject. I just would like to know if Foundation 4.1i (w/SP1?) supports any more parts than 3.1i w/SP8. Trying to find this information on Xilinx's site isn't easy, I've already tried, that's why I'm asking here. I'm also curious if Foundation 4.1i actually has any real usefulness over Foundation 3.1i(w/SP8)? Is "XST" synth much better than the latest offerings from Synplicity(Synplify Pro 7.0) or Exemplar(Leonardo 2001.1d)? I found Foundation 3.3ISE pretty non-intuitive and I didn't like how with Foundation 3.3ISE the Xilinx ver. of FPGA Express would overwrite a non-Xilinx FPGA Express (and subsequently, wouldn't call the non-Xilinx version!). Thanks, VR.Article: 36111
Hello Newsgroup ! I have a problem setting up or configuring a SPROM via JTAG in the right manner. My programs are running if I download them directly into the FPGA (a Spartan2), no problem. But if I download the data into the SPROM the program is not starting at all. Do I have to setup some configurational stuff ? Or how can I get the program automatically downloading from SPROM to FPGA and starting? Also after reset, the program should be read into FPGA and started. The Software I am using is Xilinx Foundation ISE 3.3. Thank you for your help Regards, SteffenArticle: 36112
I doubt if any integrated DLL/PLL is good enough for this, depending on what level of phase noise/jitter performance you're looking for. When we're doing our DAC evaluations we have difficulty finding any clock source with low enough jitter, even low-noise benchtop RF generators. You might want to look at PLLs based on voltage-controlled SAW oscillators from vendors like Sawtek -- their lowest jitter VCSOs have about 0.01ps rms jitter... "Paul Teagle" <pteagle@bigpond.net.au> wrote in message news:<8Jbz7.175058$bY5.823126@news-server.bigpond.net.au>... > Related to the recent DLL/PLL discussions, are there any measured figures on > phase noise performance for the DLL/PLL. Are phase noise figures specific to > the divide/multiply ratios & frequencies used? > > From a quick look at the jitter figures, I doubt they are suitable to > directly drive eg a DAC in a direct IF synthesis scheme for high resolution > systems. > > Comments? > > Paul T. > CAE Inc > [at home]Article: 36113
Peter Alfke wrote: > > deerlux wrote: > > > I want to implement a bideriction bus buffer controlled by "DIR". But I > > don't want to use 3-state gate.Can I do it? > > No, you cannot. What's wrong with 3-state? It has served us well for 35 > years... > > Peter Alfke Long live open collector! While open collector gates can be slow they do have the one advantage that bus contention is simpler to deal with.Enables and disables can overlap with no problem. Mind you this is external to the FPGA. With what few tri-state circuits I use spend a lot of time fiddling to make sure the enables don't glitch. Ben. -- Standard Disclaimer : 97% speculation 2% bad grammar 1% facts. "Pre-historic Cpu's" http://www.jetnet.ab.ca/users/bfranchuk Now with schematics.Article: 36114
Ben; here are many uses for firewire, but among the best is the support for isochronous data (low latency) and multi streaming I/O peripherals like video from camcorders and tv's. There is a proposed enhancement in the forthcoming IEEE 1394B proposal to 800 Mbps. I have researched the PCI to Firewire interface and looked for devices that support the greatest number of features. The criteria is used was: Single chip PCI to Firewire solution Supports IEEE-1394 (100, 200MBps) and IEEE-1394A (100, 200, 400MBps) Supports PCI 2.1 interface +3.3 Volt power, +5V tolerant inputs Multiple port capability - 2 port minimum Here is the list of chip manufacturers that i have looked thru for a PCI to Firewire interface: Agere (single chip, low power features): FW322 (2 port, 120 pin TQFP) FW323 (3 port, 128 pin TQFP) Phillips (8/16 bit embedded soltion, **NO PCI interface**, here for completeness): PDI 11394L40 / 11394L41 (single port, link controller, LQFP144) PDI 1394P21 (3 port) / 1394P22 (3 port) / 1394P24 (2 port) Opti (dual chip - supports USB/Firewire thru PCI like Orange Micro card): 82C881 / TriFire (3 ports, 100 pin & 64 pin TQFP) Texas Instruments: (single chip, compliant with Intel Mobile Power Guideline 2000) TSB43AA22 (2 port, 128 pin TQFP) TSB43AA82 (2 port, 128 pin TQFP) TSB43AB21 (1 port, 128 pin TQFP) TSB43AB22 (2 port, 128 pin TQFP) VIA (single chip, low power features): VT6306 (3 ports, 128 pin PQFP) The selection of the number of ports and the other features can be discussed by engineering. My suggestion is one of these: Agere, TI, or VIA. And BTW, not everyone is embracing USB 2.0: http://www.agere.com/NEWS/PRESS2001/071601a.html "e-m" Ben wrote: > Hi all, > I'm working on a university project invloving using Firewire (IEEE 1394) > interfaces for input and output from an FPGA-based video processing board. > The firewire will form a link from a DV camera to the board, and from the > board to a PC/workstation. > > Does anyone have any reccomendations for physical layer interfaces and link > layer controller devices? I've found the > Altera IP for FPGA-based LLCs, but would prefer to have an external device > if possible, as I need all the logic resources for other things. > > Also, has anyone else done this kind of thing before? If so, any > hints/tips/links would be handy. > > Thanks, > Ben.Article: 36115
hi, Is the timing analysis after synthesis and after mapping very different? I used synopsys design compiler for synthesis and I got a max_time delay as 140 ns for a 56 bit adder, whereas after mapping using xilinx alliance tool on xcv1000 virtex, i get a minimum period as 35ns [but here I had instantiated this 56 bit adder as partof another entity] still why is there such a big difference between the timing? and as such while reporting what is the timing I shud consider? kindly help. nandiniArticle: 36116
Steffen Thieringer a ιcrit : > > Hello Newsgroup ! > I have a problem setting up or configuring a SPROM via JTAG in > the right manner. > My programs are running if I download them directly into the > FPGA (a Spartan2), no problem. > But if I download the data into the SPROM the program is not > starting at all. > Do I have to setup some configurational stuff ? > Or how can I get the program automatically downloading from > SPROM to FPGA and starting? > Also after reset, the program should be read into FPGA and > started. Hi Are you using a reprogrammable PROM or not? I didn't understand very well. Anyway, if you want to use an SPROM to configure your FPGA, you need to generate a bitstream with CClk as tha startup clock, whereas the bitstream for JTAG downloading has JtagClock as the startup clock. You then need to generate a PROM file with the PROM File Formatter (usually this will be a .mcs) that will be downloaded into the SPROM. Hope this helps -- Nicolas MATRINGE IPricot European Headquarters Conception electronique 10-12 Avenue de Verdun Tel +33 1 46 52 53 11 F-92250 LA GARENNE-COLOMBES - FRANCE Fax +33 1 46 52 53 01 http://www.IPricot.com/Article: 36117
--------------D27CCF965B13619C1551498A Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit You Bet Phase Noise is an Issue! Sampling at the IF is the "Holy Grail" of the monster Xtreme DSP (tm) engines in all of the 3G and later basestations. The spurious free dynamic range (SFDR) is directly degraded by any phase noise, and is THE problem of the day. Analog Devices has an excellent applications note on this subject, and some exciting products: http://products.analog.com/products/info.asp?product=AD6645 0.3 ps (RMS) is all that is allowed at a 100 MHz IF (desired specification -- no one has met it as a clcok source). Think about it. Ian is right on the money when he states that even the best bench top generators are 10 to 30 times worse than this. The solution I have seen is to use the absolute best resonator (SAW is good), followed by the best differential clock driver that can be found, in an isolated analog plane with isolated analog supplies, with a solid tin can over the whole thing (faraday shielded) driving the A/D and also driving the FPGAs (from another output of the clock driver for further isolation). The present state of the art jitter is ~3 to 6 ps this way. Once the data is sampled at the A/D, then jitter from then on is a don't care, as the sampling instant defined the SFDR, and it is all digital (and downhill) from there. The frustrating thing is that since the resolution is governed by the sampling instant (decision is made), there is nothing one can do to recover resolution after the fact if there is noise. This is one reason why in set top satellite receivers they downconvert the IF to ~8 MHz so that sampling such a low frequency IF is possible for the amount of money that they can spend in such a box. Unfortunately, in a 3G base station, the information bandwidth is wide enough, that conversion down to such a low IF is not as ideal. This is why many designs still convert down to the baseband (DC) with separate I and Q channels (mixers) and then proceed to adaptively equalize and repair all of the distortion added by the down conversion and I/Q separation process. Austin Ian Dedic wrote: > I doubt if any integrated DLL/PLL is good enough for this, depending > on what level of phase noise/jitter performance you're looking for. > When we're doing our DAC evaluations we have difficulty finding any > clock source with low enough jitter, even low-noise benchtop RF > generators. > > You might want to look at PLLs based on voltage-controlled SAW > oscillators from vendors like Sawtek -- their lowest jitter VCSOs have > about 0.01ps rms jitter... > > "Paul Teagle" <pteagle@bigpond.net.au> wrote in message news:<8Jbz7.175058$bY5.823126@news-server.bigpond.net.au>... > > Related to the recent DLL/PLL discussions, are there any measured figures on > > phase noise performance for the DLL/PLL. Are phase noise figures specific to > > the divide/multiply ratios & frequencies used? > > > > From a quick look at the jitter figures, I doubt they are suitable to > > directly drive eg a DAC in a direct IF synthesis scheme for high resolution > > systems. > > > > Comments? > > > > Paul T. > > CAE Inc > > [at home] --------------D27CCF965B13619C1551498A Content-Type: text/html; charset=us-ascii Content-Transfer-Encoding: 7bit <!doctype html public "-//w3c//dtd html 4.0 transitional//en"> <html> You Bet Phase Noise is an Issue! <p>Sampling at the IF is the "Holy Grail" of the monster Xtreme DSP (tm) engines in all of the 3G and later basestations. <p>The spurious free dynamic range (SFDR) is directly degraded by any phase noise, and is THE problem of the day. <p>Analog Devices has an excellent applications note on this subject, and some exciting products: <p> <a href="http://products.analog.com/products/info.asp?product=AD6645">http://products.analog.com/products/info.asp?product=AD6645</a> <p>0.3 ps (RMS) is all that is allowed at a 100 MHz IF (desired specification -- no one has met it as a clcok source). Think about it. Ian is right on the money when he states that even the best bench top generators are 10 to 30 times worse than this. <p>The solution I have seen is to use the absolute best resonator (SAW is good), followed by the best differential clock driver that can be found, in an isolated analog plane with isolated analog supplies, with a solid tin can over the whole thing (faraday shielded) driving the A/D and <b>also driving the FPGAs</b> (from another output of the clock driver for further isolation). <p>The present state of the art jitter is ~3 to 6 ps this way. <p>Once the data is sampled at the A/D, then jitter from then on is a don't care, as the sampling instant defined the SFDR, and it is all digital (and downhill) from there. <p>The frustrating thing is that since the resolution is governed by the sampling instant (decision is made), there is nothing one can do to recover resolution after the fact if there is noise. This is one reason why in set top satellite receivers they downconvert the IF to ~8 MHz so that sampling such a low frequency IF is possible for the amount of money that they can spend in such a box. Unfortunately, in a 3G base station, the information bandwidth is wide enough, that conversion down to such a low IF is not as ideal. <p>This is why many designs still convert down to the baseband (DC) with separate I and Q channels (mixers) and then proceed to adaptively equalize and repair all of the distortion added by the down conversion and I/Q separation process. <p>Austin <p>Ian Dedic wrote: <blockquote TYPE=CITE>I doubt if any integrated DLL/PLL is good enough for this, depending <br>on what level of phase noise/jitter performance you're looking for. <br>When we're doing our DAC evaluations we have difficulty finding any <br>clock source with low enough jitter, even low-noise benchtop RF <br>generators. <p>You might want to look at PLLs based on voltage-controlled SAW <br>oscillators from vendors like Sawtek -- their lowest jitter VCSOs have <br>about 0.01ps rms jitter... <p>"Paul Teagle" <pteagle@bigpond.net.au> wrote in message news:<8Jbz7.175058$bY5.823126@news-server.bigpond.net.au>... <br>> Related to the recent DLL/PLL discussions, are there any measured figures on <br>> phase noise performance for the DLL/PLL. Are phase noise figures specific to <br>> the divide/multiply ratios & frequencies used? <br>> <br>> From a quick look at the jitter figures, I doubt they are suitable to <br>> directly drive eg a DAC in a direct IF synthesis scheme for high resolution <br>> systems. <br>> <br>> Comments? <br>> <br>> Paul T. <br>> CAE Inc <br>> [at home]</blockquote> </html> --------------D27CCF965B13619C1551498A--Article: 36118
Nandini wrote: > > hi, > > Is the timing analysis after synthesis and after mapping very > different? Yes. The synthesis timing is an estimate based on average delays for the selected device. Unless place and route takes a long time, you don't have to bother with this analysis. The static timer after place and route is the (sometimes awful) truth. The timing differences are due to fact that few place and routes hit the average values. --Mike TreselerArticle: 36119
I stand corrected: open "collector" is a viable alternative. Advantage: No risk of contention when enables overlap Disadvantage: Needs passive pull-up ( usually a resistor ), which makes it slow. Good choice if you don't need speed, and you have the pull-up resistor. BTW: You can convert any 3-state driver into open collector by connecting the D input and the 3-state ( active Low output enable ) together. I suppose everybody knows that... Peter Alfke ====================== deerlux wrote: > I want to implement a bideriction bus buffer controlled by "DIR". But I > don't want to use 3-state gate.Can I do it? > Thank you!Article: 36120
django625 schrieb: > > Greetings > > I'm using a Spartan XCS40XL part in a design which has several shift > registers of various lengths and I'm using schematic entry. I'm > confused as to how to specify the timing. I don't have enough clock > buffers to use one for each shift register and I need obviously to > ensure that a clock edge arrives at shift register flip-flop N before > data has been shifted by flip-flop N-1, and it seems that this is a > problem with my longer shift registers. ;-)) The global clock buffers drive a clock net for the whole chip. So all you need is just to connect your clock input pin to a global clock buffer and then use this signal for all FFs in the shift register. Works nice, you dont have to worry about skew, fan-out, hold-time etc. -- MFG FalkArticle: 36121
Try to:) Cycle the power after the prom is programmed , if your design is done so that master serial configuration is expected (M1=M2=M3=GND on the spartan2) then the configuration should be automatic after power up! There is a way to do this without powering down/up if you have the right connections between your prom/fpga/JTAG, check xilinx docs for details. jakab Steffen Thieringer <steffen.thieringer@nmb.co.uk> wrote in message news:9rmch4$uegf1$1@ID-41871.news.dfncis.de... > Hello Newsgroup ! > I have a problem setting up or configuring a SPROM via JTAG in the right > manner. > My programs are running if I download them directly into the FPGA (a > Spartan2), no problem. > But if I download the data into the SPROM the program is not starting at > all. > Do I have to setup some configurational stuff ? > Or how can I get the program automatically downloading from SPROM to FPGA > and starting? > Also after reset, the program should be read into FPGA and started. > > The Software I am using is Xilinx Foundation ISE 3.3. > > Thank you for your help > > Regards, > Steffen >Article: 36122
You should also make sure that the startup clock is set to CCLK in bitgen. This is -g StartUpClk:CCLK or in Design Manager Design/Options.../Configuration: Edit Options/Startup/click on CCLK radio button. Alan NishiokaArticle: 36123
I want to implement a bideriction bus buffer controlled by "DIR". But I don't want to use 3-state gate.Can I do it? Thank you!Article: 36124
William Lenihan <lenihan3we@earthlink.net> writes: > I have a xcv600E design that is fairly well populated (82% utilization) > and the P&R time (starting from scratch) on our best Sun workstation is > ~ 2 hours (using Alliance s/w version 3.1i, though it says 'v3.3.08i' in > the "About" dialog box). I have a xcv1000e design which takes 7-8 hours on a guided par, a full par takes 22 hours or so. This is on a 1.2GHz PC. On my fastest Sun it takes 3x as long :-( I suggest you write some shell scripts or similar to run the par job so you can specify the exact options on the command line. However, I don't think it will get very much faster. If you have lots of workstations you can run multiple iterations and pick the best. Petter -- ________________________________________________________________________ Petter Gustad 8'h2B | (~8'h2B) - Hamlet in Verilog http://gustad.com
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