Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Also, there's a crazy dude making a "meta FPGA" which is an FPGA with an open bitstream that resides on a Xilinx. Do a search on "meta fpga". I think he's got a website. Doesn't Altera have a public bitstream? Otherwise, how would ClearLogic be able to clone parts with just an Altera bitfile? "Nicholas Weaver" <nweaver@CSUA.Berkeley.EDU> wrote in message news:9rumr9$uc$1@agate.berkeley.edu... > In article <3BE2DCF1.3E7E12D3@AAI.ca>, > Patrick Maheral <pmaheral@AAI.ca> wrote: > > >Does anyone know of another FPGA with available (preferably open, > >ie. no NDA required) configuration bitstream documentation. > > >Any pointer would be appreciated. > > Xilinx Virtex: > > Jbits provides an API to directly edit the configuration bitfiles. > > Appnote, "Virtex Series Configuration Architecture User's Guide" > http://www.xilinx.com/xapp/xapp151.pdf > > Enjoy! > -- > Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 36226
--------------518AA323FEBB00DEF86C0769 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Well, Illegally, based on the recent court decision. Austin snip > how would ClearLogic be able to clone parts with just an Altera bitfile? snip --------------518AA323FEBB00DEF86C0769 Content-Type: text/html; charset=us-ascii Content-Transfer-Encoding: 7bit <!doctype html public "-//w3c//dtd html 4.0 transitional//en"> <html> Well, <p>Illegally, based on the recent court decision. <p>Austin <p>snip <blockquote TYPE=CITE><b>how would ClearLogic be able to clone parts with just an Altera bitfile</b>?</blockquote> snip</html> --------------518AA323FEBB00DEF86C0769--Article: 36227
This is a multi-part message in MIME format.
------=_NextPart_000_0056_01C1639E.355DB200
Content-Type: text/plain;
charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable
Hmmm. The only news about this I could find was this, from Reuters:
"Separately, Altera said that the U.S. District Court for the Northern =
District of California ruled that using Altera software to program a =
chip made by Clear Logic is a violation of Altera's licensing agreement =
with Clear Logic."
Licensing agreement? Why would Altera have made a licensing agreement =
with a cloner? Was this some sort of spinoff? And why can't customers =
just send the source code to Clear Logic and let them create their own =
bitfile?
PS here's the "MPGA" website. This page has the best ASCII schematic =
I've ever seen.
http://ce.et.tudelft.nl/~reinoud/mpga/README.html
"Austin Lesea" <austin.lesea@xilinx.com> wrote in message =
news:3BE2EB89.5D046CC2@xilinx.com...
Well,=20
Illegally, based on the recent court decision.=20
Austin=20
snip=20
how would ClearLogic be able to clone parts with just an Altera =
bitfile?
snip=20
------=_NextPart_000_0056_01C1639E.355DB200
Content-Type: text/html;
charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META http-equiv=3DContent-Type content=3D"text/html; =
charset=3Diso-8859-1">
<META content=3D"MSHTML 6.00.2600.0" name=3DGENERATOR>
<STYLE></STYLE>
</HEAD>
<BODY bgColor=3D#ffffff>
<DIV><FONT face=3DArial size=3D2>Hmmm. The only news about this I =
could find=20
was this, from Reuters:</FONT></DIV>
<DIV><FONT face=3DArial size=3D2></FONT> </DIV>
<DIV><FONT face=3DArial size=3D2>"Separately, Altera said that the U.S. =
District=20
Court for the Northern District of California ruled that using Altera =
software=20
to program a chip made by Clear Logic is a violation of Altera's =
licensing=20
agreement with Clear Logic."</FONT></DIV>
<DIV><FONT face=3DArial size=3D2></FONT> </DIV>
<DIV><FONT face=3DArial size=3D2>Licensing agreement? Why would =
Altera have=20
made a licensing agreement with a cloner? Was this some sort of=20
spinoff? And why can't customers just send the source code to =
Clear Logic=20
and let them create their own bitfile?</FONT></DIV>
<DIV><FONT face=3DArial size=3D2></FONT> </DIV>
<DIV><FONT face=3DArial size=3D2>PS here's the "MPGA" website. =
This page has=20
the best ASCII schematic I've ever seen.</FONT></DIV>
<DIV><FONT face=3DArial size=3D2><A=20
href=3D"http://ce.et.tudelft.nl/~reinoud/mpga/README.html">http://ce.et.t=
udelft.nl/~reinoud/mpga/README.html</A></FONT></DIV>
<BLOCKQUOTE=20
style=3D"PADDING-RIGHT: 0px; PADDING-LEFT: 5px; MARGIN-LEFT: 5px; =
BORDER-LEFT: #000000 2px solid; MARGIN-RIGHT: 0px">
<DIV>"Austin Lesea" <<A=20
=
href=3D"mailto:austin.lesea@xilinx.com">austin.lesea@xilinx.com</A>> =
wrote in=20
message <A=20
=
href=3D"news:3BE2EB89.5D046CC2@xilinx.com">news:3BE2EB89.5D046CC2@xilinx.=
com</A>...</DIV>Well,=20
<P>Illegally, based on the recent court decision.=20
<P>Austin=20
<P>snip=20
<BLOCKQUOTE TYPE=3D"CITE"><B>how would ClearLogic be able to clone =
parts with=20
just an Altera bitfile</B>?</BLOCKQUOTE>snip =
</BLOCKQUOTE></BODY></HTML>
------=_NextPart_000_0056_01C1639E.355DB200--
Article: 36228the 6 hour PAR time sounds a little long. i am using the XC2V1000 right now in a design of mostly control logic and is 98% full (really bad, i know). the PAR time is about 45 minutes with my P4, 1.7GHz computer. it also has 1 gigabyte of RAMBUS which i believe greatly improves the speed. by the way, the XC2V1000 is probably equivalent to something around a XCV300 in terms of usable logic gates, which means that it might take more time to PAR a large XCV600 design. if you are using a pentium4 chip, you might want to consider adding RAMBUS to the max amount of supported memory, if you haven't already. the savings in time i get versus my regular work computer is tremendous. chrisArticle: 36229
Right, but the real reason is to provide fast connections for logic using the
carry/cascade chains. Those chains run across the LE's in a LAB, which prevents
the LE's from connecting to another LE in the same LAB. The inter-lab connects
give you a way to connect arithmetic logic with a reasonable delay.
Steve Fair wrote:
> Digari -
>
> It's all about speed . . .
>
> The interleaving of the labs gives the router more flexibility. Each lab
> has it's own local routes, which is the fastest non-dedicated route (as
> opposed to carry or cascade chains). If all the logic between two flops can
> fit into a lab, you will achieve the best performance possible. If the
> logic can't fit into the lab, you go to a megalab route in the apex II
> architecture, which adds delay AND uses another routing resource. By
> interleaving the labs, an LE can be connected to many more LE's for making
> those fast, local connections. The area expense isn't that great (a single
> line and mux to the next lab's local interconnect), so it's a very efficient
> way to increase routing and performance. Put another way, a lab goes from
> having 9 possible local connections to 19 with very little overhead. With
> the further interleaving available (remember the left & right drives), you
> can do some pretty deep equations with very small routing delays.
>
> Hope that helps.
>
> Steve
>
> "digari" <digari@dacafe.com> wrote in message
> news:e0855517.0111010034.375d9328@posting.google.com...
> > Why there is interleaved routing from an LE to adjecent LLIs in
> > Mercury and ApexII architectures.
> >
> > "APEX II devices use an interleaved LAB structure, so that each LAB
> > can
> > drive two local interconnect areas. Every other LE drives to either
> > the left
> > or right local interconnect area, alternating by LE."
> >
> > Can anyone shed some light on the alternate routing structure of LEs
> > within a LAB.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 36230
That may be a comparison of ducks to oranges (apples would be closer, at
least there they are both fruits). How close your constraints are set to
the delay with no routing has a big bearing on the PAR time. If your
design is big enough that the computer has to start paging, your compile
times go to hell in a handbasket as well. Also, if parts of the design
are floorplanned, you can reduce the run times considerably.
chris wrote:
> the 6 hour PAR time sounds a little long. i am using the XC2V1000
> right now in a design of mostly control logic and is 98% full (really
> bad, i know). the PAR time is about 45 minutes with my P4, 1.7GHz
> computer. it also has 1 gigabyte of RAMBUS which i believe greatly
> improves the speed. by the way, the XC2V1000 is probably equivalent to
> something around a XCV300 in terms of usable logic gates, which means
> that it might take more time to PAR a large XCV600 design.
> if you are using a pentium4 chip, you might want to consider adding
> RAMBUS to the max amount of supported memory, if you haven't already.
> the savings in time i get versus my regular work computer is
> tremendous.
> chris
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 36231Lattice has a core on their site for 32-bit PCI, but I'm wondering if there is available from Lattice or third parties a 64-bit core. It would be ideal if it can run at 66MHz to boot. I'm looking to target an ispLSI8600VE. Such a core would be helpful because it would let me save an additional chip on our circuit board. Right now we're using a different (much smaller) CPLD on our board for other, non-PCI functions. I'm getting ready to design the second revision. I'm leaning towards the Lattice chip because I've been unsatisfied with the s/w tools for the chip I have now, and because I really could use the internal tristate busses on the 8000 series. The 8600VE is way, way overkill in terms of macrocell density as a direct replacement for our current CPLD, but if I could integrate the PCI core onto the chip as well then I think it's justifiable. BTW, anybody out there have any experience with Lattice's tools? What are your thoughts on them? Alex Rast arast@qwest.net arast@inficom.comArticle: 36232
Peter Alfke <palfke@earthlink.net> writes: >If you have an error at such a low frequency, ( anything below 20 MHz ), >lowering the frequency even more will never cure the problem, since excessive >delay is not the cause. >(Almost fits on a fortune cookie...) What a great idea! Fortune cookies with EE fortunes on them. Might as well have them for other kinds of engineering and science, too! -- glenArticle: 36233
> > BTW, anybody out there have any experience with Lattice's tools? What are your > thoughts on them? I got into Lattice because they gave me a demo CD and I was new to CPLD/FPGA. Now, after several years and larger designs I've gone over to Xilinx webpack (free again). The FPGA logic density is massive in comparison, CPLDS that compare to Lattice. The biggest problem with Lattice was that I had a design that fitted to an 81080 only if the software picked the pin out. If I specified the same pinout the software would not fit. My advice is to try Xilinx as they are generally cheaper (UK). DaveArticle: 36234
Hi. I'm using Xilinx WebPack with a SpartanII board. I have checked everything on my board time and again, but I keep getting the following error message when trying to use the Xilinx JTAG Programmer software: 'counter(Device1): Manufacturer's ID = Unknown Manufacturer ID : 01110001000001001000001001110001 The design, a simple counter, has the correct device name specified when the design is synthesized to a bit file. I'm tempted to ditch using the JTAG from parallel and try another cable setup. Does anyone know what my problem is here?? ThanksArticle: 36235
Have you actually measured that the frequency going into the xc6216 is 1MHz/2 using a scope? It may not work exactly as the software tells it to. Jim "Pedro Alexandre" <pedro_alves.4@netc.pt> wrote in message news:3be1c401@212.18.160.197... > Hello > > Does anyone remember the HOT Works board with the xc6216 (and 2MB SRAM)? > I'm working on that board and I'm implementing a circuit that reads some > portions of memory, acumulate its contents and writes the result to SRAM. > I'm experiencing some problems accessing the on-board SRAM. With a 32 bit > access from the XC6000, some significant bits are wrong. It may be a problem > with the frequency because the circuit worked fine with a step by step user > clock. I've tried to lower the frequency to its minimum value (1MHz/2) by > software (JAVA), and the problem is still there. Does anyone had the same > problem? An internal freq. divider would solve the problem? > > thanks, > pedro > > -- > ___________________________________ > _.._ > .' .-'` > / / > | | > \ \ > '._'-._ > ``` > , , > |\---/| > / , , | > __.-'| / \ / > __ ___.-' ._O| > .-' ' : _/ > / , . . | > : ; : : _/ > | | .' __: / > | : /'----'| \ | > \ |\ | | /| | > '.'| / || \ | > | /|.' '.l \\_ > || || '-' > '-''-' > > >Article: 36236
> 'counter(Device1): Manufacturer's ID = Unknown Manufacturer ID : > 01110001000 001001000 001001110001 > Probably you have a defective device. Xilinx id is 49h, while the idcode shows 48h (bits 20:12). JimArticle: 36237
There is an article from EE Times that provides quite a bit of data on both parts that you mentioned. http://www.eet.com/story/industry/semiconductor_news/OEG20011031S0025 http://www.eetimes.com/story/OEG20011016S0097 Altera has demonstrated samples of the XA10 at trade shows and there are parts listed at distribution, staring at over US$2,000 each (single quantity). Looks like Altera's MIPS project is on the back burner, though. All information on the MIPS-based product was removed from their web site. I haven't seen a physical Virtex 2 Pro device yet but I know of at least one company that is an "alpha" site. There doesn't appear to be any datasheet on the Xilinx web site and I don't see any parts listed at distribution. Both companies presented thier solutions at the Microprocessor Forum in October. These are exciting parts, assuming that you can afford them. For comparison, there are other companies are already shipping similar, more cost-effective devices in production. Triscend, for example, has been shipping 32-bit ARM-based devices with embedded programmable logic for over a year now. The Triscend A7 family is in production, available through distribution, and is supported by compilers, synthesizers, simulators, development boards, etc. The largest family member starts at about US$40, single piece. The A7 configurable system includes cache, DMAs, UARTs, on-chip SRAM, SDRAM controller, and lots of I/O pins. http://www.triscend.com/products/indexa7.html For smaller systems, our 8-bit accelerated 8051-based E5 family has parts starting as low as US$9 in single-piece quantities, or below US$4 in high volumes. Like the A7 family, the E5 family is well supported by development tools and boards. The E5 family has been in production since 1999. http://www.triscend.com/products/IndexE5.html Both product families are supported by the Triscend FastChip development system and the FastChip drag-and-drop IP library, complete with standard peripheral functions. http://www.triscend.com/products/IndexFCintro.html http://www.triscend.com/products/indexfc_ip.html "Jae-cheol Lee" <jchlee@lge.com> wrote in message news:<dvHD7.1657$cI6.685978@news.bora.net>... > There were some news about Virtex II with PowerPC cores. > Altera announced Excalibur series with ARM or MIPS cores. > > What is the schedule of production of the first one? > > Is there any good story on the use of the second one? > > Please let me know...Article: 36238
Hello, We have a problem implementing Altera NIOS soft core in ACEX 1K device. It seems that the only target architecture is APEX 20KE. The Verilog files generated by the Wizard contain some apex20ke_lcell, which cannot be processed by Quartus II software when targeting project to the ACEX devices. The Wizard performs only functional tuning, not asking about preferred targed device. Oddly enough, Altera reports ACEX and FLEX among supported architectures. Thank you. IgorArticle: 36239
I am currently trying to synthesize a loadable
accumulator with synopsis. The target architecture
is a spartan. (not 2)
In my opinion the code below should fit into one 4 LUT
per bit. (inputs to each 4 LUT: pc, cin, load, inp)
However, after synthesis the design requires no less
than 16 4-luts.
Did I miss something ? Is there any way to infer a
combined add/load structure ? I already tried
lots of combinations without success and unfortunately
it seems that the xilinx libs dont allow direct
access to the LUTs and the carry logic for spartan..
(They do for spartan 2)
------------------------------------------------------
architecture synth of counter is
signal pc: std_logic_vector(7 downto 0);
begin
process(clk)
begin
if (res ='1') then
pc <= "00000000";
elsif rising_edge(clk) then
if (load = '1') then
pc <= inp;
else
pc <= pc + inp;
end if;
end if;
end process;
outp <= pc;
end synth;
Article: 36241Hi, if You want to implement NIOS core in ACEX familiy, You have to use the Max+PlusiI tool, as the ACEX isn't (yet) supported by Quartus. HTH, Carlhermann SchlehausArticle: 36242
glen herrmannsfeldt wrote: > Peter Alfke <palfke@earthlink.net> writes: > > >If you have an error at such a low frequency, ( anything below 20 MHz ), > >lowering the frequency even more will never cure the problem, since excessive > >delay is not the cause. > >(Almost fits on a fortune cookie...) > > What a great idea! Fortune cookies with EE fortunes on them. > > Might as well have them for other kinds of engineering and > science, too! > > -- glen If we get in quick we could all make our fortunes this Christmas with a gift ``for the engineer who has everything - even a Spartan3''. The first ever (?) C.A.F based virtual start-up with share options allocated on the wit and depth of contributed `fortunes'; Anyone got any first round funding to spare?Article: 36243
> > Yes, this is possible. But my read/write clocks are independent, and > > the source codes I have seen use gray-coding to reliably sample the > > read/write addresses across the read/write clock domains for status > > signal generation . Correctly me if I am wrong: but I think gray > > Right, the use gray code to transfer the write/read pointers across the > clock boundary. But the use normal binary couters for addressinf the two > port of the RAM , arnt they? Hi Falk, Thanks for sticking around. :-) Yes, normal binary counters are used as address pointers to the two ports of the RAM. But I think the reason for using gray-coding is because all consecutive gray-code differ by only one bit, including the last and the first gray-code (when the address pointer wraps around). That means during all times, when the gray-code in read/write domain is sampled by the opposite clock domain (to be used to generate those full/empty/element count status), the opposite clock domain is always certain to gets a gray code that is reliable. If we truncate the gray-code, then when the gray-code wraps around back to the first one, we lose the gray-code feature. As an example, let's consider a 8-word deep fifo using 3-bit gray code. Binary Code (used as address pointer) 000 001 010 011 100 101 110 111 Gray code 000 001 011 010 110 111 101 100 Suppose I decide to have a fifo that is only 6-word deep, so my binary code goes from 000 to 101 before wrapping back to 000. My corresponding gray code will be 000 to 111 before wrapping back to 000. Going from 111 to 000 there are 3 bits flipping. If my write pointer is sampled by the read clock at exactly the instant my write gray-code is flipping from 111 to 000, I may end up sampling 101 or 100 or 110 or any other thing. When this garbage value is used to derive empty or element count signals or other status signals in the read domain, I end up with unreliable status. Now that I am staring at the gray code, it looks to me that if we make the jump from 011 to 111, we have a 6-code long gray code. I wonder if there is a systematic way of generating gray codes that are not power-of-2 long. Actually, my problem at work has been "solved" because they have decided they do not need such a big fifo afterall. But I do enjoy the discussions because I think I have much to learn. Thanks. TA TA. Regards, kahheanArticle: 36244
Sorry for not ansering this before now, been a busy week.
>> But for me, it's ok as long the jitter (to the 'DAC') stays withing
>> (the equal to) 1/2 - 1 LSB of my signal.
> I think you got something wrong. Jitters does NOT mean an error in the
> sampling value, it means an error in sampling TIME.
I know, thats why I added 'the equal to'. The result of the jitter will
(if jitter is big enough) result in an error in the amplitude (as Ray
pointed out).
> Anyone got some basic numbers?
> How much does a jitter of lets say 10ns affect the audio quality when
> sampling (RECONSTRUCTING) at 44.1kHz (22.6 us period, so 10ns is just
> 0.04% timing error)
I can try to give a easy example (please correct me if I'm wrong)
But before I start, remember all the jitter noise isn't always inside
your 'signal-band' (the part of the freqdomain your using for your
signal), e.g. if you have a system using oversampling. Then you can
probably have more jitter before it affects your signal (more than you
want).
Jitter -> amplitude error
We look at 'worst case'.
We first need a signal for calculating the error. 20kHz sinus signal is
close to 'worst case' in a system with 44,1KHz sample rate.
The signal is full amplitude. (peaks at -1 and 1)
The biggest change in the signal amplitude per sample is when
it's close to 0. (derivative of sin is cos, cos(0) = 1)
signal freq 20kHz
-> 1/20kHz = 50us is one period (360 deg)
Jitter error 10ns
-> How many degrees is that for the signal
1 degree : 50us / 360deg = 138,89ns/deg
10ns / 138,89ns/deg = 0,072deg
Amplitude for 0.072deg error (biggest close to 0)
-> sin(0,072) = 0,0012566
Amplitude error in % : 1,2566% (or /2, depends on how you look at it)
So for the 0.04% timing error we get a 1,2566% amplitude error (20KHz
sinus signal - worst case)
Was this understanable? (haveing a whiteboard and markers is quite
easyer :-)
And did I get it/the numbers correct?
)RST(
Article: 36245Sorry, I didn't mean to be offensive! English is not my native language; sure "whining" was not the right term. I was trying to say that in my opinion there's not a simple answer to vhdl / verilog issue; I was trying to share the point of view of a "newbie" like me. I apologize for my offensive use of the term. "AME" <AME3141592@yahoo.com> ha scritto nel messaggio news:9rkhtb0bop@enews1.newsguy.com... > "Antonio Pasini" <pasini.a@libero.it> wrote in message > news:RUOC7.18406$Qj6.1344938@news.infostrada.it... > > > So... stop whining :-), take your next idea, take a book, a compiler and > > start playing around. It's really worthwile! > > Just for the record. I have not been whining at all. It is a fact that the > choices today are VHDL and Verilog (and Handel-C) and, after much reading > and thinking about the comments on ths NG I decided to concentrate on VHDL, > which is what I'm doing now. > > My comments about a "next generation" approach have nothing to do with > complaining as much as just offering ideas for anyone who might be listening > on what might help increase a designer's productivity. > > -Martin > > >Article: 36246
"Robert Staven" <robertst.stopthespam@tihlde.org> schrieb im Newsbeitrag news:3BE3FB78.3010609@tihlde.org... > I can try to give a easy example (please correct me if I'm wrong) > But before I start, remember all the jitter noise isn't always inside > your 'signal-band' (the part of the freqdomain your using for your > signal), e.g. if you have a system using oversampling. Then you can Right, AFAIK this is called noise shaping and is heayly used with Sigma-Delta DAC/ADCs ?! > Jitter -> amplitude error > We look at 'worst case'. > We first need a signal for calculating the error. 20kHz sinus signal is > close to 'worst case' in a system with 44,1KHz sample rate. > The signal is full amplitude. (peaks at -1 and 1) > The biggest change in the signal amplitude per sample is when > it's close to 0. (derivative of sin is cos, cos(0) = 1) > > signal freq 20kHz > -> 1/20kHz = 50us is one period (360 deg) > > Jitter error 10ns > -> How many degrees is that for the signal > 1 degree : 50us / 360deg = 138,89ns/deg > 10ns / 138,89ns/deg = 0,072deg > > Amplitude for 0.072deg error (biggest close to 0) > -> sin(0,072) = 0,0012566 > > Amplitude error in % : 1,2566% (or /2, depends on how you look at it) its just 0.125 % , the dot moved on digit ;-) > So for the 0.04% timing error we get a 1,2566% amplitude error (20KHz > sinus signal - worst case) Hmm, althrough its "just" 0.12% its freigthning. This doesnt sound like 16 bit quality. And thing can get worse if we lower the amplitude of our signal (still music) > Was this understanable? (haveing a whiteboard and markers is quite > easyer :-) > And did I get it/the numbers correct? Not at all. But I think the point lies in the noise shaping, which can transform the nois outside the audio band. -- MfG FalkArticle: 36247
Hello, I am new to FPGA/PLA/CPLD technology. I have a couple questions about them. (1) How dense can you get these (How many gates)? (2) Hiw much are they typically if you are buy small quantities 1-5 for prototyping? (3) Are they dense enough to build a CPU or a 3d VGA display chip with these? or maybe multiple chips. Thanks, -M. BazaillionArticle: 36248
Igor, Make sure you're using the latest version of Quartus II (ver 1.1, Service Pack 1) and Nios (ver 1.1.1). When you run the MegaWizard, one of your last choices (in the System Builder part, page 5 of 6) is to select which device family you are targeting. The current Quatus II software supports Nios in ACEX 1K, FLEX 10K/A/B/E, Apex 20K/E/C, Mercury, and the ARM Excalibur devices. You can also use MAX+Plus II for Nios in a ACEX or FLEX device, but Quartus is going to be a more friendly environment due to it's software mode and other features. Note that contrary to Carlhermann Schlehaus' comment, ACEX 1K and FLEX 10KE are fully supported in Quartus II ver 1.1. Here are the links to the latest service packs/updates: Quartus II v 1.1 SP 1: https://websupport.altera.com/dwl/ Nios ver 1.1.1 update: http://www.altera.com/products/devices/excalibur/exc-nios_devtkit.html (click on the "license agreement" link at the bottom of the page) BTW, there are several commercial products on the market today that have Nios running in an ACEX part. The design flow for ACEX is well supported. -Pete- ikauranen <ikauranen@netscape.net> wrote in message news:b0438406.0111021704.322d461e@posting.google.com... > Hello, > We have a problem implementing Altera NIOS soft core in ACEX 1K > device. It seems that the only target architecture is APEX 20KE. The > Verilog files generated by the Wizard contain some apex20ke_lcell, > which cannot be processed by Quartus II software when targeting > project to the ACEX devices. The Wizard performs only functional > tuning, not asking about preferred targed device. Oddly enough, Altera > reports ACEX and FLEX among supported architectures. > > Thank you. > IgorArticle: 36249
Hi Peter, "Peter Ormsby" <faepete.deletethis@mediaone.net> schrieb im Newsbeitrag news:uKYE7.23368$CN5.1699700@typhoon.mn.mediaone.net... ... > Note that contrary to Carlhermann Schlehaus' comment, ACEX 1K and FLEX 10KE > are fully supported in Quartus II ver 1.1. > Thanks for the hint, last time I tried to compile a "normal" design for ACEX with Quartus, the ACEX weren't available as target device. CU, Carlhermann
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z