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"Børge Strand" <borge.strand.remove.if.not.spamming@sintef.no> schrieb im Newsbeitrag news:1022230585.37631@halvan.trd.sintef.no... > I will need some really small FIFOs for my next project. The word length > will be 24 bits, but the depth of the FIFO is not requirred to be more than > two to sixteen. > > Could dedicated parts of the Spartan be used for such small FIFOs? I plan to > program the thing in VHDL. If this is for educational purpose, you can use the dual port capability of the Spartan LUTs. If it is "just" to solve a problem, use coregenerator to create the FIFO. But for Spartan (do you really mean Spartan, not Spartan-II?) this is only possible with Foundation 3.3 or older, since the synchronous FIFO for Spartan is missing in newer version of coregen (Xilinx is pushing its customers to leave the old parts by stoping to support them as usual) -- MfG FalkArticle: 43576
I have a customer who has off-loaded a small portion of a project to my company. Originally the project was to use a Virtex E part, but it got changed to Virtex along the way (not under my control). I've always used Altera products in the past; this is my first Xilinx project In the near future, I will have more capable tools to work with, but I was hoping to get a head start using WebPack. Unfortunately, Virtex is not one of the supported device families. I understand Spartan 2 bitstreams are compatible (yes, I've read Xilinx's positions on this). Here's the question: The Virtex part is in a 240 pin package, and the Spartan 2 line does not support this package. Can I target a Spartan 2 in 144 pin package, and load that bitstream into a 240 pin Virtex? Spartan 2 docs seem to show how pins for same chip in different packages correlate, but Virtex docs don't show this (or I've not found it). If the bitstream works, how do I match up pins between the 144 and 240 packages? Thank you. -- Kevin Hales Catalpa Technology, Inc. 302 E. Davis St. Ste 211 Culpeper, VA 22701 540-727-8005Article: 43577
For new designs, the Spartan-II or Spartan-IIE may be more cost effective. The CLB SelectRAM FIFO elements don't need to be in a single row so the smallest device in the families are the XC2S15 (8x12 CLB array) or the XC2S50E (16x24 CLB array) for the newer family. One 24 bit word, 2 to 16 words deep would require 24 *slices* or 12 CLBs using a DPRAM, the native SRL16 elements in the Spartan-II(E) series would only require half that. In either case you'll need a little extra logic (or pins) for address manipulation. Utku Ozcan wrote: > "Børge Strand" wrote: > > > I will need some really small FIFOs for my next project. The word length > > will be 24 bits, but the depth of the FIFO is not requirred to be more than > > two to sixteen. > > > > Could dedicated parts of the Spartan be used for such small FIFOs? I plan to > > program the thing in VHDL. > > > > Regards, > > Børge > > Let's calculate: > > your FIFO will use a DP RAM of 24 x 16 max. a DP RAM is composed of > 16x1 RAM16X1D.v primitives. Thus: > > NUM_OF_DPRAMS_OF_BORGE = (24 x 16) / (16 x 1) = 24 CLBs. > This gives you 24 CLBs laid horizontally on the chip. > > This DPRAM can be generated with Logiblox but your chip must be greater > than or equal to Xilinx Spartan/XL XCS30XL (24x24 CLB matrix). > > Otherwise, you have to divide your words into smaller words. > This is not bad, but uses twice routing resources the one above has. > More routing resources cause longer PAR times. > > I'm using a 32x8 FIFO on a Xilinx Spartan-XL XCS40XL-4-PQ208C. > > UtkuArticle: 43578
Sorry, my last link was for verilog sources try for vhdl one: http://www.latticesemi.com/account/_download.cfm?AMID=2886 Or use the search on http://www.latticesemi.com/ Laurent Gauch Amontec Laurent Gauch wrote: > Philippe, > > try this free HDL source of sdram controller: > http://www.latticesemi.com/account/_download.cfm?AMID=3866 > > Since I want to includ it on a spartanII in next months, could you give > me a feedback, if you use it. > > Laurent Gauch > > Philippe Robert wrote: > >> Hi, >> >> I am after an SDRAM controller in VHDL for Virtex-II. >> Does anyone know where I could get one from ? >> >> Thanks. >> Philippe. >> >> >> >Article: 43579
? = normal ?? = typo ??? = drunk ???? = stupidArticle: 43580
I notice that in the ISE4.2 Constraints Editor you can specifiy whether an input or output has a pull up or pull down on it. What is the default if you don't specify anything? I'm using an XCS10XL. Thanks, DaveArticle: 43581
That will be not very easy to write the same software to programm Xilinx and Altera FPGAs and Atmel AVRs. That's the job of www.jtag.com . Price about $30K for the jtag software, but I know why! Same hardware is possible using the universal POD called Chameleon POD http:\\www.amontec.com\chameleon.shtml Laurent Frank Scherler wrote: > Hello > > I am looking for a JTAG ICE. I don't wanne spend much money on it. > I want to be able to have a look on the schematics and to be able to > compile the software on my own. I am looking for hardware to programm > Xilinx and Altera FPGAs and Atmel AVRs with one Software and one > hardware. If it would be possible to debug software over JTAG with > this hardware it would be great. Dose anyone know any Project with > this topic? > > regards > Frank >Article: 43582
Some comments:
Przemyslaw Wegrzyn wrote:
> I use Xilinx ISE 4.1 (FPGA Express 3.6.1) + Active-HDL.
> Target chip: XC4003E
>
> 1. I/OPADS problem.
>
> Should I place PADS or PORTS next to I/OBUFs ? PADS are a little
> uncomfortable to me, as I can't use such entity for simulation,
> thus I use ports everywhere. I've tried to use FPGA Express option to
> inert I/O pads but it doesn't seem to work.
> Finally I've found similar option in the implementation tools ("Create
> I/O Pads from Ports"), and it works, but I'm not
> sure if it's a right solution.
Selecting the implementation option "Create I/O Pads from Ports" will
insert IPAD/OPAD primitves on your ports in the EDIF netlist. The FPGA
Express option "Insert I/O Pads" will insert both the IPAD/OPAD as well as
the IBUF/OBUF primitives except in certain cases when FPGA Express infers
a BUFG for the clock line. You will know when you have reached this
'special' condition when your design goes through the map portion of the
implementation tools as map will trim away everything associated with that
clock line. The reason is that FPGA Express is not inserting an IPAD/BUFG
combination (required for 4K). When the design then goes through
implementation map sees this portion of logic as being not connected.
FYI for Virtex devices you do not need IPADs/OPADs although they are valid
primitives for the part. Furthermore, the "Insert I/O Pads" option in
FPGA Express will only insert IBUF/OBUF type components.
>
>
> 2. How to use GSR ?
> I've placed STARTUP component on my toplevel schematic, connected IBUF
> and port to it, it seems to be ok -
> I can see these components connected together in FPGA Editor. But GSR
> option is disabled in STARTUP block :(
> I don't know what to do next. There's a net that sets/resets all the
> flipflops (I've checked it in post-synth EDIF netlist),
> but I don't know what to do with it - place IBUF/port on it ?
Excuse me if I am missing the question on this one as I do not know what
could be the problem. Here are some possible scenarios for using the
STARTUP block:
If the design is all HDL then having an asynchronous reset will let FPGA
Express automatically infer the STARTUP block.
If the design is all HDL with a black box core then an option needs to be
set to tell FPGA Express to ignore black boxes when connecting the STARTUP
block.
Connect your reset line to the output of the instantiated IBUF.
>
>
> 3. Clocks
>
> I use 2 clocks in my design, one external and OSC4 output. I pass the
> clocks through BUFGS.
> During implementation I get the following warning:
>
> Timing - Clock nets using non-dedicated resources were found in this
> design....
>
> Why ? Both clocks uses dedicated global nets !
A possbility would be a gated clock or a latch that got inferred. A quick
way to check the validity of the warning message is to examine your design
in FPGA Editor and follow the clock line.
>
>
> -=Czaj-nick=-
Steve
Article: 43583Hal Murray wrote: > > >Agreed, The raid is in the current system for reliability. I've suffered 3 > >or 4 disk failures over the years and the time spent recovering from backups > >is well worth the extra cost of having a raid system. > > Don't forget to back things up (somehow) anyway. RAID won't protect > you from software/mushware/operator errors. Just to add my two cents worth. I use a manual disk mirror approach for protection against HW, SW and "mushware" issues. The second HD is an exact duplicate of the first and is updated on a regular basis. We do this once a week, but the weak point in the system is the operator reliability. If I forget, I have lost some of my protection. By not having automatic duplication, we have some protection against accidentally deleted file and other issues from software installation and such. If we decide the backup is eaiser to work with than the messed up current drive, we swap the drives and copy the backup to the old original. This has saved us in some situations where a software crash wiped out a significant part of the OS, once when we were infected with a virus and many times when we did something to a file that we regretted. So RAID may not be the best option if you have the discipline to do your backups. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 43584
The default would be neither. "D Brown" <dbrown123@shaw.ca> wrote in message news:acln3d$917$1@pallas.novatel.ca... > I notice that in the ISE4.2 Constraints Editor you can specifiy whether an > input or output has a pull up or pull down on it. What is the default if you > don't specify anything? I'm using an XCS10XL. > Thanks, > Dave > > >Article: 43585
In article <3CEE74F0.1CC15C51@yahoo.com>, rickman <spamgoeshere4@yahoo.com> wrote: >Hal Murray wrote: >> >> >Agreed, The raid is in the current system for reliability. I've suffered 3 >> >or 4 disk failures over the years and the time spent recovering from backups >> >is well worth the extra cost of having a raid system. >> >> Don't forget to back things up (somehow) anyway. RAID won't protect >> you from software/mushware/operator errors. > >Just to add my two cents worth. I use a manual disk mirror approach for >protection against HW, SW and "mushware" issues. The second HD is an >exact duplicate of the first and is updated on a regular basis. We do >this once a week, but the weak point in the system is the operator >reliability. If I forget, I have lost some of my protection. > >By not having automatic duplication, we have some protection against >accidentally deleted file and other issues from software installation >and such. If we decide the backup is eaiser to work with than the >messed up current drive, we swap the drives and copy the backup to the >old original. > >This has saved us in some situations where a software crash wiped out a >significant part of the OS, once when we were infected with a virus and >many times when we did something to a file that we regretted. > >So RAID may not be the best option if you have the discipline to do your >backups. My 2 cents worth: Retrospect. It is a wonderful mac backup tool, doing both full and incremental backups, both on the machine and to other client machines over the network. My dad has had it save his bacon on his production mac system many times: he uses both a nightly incremental backup of everything and a nightly copying of critical files onto other drives. They finally have a Windows version as well, which if it works half as good as the Mac version, makes it worth its weight in gold. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 43586
I am building a card which will initially be used as a PCI 64/66 card and eventually as a PCI-X card (also 64/66). The card will use a Xilinx as the PCI/PCI-X interface. In the datasheet for the Xilinx "Real PCI-X" core there is a listing of the various modes in which the core can operate. PCI 64/33 is listed but PCI 64/66 is not. Am I correct to assume that if I place a device utilizing this core into a PCI bus running 64-bits wide at 66-MHz that it will not be able to run at 66 MHz? My interest in using the PCI-X core for my PCI 64/66 design is based on a desire to use the same core (and card) for both modes. According to the datasheets for the PCI-X and PCI 64/66 cores, both can operate on the XCV300E. Can both cores operate with the same pinout on this device? Until I buy either of them, it seems difficult to get information like this from the Xilinx website. Thanks. -GeorgeArticle: 43587
I currently do my backups onto a drive on another machine. The hard part is
remembering to do the copy. I don't trust one machine to hold the data
uncorrupted. I had a case a year or so ago where my raid card bellied up and took
out the data on the raid array. I am still concerned about a virus getting into the
network and wiping both, so I keep not-frequent-enough-backups of the accounting and
project files onto CDs. I've dabbled with tapes a couple of times, but frankly have
never had much success with them. I had attempted to use an IDE drive on my machine
which I did disk images too on a frequent basis, and intended to disable in the BIOS
except when doing the back-up. Good intention, but too inconvenient to keep it off
line.
Nicholas Weaver wrote:
> In article <3CEE74F0.1CC15C51@yahoo.com>,
> rickman <spamgoeshere4@yahoo.com> wrote:
> >Hal Murray wrote:
> >>
> >> >Agreed, The raid is in the current system for reliability. I've suffered 3
> >> >or 4 disk failures over the years and the time spent recovering from backups
> >> >is well worth the extra cost of having a raid system.
> >>
> >> Don't forget to back things up (somehow) anyway. RAID won't protect
> >> you from software/mushware/operator errors.
> >
> >Just to add my two cents worth. I use a manual disk mirror approach for
> >protection against HW, SW and "mushware" issues. The second HD is an
> >exact duplicate of the first and is updated on a regular basis. We do
> >this once a week, but the weak point in the system is the operator
> >reliability. If I forget, I have lost some of my protection.
> >
> >By not having automatic duplication, we have some protection against
> >accidentally deleted file and other issues from software installation
> >and such. If we decide the backup is eaiser to work with than the
> >messed up current drive, we swap the drives and copy the backup to the
> >old original.
> >
> >This has saved us in some situations where a software crash wiped out a
> >significant part of the OS, once when we were infected with a virus and
> >many times when we did something to a file that we regretted.
> >
> >So RAID may not be the best option if you have the discipline to do your
> >backups.
>
> My 2 cents worth:
>
> Retrospect. It is a wonderful mac backup tool, doing both full and
> incremental backups, both on the machine and to other client machines
> over the network. My dad has had it save his bacon on his production
> mac system many times: he uses both a nightly incremental backup of
> everything and a nightly copying of critical files onto other drives.
>
> They finally have a Windows version as well, which if it works half as
> good as the Mac version, makes it worth its weight in gold.
> --
> Nicholas C. Weaver nweaver@cs.berkeley.edu
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 43588Checking the Xilinx web site it looks like you can download IBIS models for various devices including the Spartan IIe devices. However, these files do you no good if you don't have IBIS simulator which seem to cost even more than a logic or HDL simulator. I also found that there are spice models available for the VirtexII parts. But not for any other devices. Since Spice is much more available, any idea why the Spice models are not available for parts other than the VII? -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 43589
What sort of frequency are you after???? Frank. Len Chisholm wrote: > Hi all, > > One of the Xilinx FPGA demo boards has a relaxation oscillator circuit > attached to a 3000 series FPGA, where there are external RC networks > attached to a pair of cross-coupled I/O blocks. > > Is there any reason why this would be a bad idea for a 9536XL ? The > datasheet says that there is 50mV hysteresis on the inputs in the XL > family but not the standard 9500s. I've cobbled a circuit together > which seems to run OK, but I'm looking for any gotchas which I've > overlooked. > > I need a not-particularly-accurate clock signal to run a state > machine, and if I can get an oscillator for 'free' then that's a good > thing. > > Thanks, > > Len Chisholm.Article: 43590
My coment is based on info from the AD 9854 data sheet. There is a short discussion of jitter from DDSs and PLLs. The PLL contributes some jitter to the final output, but is less than the jitter of a PLL by itself. I seem to recall an article from about 10 or more years ago that stated that no output from the phase accumulator would provide a good square wave. That is probably why AD connects the comparator to the filtered sinewave output of the DDS. Marty Ray Andraka <ray@andraka.com> wrote in message news:<3CEE572B.D07F18FC@andraka.com>... > Depends on the number of bits you use from the DDS. If you use the DDS to create > a sinewave, convert it to analog, filter it then use a comparator it can be better > than a PLL. If you just take the MSB to create a square wave, then your jitter is > up to a cycle of your master clock. > > Marty wrote: > > > Jitter from a DDS is lower than a PLL! > > > > Marty > > > > --Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com > > "They that give up essential liberty to obtain a little > temporary safety deserve neither liberty nor safety." > -Benjamin Franklin, 1759Article: 43591
I am working with Altera products since two years. I have my first project with Xilinx, now. We are going to use Virtex(-E) device. In order to get start to Xilinx, I need help with evaluation boards with Virtex-e. Actually, I am looking for the Xilinx counterparts of the following Altera boards, 1-) APEX PCI Development Kit (http://www.altera.com/products/devkits/altera/kit-apex_dev_kit.html) 2-) Altera SOPC board. Thanks in advance. -- Posted via Mailgate.ORG Server - http://www.Mailgate.ORGArticle: 43592
Hi Rick, your comments on ChipScope helped me a lot. I will go for it! Thanks for your help! Best Regards, Harris "Rick Filipkiewicz" <rick@algor.co.uk> wrote in message news:3CED84C8.E94491D3@algor.co.uk... > > > "H.L" wrote: > > > Hello all, > > I have read few weeks ago in xilinx site about the Chip Scope, seems like a > > good solution for testing a FPGA. I am thinking to purchase it but first I > > would like some comments about this tool from someone who have used it. Can > > someone help me on this? > > > > Greetings, > > Harris > > Very good tool and a steal @ $450 (well it saved my bacon a couple of months > ago so I may be biased). > > Some restrictions and caveats: > > o The GUI is pretty clanky but just about useable. For example there's no way > to reset the triggers(s) to all `X' after you've been using one of the trigger > types that doesn't support `X' values. > > o The s/w resident on the PC sometimes fails to connect to the ILA core through > the JTAG if there's some heavy compute process running in the background. The > symptom is the s/w complaining of an illegal version - I've seen v0.0 and > v15.0. > > o I've heard that MultiLinx USB is very flakey/fragile, use the Parallel-III/IV > JTAG cable instead. In fact knowing this is what held me back from using > Chipsope a while ago when V1.x didn't support Paralle-III. > > Things missing that you'd find in a real LA: > > o It requires a continuous sample clock of some description. i.e. you cannot > async sample some number of events, hit stop before the buffer's full, and > expect to see at least the events you captured. I got around this by creating a > sort of background sample clock that ticked if no real one had arrived for a > while. > > o There's no filter on pre-trigger events. In other words you can't say ``trig > on event E while storing <filtered subset of states>''. Again its possible to > get around this by designing some extra h/e to wrap around the ILA core but > changing the pre-filter condition => rebuilding the FPGA. > > Other than that its an verygood-to-excellent tool and works as advertised. If > Xilinx would fix up some of the points above it might even head into magic > class. >Article: 43593
"Børge Strand" <borge.strand.remove.if.not.spamming@sintef.no> skrev i meddelandet news:1022230585.37631@halvan.trd.sintef.no... > I will need some really small FIFOs for my next project. The word length > will be 24 bits, but the depth of the FIFO is not requirred to be more than > two to sixteen. > > Could dedicated parts of the Spartan be used for such small FIFOs? I plan to > program the thing in VHDL. > > Regards, > Børge > > This is an excellent application for the Atmel AT40K. For each 16 macroblocks, you have a small Dual Port RAM 32 x 4. The H/W Macrogenerator can be used to create a 32 x 24 FIFO. You will have 16 of the 32x4 DP SRAMs in the smallest 5 k gate FPGA, (Only 12 can be used as DPRAM though) If you need more than two FIFOs then there are larger FPGAs available. Maybe you could also use the FPSLIC which has an internal AVR processor. -- Best Regards Ulf at atmel dot com These comments are intended to be my own opinion and they may, or may not be shared by my employer, Atmel Sweden.Article: 43594
"Ray Andraka" <ray@andraka.com> skrev i meddelandet news:3CED5561.82DA8B37@andraka.com... > I agree, but then there is a limit to the amount of RAM that can go in a system, > and that is often greater than what the OS can use. I've got 2GB in my current > system: that frequently gets exceeded during synplicity's compile phase and Xilinx > PAR. As soon as paging starts, it slows to a crawl. > > hamish@cloud.net.au wrote: > > > Tyan S2468 will allow for 4 GB of SDRAM or wait for Hammer's w 64 bit addressing. -- Best Regards Ulf at atmel dot com These comments are intended to be my own opinion and they may, or may not be shared by my employer, Atmel Sweden.Article: 43595
Rick Filipkiewicz <rick@algor.co.uk> ha scritto: >that makes ASIC vendors dislike tristates So in ASIC data bus can not be realized? -- Per rispondermi via email sostituisci il risultato dell'operazione (in lettere) dall'indirizzo.Article: 43596
FWIW, both of those links are 'protected', and require an NDA with Lattice... On Fri, 24 May 2002 17:37:15 +0200, Laurent Gauch <laurent.gauch@amontec.com> wrote: >Sorry, my last link was for verilog sources > >try for vhdl one: >http://www.latticesemi.com/account/_download.cfm?AMID=2886 > >Or use the search on http://www.latticesemi.com/ > >Laurent Gauch >Amontec > >Laurent Gauch wrote: > >> Philippe, >> >> try this free HDL source of sdram controller: >> http://www.latticesemi.com/account/_download.cfm?AMID=3866 >> >> Since I want to includ it on a spartanII in next months, could you give >> me a feedback, if you use it. >> >> Laurent Gauch >> >> Philippe Robert wrote: >> >>> Hi, >>> >>> I am after an SDRAM controller in VHDL for Virtex-II. >>> Does anyone know where I could get one from ? >>> >>> Thanks. >>> Philippe. >>> >>> >>> >> >Article: 43597
The Xilinx app. note for sdr sdram controller on Virtex could be a good start; I also have to design a simple controller for Spartan II. http://www.xilinx.com/apps/xappsumm.htm#xapp134 "Philippe Robert" <PhilippeR@sundance.com> ha scritto nel messaggio news:3cee31f1$1@shiva.ukisp.net... > Hi, > > I am after an SDRAM controller in VHDL for Virtex-II. > Does anyone know where I could get one from ? > > Thanks. > Philippe. > >Article: 43598
From archived postings to comp.arch.fpga I've figured out that some documentation is available at $XILINX/help/data/xdl/xdl.html. Unfortunately the BNF included there only covers converted designs and not XDL reports (c.f. "xdl -report virtex2 xc2v40"). Can anybody suggest any pointers?Article: 43599
Jeff Mock wrote: > > For me the linux environment is great. I don't use any of > the Xilinx GUI tools, just the command line tools. By the way, in case you (or someone) are interested in running fpga_editor under wine, here is a patch that cleans up most of the remaining wine bugs that affect it. It is against the recent CVS version of wine, and I will attempt to keep it up to date. http://www.leewardfpga.com/fpga.diff Stick that in the wine top level directory, and execute: patch -p0 < fpga.diff I run quite a few programs under wine, and it does not appear to harm any of them (some run better). But as always, my warranty only extends to the price you paid for the patch :-) -- My real email is akamail.com@dclark (or something like that).
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