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Didn't they fix that with 2000? If I remember correctly, 2000 is the update to NT, right? They made PCMCIA and USB work correctly, no? Ray Andraka wrote: > > Even the PCMCIA stuff doesn't do too well under NT. > > rickman wrote: > > > Instead of disabling it in the BIOS, why not make it removable with a > > slide in cartdrige or use a PCMCIA adapter? I guess with the slide in > > cartdrige you still have to take it out of the BIOS unless they provide > > software to automatically do that as with the the PCMCIA interfaces. > > > > Ray Andraka wrote: > > > > > > I currently do my backups onto a drive on another machine. The hard part is > > > remembering to do the copy. I don't trust one machine to hold the data > > > uncorrupted. I had a case a year or so ago where my raid card bellied up and took > > > out the data on the raid array. I am still concerned about a virus getting into the > > > network and wiping both, so I keep not-frequent-enough-backups of the accounting and > > > project files onto CDs. I've dabbled with tapes a couple of times, but frankly have > > > never had much success with them. I had attempted to use an IDE drive on my machine > > > which I did disk images too on a frequent basis, and intended to disable in the BIOS > > > except when doing the back-up. Good intention, but too inconvenient to keep it off > > > line. > > > > > > Nicholas Weaver wrote: > > > > > > > In article <3CEE74F0.1CC15C51@yahoo.com>, > > > > rickman <spamgoeshere4@yahoo.com> wrote: > > > > >Hal Murray wrote: > > > > >> > > > > >> >Agreed, The raid is in the current system for reliability. I've suffered 3 > > > > >> >or 4 disk failures over the years and the time spent recovering from backups > > > > >> >is well worth the extra cost of having a raid system. > > > > >> > > > > >> Don't forget to back things up (somehow) anyway. RAID won't protect > > > > >> you from software/mushware/operator errors. > > > > > > > > > >Just to add my two cents worth. I use a manual disk mirror approach for > > > > >protection against HW, SW and "mushware" issues. The second HD is an > > > > >exact duplicate of the first and is updated on a regular basis. We do > > > > >this once a week, but the weak point in the system is the operator > > > > >reliability. If I forget, I have lost some of my protection. > > > > > > > > > >By not having automatic duplication, we have some protection against > > > > >accidentally deleted file and other issues from software installation > > > > >and such. If we decide the backup is eaiser to work with than the > > > > >messed up current drive, we swap the drives and copy the backup to the > > > > >old original. > > > > > > > > > >This has saved us in some situations where a software crash wiped out a > > > > >significant part of the OS, once when we were infected with a virus and > > > > >many times when we did something to a file that we regretted. > > > > > > > > > >So RAID may not be the best option if you have the discipline to do your > > > > >backups. > > > > > > > > My 2 cents worth: > > > > > > > > Retrospect. It is a wonderful mac backup tool, doing both full and > > > > incremental backups, both on the machine and to other client machines > > > > over the network. My dad has had it save his bacon on his production > > > > mac system many times: he uses both a nightly incremental backup of > > > > everything and a nightly copying of critical files onto other drives. > > > > > > > > They finally have a Windows version as well, which if it works half as > > > > good as the Mac version, makes it worth its weight in gold. > > > > -- > > > > Nicholas C. Weaver nweaver@cs.berkeley.edu > > > > > > -- > > > --Ray Andraka, P.E. > > > President, the Andraka Consulting Group, Inc. > > > 401/884-7930 Fax 401/884-7950 > > > email ray@andraka.com > > > http://www.andraka.com > > > > > > "They that give up essential liberty to obtain a little > > > temporary safety deserve neither liberty nor safety." > > > -Benjamin Franklin, 1759 > > > > -- > > > > Rick "rickman" Collins > > > > rick.collins@XYarius.com > > Ignore the reply address. To email me use the above address with the XY > > removed. > > > > Arius - A Signal Processing Solutions Company > > Specializing in DSP and FPGA design URL http://www.arius.com > > 4 King Ave 301-682-7772 Voice > > Frederick, MD 21701-3110 301-682-7666 FAX > > -- > --Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com > > "They that give up essential liberty to obtain a little > temporary safety deserve neither liberty nor safety." > -Benjamin Franklin, 1759 -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 43776
Janusz Raniszewski wrote: > > Hi, > > > There may also be soft core starting points for this, plus you > > have reference silicon to compare with :-), and the option of a > > hard core, with FLASH, which is likely to be more ecconomical > > than a soft core. > > > > -jg > > I think in prototypes or small production the soft core is more economical why? > - Is possibly unification of the device hardware and change it by soft > - At first point reduce cost of the board design and manufacturing > - Reduce of the around processor chips obtain cost > - Is possibly to design a new commands or hardware processor > - Project of the board is more simplicity because all chips around processor are > in FPGA structure > - FPGA chips have more pins than typical hardware processor. It provides to ease > design of device. > - Start to work a new device is quickly > - Is possibly to design a new architecture of device e.g. delta-sigma DAC > converter which in traditional > technique require many chips or hard (not flexibility) solution by hard core DAC > chips > - Generally soft core grows freedom of the desing process and reduces cost of the > activate a new device > > One disadvantage is difficulty to protect of the project copy. > > JanuszR You mention cost as two of the reasons for using a soft CPU, but I think you will find that the cost of a CPU includes a lot of peripherals that are not digital in nature and therefore have to be added back to an FPGA implementation. The clock is one, power on reset, ADC/DAC and analog comparators are others. Flash and large RAM are other things missing from FPGAs, they have a few kBytes in the small ones at best. The large ones cost big, big $$$. By the time you have added back the missing functions, you will likely have added more $$ and size than you would have saved with the single MCU and a smaller FPGA. Of course some of the other issues you have raised are not mitigated by the MCU. Adding commands is the only one that especially seems to stand out however. The idea that a soft core makes the design process easier is not expecially valid. Just the fact that you need to design a new C compiler seems to make this harder. Until the new compiler has been worked enough to fully debug, it will be a major liability. The idea that an FPGA has more pins is not valid if you combine an MCU with an FPGA of a size that matches the task. Keeping them separate helps to match the hardware to the task. If I use a soft CPU I may need to buy a huge FPGA to get enough RAM for my task while only needing a small amount of logic. Starting a design more quickly is a feature of using an MCU. I can start writing and testing code as soon as I have hardware while an FPGA design is still messing with P&R. I can then integrate my FPGA design once I have the basice MCU working. I can even use the MCU as a debug tool for the FPGA. So unless you have a unique design that needs little RAM and nearly no analog functions, you will do well to use one of the many MCUs on the market. They have been designed for tight integration of perpherals and cost effective deployment. They are hard to beat. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 43777
Prager Roman <rprager@frequentis.com> ha scritto: >> It is a reconfigurable processor for high performance embedded system: >> something similar (but better) to Nios: it has a built in FGPA... so >> it's FPGA^2 !! (actual, on Altera I've implemented a smaller version of >> the FPGA than the one on the sylicon version). > >I am not sure what for this is supposed to be useful ? > Why do you want >to split up the FPGA? Well, the reconfigurable processor is going to be realized on sylicon chip and it also include a functional unit that is a full custom FPGA array. What we want to do is also to try synthetize on FPGA a symplified version of the processor using the same HDL code: just a prototype. So, due to the fact that the original processor includes a built in custom FPGA, my prototype version has to include the custom FPGA on the Altera FPGA... FPGA^2 as i said. >You can use the NIOS to write the new image. There should be a description >in the Nios documentation how to write such a routine, or maybe there is >already some example included. Thanx, I'm gonna search now. Bye! -- To reply via email please write the correct sum (in letters) in the email address.Article: 43778
jetmarc wrote: > > Hi. I'm prototyping a new design with AT40K FPGA and > CompactFlash memory card. The CompactFlash is being > talked to in the "common memory mode", meaning that > the data is not addressed with ADDRx lines but read by > consecutive read cycles to one single address. > > The CompactFlash card has an internal address pointer > that increments after each read cycle. > > My circuit doesn't work. After reading 512 bytes I > find that some are missing, and the buffer is padded > with dummy bytes. > > Obviously the CompactFlash card has taken a few of > the read cycles for two (double-clocked on the falling > /OE edge), so that its internal address has reached > the end while my FPGA was still reading more data. > > I spent hours already, trying to remove this problem. > But no avail. I tried all software options that the > AT40K gives (io pin slew rate, pullup/pulldown). I > added external RC filters on the /OE, /CS, /WE pins > (making the problem worse). I inserted schmitt trigger > '244 bus drivers in the signal path. > > On the scope, the signals look OK, but it is only a > 5ns/200MHz model. > > The problem only occurs when there is a lot of change > on the 8bit data bus. Reading a sector with all 0x00 > or all 0xff is possible (without errors). The data > signals are far away from the clock signals (/OE, /CS, > /WE) both on the (short) cable and the FPGA pinout. > > The same card (with same cable) has previously worked > fine on another prototype. That prototype used 5.0v > (while the new one uses 3.3V) and connected the CF card > to an ATmega microcontroller (while the new one has an > AT40K FPGA). > > I believe that the AT40K IO pin driver generates noisy > signals, at least more noisy than the ATmega. I don't > know how to fix that. Schmitt trigger buffers didn't help. > > Do you have an idea what I can try to fix it? > > Marc There are two directions to manage, and thus two driving sources. If the problems are on read, the FPGA is mostly passive, and the FLASH is driving the DBus. Check carefully also on write, where the FPGA drives, and FLASH listens. Also, check just when the loss of read-sync occurs. If the flash clocks on the same edge that de-Tristates the bus, then that is going to be prone to ground bounce problems, mainly in the connections between card and FPGA. -jgArticle: 43780
Hi All:) Can anyone tell me how i can get the B5 Spartan 2 board(http://www.burched.com.au/B5Spartan2.html)to communicate with a 68HC11 motorola EVB11 board that is to say what would be needed to interface the two so that they can communicate to each other Thanx:) Harkirat harkirat@joymail.comArticle: 43782
Thanks for your help. The problem is solved now, by shortening the track length, improving bypassing, adding series resistance in the data lines to reduce ground bounce, and by matching the clocks to the line impedance. I didn't know that CF cards can be so picky.Article: 43783
Main reason is just that you have the mapped output without going through the
Xilinx tools too. A functional sim using the timing output is about the same
simulation time from what I have seen (I don't often go either place).
Allan Herriman wrote:
> On Sat, 1 Jun 2002 17:18:03 +0000 (UTC), nweaver@CSUA.Berkeley.EDU
> (Nicholas Weaver) wrote:
>
> >In article <3cf8fc35.13519329@netnews.agilent.com>,
> >Allan Herriman <allan_herriman.hates.spam@agilent.com> wrote:
> >>>Ray Andraka proposed to do post-mapping simulation to veryfy the sythesis
> >>>result, since a post-maping is (much?) faster than post P&R.
> >>
> >>Why is it faster? The simprim blocks take most of the simulation
> >>time, and these will be the same post map and post PAR.
> >>(Note that you *don't* have to load the SDF if you are doing a post
> >>PAR functional simulation.)
> >
> >I think because you end up ignoring all the timing info (which ends up
> >being pretty substantial post-routing.
>
> I thought it was possible to ignore all timing in the post-PAR VHDL.
> You don't have to load the SDF and (in Modelsim) you can use the
> +notimingchecks command line option to turn off the VITAL timing.
>
> I haven't ever done a post-map sim to know if there's a difference or
> not. Does anyone have any quantitative results?
>
> Allan.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 43784Thank u all for ur valuable feedback. To sum up: >>"Engineering Sample" usually refers to chips that are not yet >>in production. They might have logic bugs or timing quirks. >>Usually the people who want them are happy to pay for them. >>They are often scarce. If so they get sold/issued to people >>who can provide the best feedback about how well they work. >>(or the big customers who need them or ...) if distributors/FAEs/X/A feel that i can bring them good volumes in the future they 'may' ship me Engg. samples or even small chips for free. but otherwise they are more expensive ( and may come with limited functionality like less number of working DLLs etc. ) than chips which are in volume production. so it only makes sense to go in for ESes if 'time to market' is an issue. regards rajatArticle: 43785
Hi,
I'm experimenting with some pipeline architectures to speed up some of
my designs. I'm targetting a Virtex 300K (speed grade 4) using XST
under ISE4.2i.
For a test, I created a 4 stage pipeline that does nothing, just passes
data from the inputs, through 4 registers, then off to the outputs, all
synched on a common clock. There is also a ready output that goes high
once the pipeline is full, which would be used like a clock enable
signal for a downstream module.
I synthesised targetting maximum speed, and am doing post-P&R sims to
see just how fast I could clock this thing. What I found is that at low
clock speeds (<20 MHz), it behaves as expected. However, if I sim it
at, say, 50MHz, there's no output for the first 10 cycles then all of a
sudden it starts working, with the appropriate delay. This is rather
disconcerting, I would have thought either it works or it doesn't. The
core VHDL code is attached - any tips appreciated. Also, any
recommended resources (online or print) for learning the nitty gritty of
pipelined architecture design?
Cheers,
John
entity pipeline is
Port (clk : in std_logic;
reset : in std_logic;
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
rdy : out std_logic);
end pipeline;
architecture Behavioral of pipeline is
signal r1,r1_next : std_logic_vector(7 downto 0);
signal r2,r2_next : std_logic_vector(7 downto 0);
signal r3,r3_next : std_logic_vector(7 downto 0);
signal r4,r4_next : std_logic_vector(7 downto 0);
signal counter,counter_next: integer range 0 to 5;
begin
-- connections between registers
r2_next <= r1;
r3_next <= r2;
r4_next <= r3;
-- register process
process(clk,reset)
begin
if(reset='1') then
r1 <= (others => '0');
r2 <= (others => '0');
r3 <= (others => '0');
data_out <= (others => '0');
elsif(clk'event and clk='1') then
r1 <= data_in;
r2 <= r2_next;
r3 <= r3_next;
data_out <= r4_next;
end if;
end process;
-- counter update process
process(clk,reset)
begin
if(reset='1') then
counter <= 0;
elsif(clk'event and clk='1') then
if(counter<3) then
counter <= counter+1;
rdy <= '0';
else
counter <= 3;
rdy <= '1';
end if;
end if;
end process;
end Behavioral;
Article: 43786I wrote: > However, if I sim it > at, say, 50MHz, there's no output for the first 10 cycles then all of a > sudden it starts working, with the appropriate delay. I should also note that my output "rdy" signal, driven by a counter, also behaves in this strange way, staying low for 10 cycles then going high. It's as if my design is somehow "missing" clock ticks. Rgds, JohnArticle: 43787
It's not in English, I don't understand it! Also, I live in the U.S and would prefer to order something within the U.S. "Johann Glaser" <Johann.Glaser@gmx.at> wrote in message news:adcltu$10cemk$1@ID-115042.news.dfncis.de... > Hi! > > Look at the CESYS X2S_USB Board at > http://www.cesys.de/ > They use a Cypress EZ-USB chip for USB communication. > > If you need Linux download drivers visit > https://sourceforge.net/projects/x2susbsfwkit/ (which is actually not > usefull) or contact me for the files. > > Bye > HansiArticle: 43788
"Kyle Davis" <kyledavis@nowhere.com> > I am looking for FPGA board that use USB port or IEEE 1394 (Firewire) for > downloading to the chip. Kyle, we just introduced our new FPGA development board which is especially well suited for FPGA-centric processing applications. The board is based upon a 300k-gate Spartan-IIE, which is accompanied by the following peripherals: - 256kx16 SRAM - 512kx16 Flash - 2x16 LC-display - USB interface - RS232 interface - VGA output - VG96 connector For a convenient desktop or laboratory setup, the board is powered and configured via USB. The Flash memory is used to store non-volatile configurations and data. The board fits into industry-standard 19" racks with VG96 connector. For easy expansion, there are up to 100 user I/Os with may be assigned freely. For further information, refer to the following links: http://www.trenz-electronic.de/prod/proden12.htm http://www.trenz-electronic.de/prod/proden10.htm http://www.trenz-electronic.de/prod/ps-TE-XC2Se.pdf The board is in stock and may be ordered via our online shop. We offer discounts for orders of two or more boards. Contact us! Best regards Felix _____ Dipl.-Ing. Felix Bertram Trenz Electronic GmbH Brendel 20 D - 32257 Buende Tel.: +49 (0) 5223 4939755 Fax.: +49 (0) 5223 48945 Mailto:f.bertram@trenz-electronic.de http://www.trenz-electronic.deArticle: 43789
John, from the symptoms, I would suspect hold time problems in your test-bench. At 50MHz, you should not be having trouble with a shift register in Virtex. If you are registering data in your testbench, then you need to pay attention to the clock relationship of the clock that you provide in the testbench, and the clock in the simulation model in the chip. The post synthesis model will include at least a pad, and bufg delay, each 100ps. The post layout model will add routing delays. Try clocking the data in the test bench that feeds the FPGA with a clock 200ps behind the clock supplied to the FPGA. This will restore hold time to the data. Regards, "John Williams" <j2.williams@qut.edu.au> wrote in message news:3CFB0167.C3CF2E15@qut.edu.au... > Hi, > > I'm experimenting with some pipeline architectures to speed up some of > my designs. I'm targetting a Virtex 300K (speed grade 4) using XST > under ISE4.2i. > > For a test, I created a 4 stage pipeline that does nothing, just passes > data from the inputs, through 4 registers, then off to the outputs, all > synched on a common clock. There is also a ready output that goes high > once the pipeline is full, which would be used like a clock enable > signal for a downstream module. > > I synthesised targetting maximum speed, and am doing post-P&R sims to > see just how fast I could clock this thing. What I found is that at low > clock speeds (<20 MHz), it behaves as expected. However, if I sim it > at, say, 50MHz, there's no output for the first 10 cycles then all of a > sudden it starts working, with the appropriate delay. This is rather > disconcerting, I would have thought either it works or it doesn't. The > core VHDL code is attached - any tips appreciated. Also, any > recommended resources (online or print) for learning the nitty gritty of > pipelined architecture design? > > Cheers, > > John > > entity pipeline is > Port (clk : in std_logic; > reset : in std_logic; > data_in : in std_logic_vector(7 downto 0); > data_out : out std_logic_vector(7 downto 0); > rdy : out std_logic); > end pipeline; > > architecture Behavioral of pipeline is > > signal r1,r1_next : std_logic_vector(7 downto 0); > signal r2,r2_next : std_logic_vector(7 downto 0); > signal r3,r3_next : std_logic_vector(7 downto 0); > signal r4,r4_next : std_logic_vector(7 downto 0); > > signal counter,counter_next: integer range 0 to 5; > > begin > > -- connections between registers > r2_next <= r1; > r3_next <= r2; > r4_next <= r3; > > -- register process > process(clk,reset) > begin > if(reset='1') then > r1 <= (others => '0'); > r2 <= (others => '0'); > r3 <= (others => '0'); > data_out <= (others => '0'); > elsif(clk'event and clk='1') then > r1 <= data_in; > r2 <= r2_next; > r3 <= r3_next; > data_out <= r4_next; > end if; > end process; > > -- counter update process > process(clk,reset) > begin > if(reset='1') then > counter <= 0; > elsif(clk'event and clk='1') then > if(counter<3) then > counter <= counter+1; > rdy <= '0'; > else > counter <= 3; > rdy <= '1'; > end if; > end if; > end process; > > end Behavioral;Article: 43790
Hi all Does anybody know of a FPGA evaluation board with ethernet communication that allows downloading the bitstream via FTP connection? Thanx ThomasArticle: 43791
> Starting a design more quickly is a feature of using an MCU. I can > start writing and testing code as soon as I have hardware while an FPGA > design is still messing with P&R. I can then integrate my FPGA design > once I have the basice MCU working. I can even use the MCU as a debug > tool for the FPGA. > > So unless you have a unique design that needs little RAM and nearly no > analog functions, you will do well to use one of the many MCUs on the > market. They have been designed for tight integration of perpherals and > cost effective deployment. They are hard to beat. But, when you develop one device, after a month you must develop other device, you can use the same board with the same uC (I assume that you invest some time and/or money to make own board with CPU-able FPGA with at least flash, ram and reset). My work is (generally) developing controlling systems which are producted in small quantities & I save much, much time by making ONE uC board for almost all designs (it's small, about 6x6cm). This is the point, where savings can be done. I know, I could make a board with uC and FPGA, but it still needs more than one piece of silicon. It's simpler to keep all the logic in one reconfigurable device (when I made the board, I've forgotten where is my soldering tool ;)) I solder i Quartus ;)) jerryArticle: 43792
> > My application is an audio oversampler. I parallelize the design to the > point where I can have 3 or 4 MAC units working in parallel. Each MAC has a > coefficient ROM and a data RAM. The FIFOs are just there to pass data > between MACs working in parallel. The RAM cells don't need to be awfully > large, 256 words of 24 bits is likely to be the largest one. The smallest is > probably around 16 words of 24 bits. And yes, there are 24x24 or 24x20 bit > MACs in there. > > I plan to put this in a Spartan or Spartan IIE. I'll need a lot of logic, it > seems, but with just a few DAC chips using series data, the IO need is > actually minimal. The reason I wrote Spartan instead of SpartanII is that > I'm a little afraid of BGA mounting. That's one thing I can't do with my SMD > iron and microscope. > > Regards, > Børge > I doubt it will fit into a Spartan, since the Spartan has no Block RAM. At least not according to my datasheet. Without BlockRAM You are using half an XCS40 just for the 256 x 24 FIFO. (Each CLB = 16 x 1 DPRAM, needs 16 x 24 CLBs = 384 CLBs, XCS40 = 784 CLBs) -- Best Regards Ulf at atmel dot com These comments are intended to be my own opinion and they may, or may not be shared by my employer, Atmel Sweden.Article: 43793
Hi, I have problems instantiating a dual-port RAM in Verilog. I have generated the VEO file but I am not so sure how to apply this on my module. Does anybody have a sample file on instantiating cores in verilog? Thanks, Chy Talles cpt2002@post.comArticle: 43794
Hello We have here a licence of Synario 7.1 and the corresponding installation CD. We downloaded a service pack to include functionallity for the chip ispLSI 5384 VA 100 lq 208 some time (years...) ago, but unfortunately that installation file got lost somehow. So we have here the Synario 7.1 software but not the service pack for this additional chip . We have old designs which do contain that chip, and we are in need to reinstall the software after a PC crash. Note we definitly do not want to switch to a newer version because we already had some trouble with newer Synario version- Can anybody provide us with a link to download that service pack for Synario 7.1 ? It is not on the latticesemi.com webpage anymore and their tech support seems to be unable to help--- I highly appreciate any help on this. Thank you Ralf Stiehler University of Siegen, GermanyArticle: 43795
Hello! Is it possible to kill (thermically destroy) an FPGA by a highly optimized design (hand-placed; high-density; litte unrelated logic) assuming that interface lines are OK/room temperature? Did anybody observe such a behavior? Regards MichaelArticle: 43796
Michael Boehnel <boehnel@iti.tu-graz.ac.at> wrote: > Hello! > Is it possible to kill (thermically destroy) an FPGA by a highly > optimized design (hand-placed; high-density; litte unrelated logic) > assuming that interface lines are OK/room temperature? Of course it is possible, at least with higher integrated FPGAs. Modern FPGAs can easily integrate the switching power for a few Gigabit per second, even if not 'highly optimized'. So the definitely need some cooling. Without cooling they go the same way like any other highspeed processor. Roman > Did anybody observe such a behavior? > Regards > MichaelArticle: 43797
On Mon, 03 Jun 2002 02:46:57 GMT, Ray Andraka <ray@andraka.com> wrote: >Main reason is just that you have the mapped output without going through the >Xilinx tools too. A functional sim using the timing output is about the same >simulation time from what I have seen (I don't often go either place). Thanks Ray, I thought they'd be about the same speed. Our standard build scripts generate the post-PAR VHDL, so that's why I've only ever used that. Regards, Allan. >Allan Herriman wrote: > >> On Sat, 1 Jun 2002 17:18:03 +0000 (UTC), nweaver@CSUA.Berkeley.EDU >> (Nicholas Weaver) wrote: >> >> >In article <3cf8fc35.13519329@netnews.agilent.com>, >> >Allan Herriman <allan_herriman.hates.spam@agilent.com> wrote: >> >>>Ray Andraka proposed to do post-mapping simulation to veryfy the sythesis >> >>>result, since a post-maping is (much?) faster than post P&R. >> >> >> >>Why is it faster? The simprim blocks take most of the simulation >> >>time, and these will be the same post map and post PAR. >> >>(Note that you *don't* have to load the SDF if you are doing a post >> >>PAR functional simulation.) >> > >> >I think because you end up ignoring all the timing info (which ends up >> >being pretty substantial post-routing. >> >> I thought it was possible to ignore all timing in the post-PAR VHDL. >> You don't have to load the SDF and (in Modelsim) you can use the >> +notimingchecks command line option to turn off the VITAL timing. >> >> I haven't ever done a post-map sim to know if there's a difference or >> not. Does anyone have any quantitative results? >> >> Allan. > >-- >--Ray Andraka, P.E. >President, the Andraka Consulting Group, Inc. >401/884-7930 Fax 401/884-7950 >email ray@andraka.com >http://www.andraka.com > > "They that give up essential liberty to obtain a little > temporary safety deserve neither liberty nor safety." > -Benjamin Franklin, 1759 > >Article: 43798
This is a multi-part message in MIME format. --------------AF4051BC65B423E6DBA161BB Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit The Xilinx VHDL timing netlists have a global set/reset signal that is defaultly held for 100 ns. That means for the first 100 ns, the entire design is held in a reset state and therefore does not do anything. Hold off inputing data (you can continue running the clock, just no data) until at least 100 ns and I'll bet it will work as you expect. Take a look at the Syntheiss and Simulation Design Guide document for more information on Xilinx simulation. -- Brian John Williams wrote: > I wrote: > > However, if I sim it > > at, say, 50MHz, there's no output for the first 10 cycles then all of a > > sudden it starts working, with the appropriate delay. > > I should also note that my output "rdy" signal, driven by a counter, > also behaves in this strange way, staying low for 10 cycles then going > high. > > It's as if my design is somehow "missing" clock ticks. > > Rgds, > > JohnArticle: 43799
does anyone know of an elegant way to divide a number of 21 bits by 5 ? please note that I'm using xilinx's virtex 2 and mentor's leonardo for synthesys.
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