Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Mitchell, See below, Austin Mitchell Crago wrote: > I need to develop a High-Speed buffer (1Gbps line speed) system using a > Xilinx FPGA - currently I am looking at the Virtex-II family. > > The Max CLKIN/CLKOUT for a -5 grade chip is 420MHz. > > Q1. Is it possible to achieve 1Gbps on a serial input for this device? > I have a feeling I cant - is this good hunch? 420 MHz, 840 Mbs is the data sheet limit. Fastest speed grade parts have been shown to perform at 1 Gbs DDR in the lab, but one would have to re-qualify the device and test for this application, which would not be economical or practical. > > > Q2. What would be the max IO datarate achievable? 840Mbps using DDR? Yes. > > > Q3. Is there a Xilinx FPGA capable of such serial datarates? Virtex II Pro, up to 3.125 Gbs with the multiple serdes cores (RocketIO(tm)). > > > Sorry for the scattered question, but I'm fed up with trolling through > datasheets http://www.xilinx.com/xlnx/xil_prodcat_landingpage.jsp?title=Virtex-II+Pro+FPGAs > > > Thanks in advance for any help, > > Mitchell Crago > mmccrraaggoo@@ffllooww.ccoomm.aauu > __________________________________________________________________Article: 43501
Having been playing around and designing for the past couple months, it is only now that I need to download my design onto a PROM. Could anyone point me to a reference which will tell me how the whole loading off PROM thing works, and if I need to make design modifications etc. etc. thanks adrianArticle: 43502
Hi! > I've had no problems so far with a dual Athlon 2GHz with a 1Gb of RAM - > running quartus 2, ActiveHDL, Leonardo with Apex 20KE 600 devices. Also > has a normal IDE hard disk system (with RAID set to mirror for backup) > which is not noticibly slower than my previous much more expensive fast > SCSI system. Also consider a server with shared directories for every employee. Then you can make centralized backup. Lets say a monday-tape, a tuesday-tape, ... sunday-tape (if you sometimes work on weekend). These tapes are reused the following week. Perhaps use CD-RW instead, if the amount of data is not too much. And once every week or every month you backup to a tape which is stored in a safe or at a more secure place. You should then buy a really fast server with good HDD (SCSI with RAID 4 or better RAID 5), lots of RAM (several GB) for cache and a thick network connection in your office. Use a Linux box with Samba running. Windows is only able to use it's own SMB network, although it is quite bad designed :-( so you have to offer it with the server. BTW: I heard that somebody replaced 5 WinNT4 Servers by one Linux server with Samba and the performance increased. :-) This is a one time investment, and all following employee workstations will get cheaper because you don't need SCSI, RAID, ... there. But I don't know if you have some reasons keeping files local. Bye HansiArticle: 43503
"stefaan vanheesbeke" wrote > I every time want to make my own processor, with the best things of all the > previous mentioned systems, and I always stuck on the C (c++) compiler port. ... > I thought on porting smaller compilers before (lcc), but I need the c++ > support. 1. I describe how I ported lcc to target my FPGA CPUs in the Circuit Cellar article series at www.fpgacpu.org/xsoc/cc.html and see also www.fpgacpu.org/usenet/lcc.html. That won't get you C++ support though. 2. The only retargetable open source C++ compiler I am aware of is GCC and that is a much larger code base than lcc, and (I believe) much more work to port, and to maintain your port; but it has been done. See OpenRISC, Nios, MicroBlaze. 3. If you implement an instruction set architecture that GCC already targets, you're golden. See LEON SPARC. 4. Alternately you can build GCC for an existing target, and write a binary translator (compile time or run time) that translates the target ISA into your FPGA CPU ISA. 5. Another approach is to use Comeau C++, based upon Edison Design Group's superb retargetable C++ front end. That emits C that you *might* be able to compile with lcc. See http://www.comeaucomputing.com/. Jan Gray, Gray Research LLCArticle: 43504
Mitchell, For fast configuration, one uses the 8 bit parallel modes, with clocks up to 66 MHz. 1697184 bits, or ~207Kbytes, is a little more than 3 milliseconds to configure (at 66 MHz). See Chapter 3 in the Virtex II Handbook, and the Datasheet. Austin Mitchell Crago wrote: > Ooops, must be time for a break - config is at 1uS per bit -> 1.7secs, damn > I'm a goose sometimes. > > "Mitchell Crago" <mcrago@flow.com.au> wrote in message > news:acfmta$kgu$1@lust.ihug.co.nz... > > I am using a XC2V250 for a project, and I'm trying to work out the > expected > > configuration times. The only reference I have found to allow around 1mS > per > > bit of the configuration stream. If this is true, it will take me around > 28 > > minutes to configure the device. Is this true? If not, how long would one > > expect to load a design? > > > > Cheers > > > > Mitchell > > mmccrraaggoo@@ffllooww.ccoomm.aauu > > __________________________________________________________________ > > > >Article: 43505
People have been providing Linux Benchmarks,and the PIII-1200 has been doing just fine there compared to the P4 at higher MHz. Athlon MP's are known to have a lot of problems. They are generally solvable, but you need to talk to people with experience that has built machines before. Check out "alt.comp.periphs.mainboard.tyan" and similar newsgroups. Problems have been around power supply (NMB does not work!), not selecting "approved" memory. GeForce 3/4 drivers (You need a registry fix). COOLING!!!! Myself building a new Home PC: Tyan S2462UNGM Motherboard (2 x 10/100, 2 x U160,VGA/4 MB, 4 x USB) 2 x 1800+ Athlon MP 512 MB SDRAM Corsair Registred Enhance-0246/24 Power Supply, small, dual fan but not soo quiet as I thought. Geforce4 Ti 4400 73GB U160 80 GB UIDE-100 Soundblaster Audigy Player (which also has issues with driver) DVD200i. Pinnacle DC1000 Waiting for a Lian-Li PC71 Aluminium box. Plenty of fans. I got the S2462 since I need a lot of expandability. - Already filled all slots. The S2468 is the next generation supporting 4 GB memory and 66 MHz PCI. Has had a few crashes, yesterday it became intolerable (crash 1 minute after booting windows ALWAYS!!!) this was identified to be the lack of the GeForce registry fix. Worked much better aftewards. Spent most of last night, trying to rebuild... and I hope to get it working today. Will try to run Modelsim afterwards to check performance... In short, get a working machine from someone with experience, or you spend a lot of time debugging incompatabilites. Then create an image (Driveimage) so you can get running again quickly. Tyan are supposedly built for "reliability" so they have some conservative memory timings. It is expensive since it needs a special power supply/box. There are some others on the market which are a little bit faster I have heard. -- Best Regards Ulf at atmel dot com These comments are intended to be my own opinion and they may, or may not be shared by my employer, Atmel Sweden. "Ray Andraka" <ray@andraka.com> skrev i meddelandet news:3CEBA648.4ACD966B@andraka.com... > I'm looking for a dual processor system for a new employee. > The systems we have in house right now are Dual P3's > (800-1200 MHz) with 1-2GB memory and ultraSCSI RAID. Looking > for similar horsepower but with more recent technology. > What are people buyng today as far as serious workstations > for synthesis, simulation and PAR? > > -- > --Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com > > "They that give up essential liberty to obtain a little > temporary safety deserve neither liberty nor safety." > -Benjamin > Franklin, 1759 > >Article: 43506
Paul Baxter wrote:
> I've had a similar problem using Leonardo for synthesis with Altera, and it
> basically stems from the use of libraries.
Surely it's libraries issue ;)
> Bringing up the library manager you'll probably see an fpga express library
> and xilinx's own. In my Altera situation, for post-synthesis simulation AHDL
> complains about missing or incorrect apex20ke LCELLs etc which stems from a
> slight naming difference between Leonardo and Altera (I think)
So far I don't quite understand how AHDL uses libraries upon simulation.
And sometimes I don't quite follow what FPGA Express does.
I'm just reviewing the post-synthesis VHDL generated by FPGA Express.
Some of 'device related' entites are defined inside this file, like:
entity IBUF is
port (
O : out std_logic ;
I : in std_logic );
end IBUF ;
architecture FPGA_Express of IBUF is
begin
O <= ( I );
end FPGA_Express;
Of course this entity is empty for post-synthesis simulation.
But some entities like OSC4 gets only instantiated as components,
and compilation fails unless I manually compile Xilinx libraries manual into
project's post-synth library, as I metnioned previously.
But still it doesn't help much, because FPGA Express strips away generics like
the ROM32X1 values, so such a simulation is worth nothing.
> FWIW AHDL-hosted synthesis/PAR often does not allow you to specify optimised
> settings for the design, so it would be worthwhile you comparing the
> synthesis/timing report generated by the tools within AHDL and separately as
> a properly configured standalone synthesis/PAR process.
Yeah, I've hit such a problem already with AHDL + Lattice's ispDesigner. I
couldn't fit the design into desired chip,
switching on some options, unavailable in AHDL flow config, solved the problem.
> Also, why are you simulating post-synthesis? Usually this has a poor guess
> at routing speeds so any 'timing' issues won't get seen. IMHO you may be
> better to PAR and then use the timing simulation for better results. Start
> with a functional sanity check, then straight to timing.
That's the point. It was a real surpise to me - VHDL generated by FPGA Express
wasn't ok,
as described above, but EDIF file contained all the required informations
(including ROM's INIT attributes),
and after-PAR simulation works flawlessly :)
> Overall AHDL is a fine product, but make sure you get the best out of the
> design flow by optimising synthesis/PAR outside AHDL first and then compare
> to the AHDL-driven approach. Youcan still easily use AHDL with the vho/sdf
> files for simulation etc.
Yes, AHDL is very comfortable enviroment, I really like it. When it comes to do
some unusual things it looses a little of its comfort.
Also I've found 2 bugs in it, already reported to and corrected by Aldec.
Thanks for your answer :)
-=Czaj-nick=-
Article: 43507
Thanks. Unfortunately we need to keep the files local because the employees
are geographically separated (different states) so the connections to the
server are quite slow. The server is fine for backups and a central
repository, but not for a working directory (also looking to upgrade the
server, but that is lower priority for now).
Our current machines have the very fast SCSI drives, and if the PAR gets into
paging the performance is very much tied to the SCSI performance. I noticed
that the fast IDE drives still have the slower rotation speeds (7200 rpm vs
15000 on my scsi drives). Is that an issue, or perhaps by using more of the
cheaper IDEs in a Raid configuration I get better overall performance at a
similar or smaller price?
Johann Glaser wrote:
> Hi!
>
> > I've had no problems so far with a dual Athlon 2GHz with a 1Gb of RAM -
> > running quartus 2, ActiveHDL, Leonardo with Apex 20KE 600 devices. Also
> > has a normal IDE hard disk system (with RAID set to mirror for backup)
> > which is not noticibly slower than my previous much more expensive fast
> > SCSI system.
>
> Also consider a server with shared directories for every employee. Then
> you can make centralized backup. Lets say a monday-tape, a tuesday-tape,
> ... sunday-tape (if you sometimes work on weekend). These tapes are reused
> the following week. Perhaps use CD-RW instead, if the amount of data is
> not too much. And once every week or every month you backup to a tape
> which is stored in a safe or at a more secure place.
>
> You should then buy a really fast server with good HDD (SCSI with RAID 4
> or better RAID 5), lots of RAM (several GB) for cache and a thick network
> connection in your office. Use a Linux box with Samba running. Windows is
> only able to use it's own SMB network, although it is quite bad designed
> :-( so you have to offer it with the server. BTW: I heard that somebody
> replaced 5 WinNT4 Servers by one Linux server with Samba and the
> performance increased. :-)
>
> This is a one time investment, and all following employee workstations
> will get cheaper because you don't need SCSI, RAID, ... there. But I don't
> know if you have some reasons keeping files local.
>
> Bye
> Hansi
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 43508
I think it is a library or use clause problem. I've run into a similar thing with
the mapped VHDL output from synplicity for code that had ROM32s instantiated. The
synplicity mapped output uses the synplify library, and as it turns out the ROM32
is missing from that libarry. In order to get around it, I had to add library
unisim; use unisims.all; to the vhm file for the components that had instantiated
ROM32's. Once that was done, the functional simulation of the mapped code is fine.
Regarding Aldec, I have found the AHDL 5.1 tool to be very well executed. Aldec
has been very responsive with bug fixes in the relatively rare instances when bugs
have come up. I highly recommend the tool, as I find it a much better value than
the competition.
Przemyslaw Wegrzyn wrote:
> Paul Baxter wrote:
>
> > I've had a similar problem using Leonardo for synthesis with Altera, and it
> > basically stems from the use of libraries.
>
> Surely it's libraries issue ;)
>
> > Bringing up the library manager you'll probably see an fpga express library
> > and xilinx's own. In my Altera situation, for post-synthesis simulation AHDL
> > complains about missing or incorrect apex20ke LCELLs etc which stems from a
> > slight naming difference between Leonardo and Altera (I think)
>
> So far I don't quite understand how AHDL uses libraries upon simulation.
> And sometimes I don't quite follow what FPGA Express does.
> I'm just reviewing the post-synthesis VHDL generated by FPGA Express.
> Some of 'device related' entites are defined inside this file, like:
>
> entity IBUF is
> port (
> O : out std_logic ;
> I : in std_logic );
> end IBUF ;
>
> architecture FPGA_Express of IBUF is
>
> begin
> O <= ( I );
> end FPGA_Express;
>
> Of course this entity is empty for post-synthesis simulation.
> But some entities like OSC4 gets only instantiated as components,
> and compilation fails unless I manually compile Xilinx libraries manual into
> project's post-synth library, as I metnioned previously.
> But still it doesn't help much, because FPGA Express strips away generics like
> the ROM32X1 values, so such a simulation is worth nothing.
>
> > FWIW AHDL-hosted synthesis/PAR often does not allow you to specify optimised
> > settings for the design, so it would be worthwhile you comparing the
> > synthesis/timing report generated by the tools within AHDL and separately as
> > a properly configured standalone synthesis/PAR process.
>
> Yeah, I've hit such a problem already with AHDL + Lattice's ispDesigner. I
> couldn't fit the design into desired chip,
> switching on some options, unavailable in AHDL flow config, solved the problem.
>
> > Also, why are you simulating post-synthesis? Usually this has a poor guess
> > at routing speeds so any 'timing' issues won't get seen. IMHO you may be
> > better to PAR and then use the timing simulation for better results. Start
> > with a functional sanity check, then straight to timing.
>
> That's the point. It was a real surpise to me - VHDL generated by FPGA Express
> wasn't ok,
> as described above, but EDIF file contained all the required informations
> (including ROM's INIT attributes),
> and after-PAR simulation works flawlessly :)
>
> > Overall AHDL is a fine product, but make sure you get the best out of the
> > design flow by optimising synthesis/PAR outside AHDL first and then compare
> > to the AHDL-driven approach. Youcan still easily use AHDL with the vho/sdf
> > files for simulation etc.
>
> Yes, AHDL is very comfortable enviroment, I really like it. When it comes to do
> some unusual things it looses a little of its comfort.
> Also I've found 2 bugs in it, already reported to and corrected by Aldec.
>
> Thanks for your answer :)
>
> -=Czaj-nick=-
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 43509
I think you'll find that it will be considerably less effort to start from the
functional specification of the design and generate a fresh design to meet that
functional spec. It is hard enough to do the reverse engineering when you have
the LCA file which you can use to pick through the design in XDE. From a
bitstream, it is nearly impossible because the bitstream format is not
published and there (AFAIK) are no bitstream to LCA converters for these old
devices. You might talk to your Xilinx FAE to see if he has access to such a
converter, as I think there was one internal to Xilinx.
svhb wrote:
> Hi,
>
> For incorporating a very old design as part for a new design, I need to
> reverse engineer the bitstream of a XC3020A fpga.
>
> Can any one point me to a method to generate a kind of edif or xnf or other
> netlist from the bitstream??
>
> I know it is maybe a stupid question, but I need to try it because it is
> important here.
>
> Thanks a lot.
>
> Stefaan
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 43510> I need to program an Altera EPM7256AETC100-5 fpga, and have available > to me the device, MPU and appropriate VHDL code. However, I don't know > which programming adaptor I need to program the device with the MPU. > Does anyone know for sure which one, as the website is a little > confusing and not much help? Why not simply use the JTAG pins? BenArticle: 43511
You'd do well to use a modern device. The current tools do not even support the
devices you've listed below (the oldest supported are the 4000E series). There
are a number of eval boards with more current devices available for under $200,
and the (crippled) tools for these are available free on the web. You'll be
hard pressed to find tools for the older families you list.
James Zaiter wrote:
> hi my name is james and my email is jzaiter@magnasys.com.au
> I am new to fgpa programming and need some direction in learning to programm
> these devices.
> I need help with software and development board preferably xilinx
> xc2000,xc3000 and xc4000 chips.
> is there any free software available to use for learning purposes only as i
> have a very small budget.
> any help would be much appreciated.
> james
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 43512In article <3CEBA90F.9F1C1F70@andraka.com>, Ray Andraka <ray@andraka.com> wrote: >It is, but at 50MHz you'd have to work really really hard at it. That assumes >you are not shorting any of the I/O, of course. I think a Xc2S50 with all the >cells connected as SRL16s plus registers and toggled on average at 50% is going >to be well under 2W. Most designs are not going to come near that level of >activity. If you REALLY want to kill the chip with a downloaded file. Legal way: Include bus fights with tristates. Illegal way: Munge the bitfile. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 43513
In article <3CEBA648.4ACD966B@andraka.com>, Ray Andraka <ray@andraka.com> wrote: >I'm looking for a dual processor system for a new employee. >The systems we have in house right now are Dual P3's >(800-1200 MHz) with 1-2GB memory and ultraSCSI RAID. Looking >for similar horsepower but with more recent technology. >What are people buyng today as far as serious workstations >for synthesis, simulation and PAR? I'd personally get a Dual Athlon, stacked with memory right now. AMD offers better bang/buck, and a much more cad tool friendly L1 and L2 cache (BIG!) than the P4. The P4 has a pathetic L1 cache and a pathetic Icache, these really hurt. As for disk, is UltraSCSI raid really necessary? How much of the time is spent waiting on disk IO? RAID improves bandwidth, not latency (which is often the bigger deal), and SCSI realyl only offers out of order requests these days. You probably would want a multihead system, but that goes without saying. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 43514
"Kelvin XCJ" <qijun@okigrp.com.sg> wrote in message news:3ce8a00a@news.starhub.net.sg... > Hi: > > I want to know what's the advantage Altera and Xilinx over each other. > Are their performance very different from each other? > If you have the luxury of having a full license for a top synthesizer, my suggestion is at the first stage write your HDL in a portable (hehehe yeah, portability is coming from software domain to hardware too ;) ) manner and then try different targets to see how it meets the design goals. This way you can check to see what's the "cheapest" FPGA that fits the project's constraints. At a later stage you may optimize your HDL code more for the selected target. Different FPGAs from different families tend to have characteristics that are suited better for different applications. I don't see any point to sticking to a certain family if I see advantages in another family for a specific design. Just like any other "part" of the system, FPGAs are "parts" and should be selected the way they fit... By the way, world is not only Xilinx and Altera, for some designs you may find better parts with other brands.... Regards ArashArticle: 43515
Hi again We were using a 4062XLA at the time. We have also used 4062XL (no 'A') line and as I mentioned, yes, I had more than eight states of logic.Article: 43516
To clarify the misunderstanding: The XC2V250 requires <1.6 million configuration bits. You can shift them in at any rate you want, up to 50 MHz CCLK rate, which then takes 32 milliseconds. Or you shift them in byte-wide at any rate, up to 50 MHz, where it take less than four milliseconds. Config time is obviously inversely proportional to CCLK rate, with SelectMAP providing the 8-times boost due to byte-parallel operation. Peter Alfke, Xilinx Applications ===================================== Mitchell Crago wrote: > I am using a XC2V250 for a project, and I'm trying to work out the expected > configuration times. The only reference I have found to allow around 1mS per > bit of the configuration stream. If this is true, it will take me around 28 > minutes to configure the device. Is this true? If not, how long would one > expect to load a design? > > Cheers > > Mitchell > mmccrraaggoo@@ffllooww.ccoomm.aauu > __________________________________________________________________Article: 43517
Has anybody else noticed that the value for Tciny on Virtex2 seems excessively large? This is the amount of time it takes for carry data to come into the slice through the carry in input and go through the carry XOR to the Y line (from which it can go into the flop). For some reason, this value and other arithmetic-related values can't be found in the V2 data sheet, but Timing Analyzer tells me this value is 1.446ns! Remember, it only takes 100ps (Tbyp) to get all the way through two carry-chain muxes. This value is made even more incredible by the fact that Tciny was only about 600ps in a Virtex-E. This is really killing me. It doesn't matter how fast my carry chains are if Tciny + Tdyck (flop setup time from Y input) is almost 2ns. With 18-bit adders at 192MHz, this leaves me about 1.1ns to route from one adder output to the next adder input, and this value seems to allow me a radius of less than ten slices. -KevinArticle: 43518
Angus, I do not know what "turns you on". I personally would not be interested in experimenting with a dead architecture. The XC6200 is no longer available. It died for lack of commercial interest. There was a lot of academic interest, but that does not pay our bills :-(. So you an make theoretical experiments, but do not expect to be able to verify them on silicon, let alone extrapolate them to realistic hardware in the future. Just a friendly warning... Peter Alfke, Xilinx Applications ===================================== Angus Thompson wrote: > Hi all, > > I have been thinking about using a simulated sea-of-gates FPGA > architecture for some design experiments. I want to keep the > architecture as simple as possible. I was thinking about using a sea > of 4 input LUTs, each of the four inputs being driven by the output > from one of the 4 surrounding LUTs, as I can easily map this to a real > FPGA. However as there is only 1 layer of logic no signal can cross > another, which really limits what combinational logic you can make. > > I understand the Xilinx 6200 had a similar architecture. I suppose the > longer lines could be used to cross signals, but it doesn't seem > reasonable to have such a serious limitation for an FPGA. Is there > anyone out there who did designs with the 6200 that can tell me what > I'm missing? > > Cheers, AngusArticle: 43519
Another question: a colleague told me that he thinks the output of the XORG (dedicated adder XOR) has to go outside of the slice to a switchbox before it gets routed back into the slice and into the flop. This sounds unusual, but the slice diagram in the V2 manual seems to indicate this, while the slice diagram in the VirtexE manual shows a dedicated switch mux in the slice to route XORG to the flop. Are the adders in V2 then slower than in VirtexE? And why has all the carry chain data been eliminated from the V2 datasheet? Is there a multinational conspiracy? "Kevin Neilson" <kevin-neilson@removethistextattbi.com> wrote in message news:uWQG8.6460$352.580@sccrnsc02... > Has anybody else noticed that the value for Tciny on Virtex2 seems > excessively large? This is the amount of time it takes for carry data to > come into the slice through the carry in input and go through the carry XOR > to the Y line (from which it can go into the flop). For some reason, this > value and other arithmetic-related values can't be found in the V2 data > sheet, but Timing Analyzer tells me this value is 1.446ns! Remember, it > only takes 100ps (Tbyp) to get all the way through two carry-chain muxes. > This value is made even more incredible by the fact that Tciny was only > about 600ps in a Virtex-E. > > This is really killing me. It doesn't matter how fast my carry chains are > if Tciny + Tdyck (flop setup time from Y input) is almost 2ns. With 18-bit > adders at 192MHz, this leaves me about 1.1ns to route from one adder output > to the next adder input, and this value seems to allow me a radius of less > than ten slices. > > -Kevin > >Article: 43520
Nicholas Weaver wrote > If you REALLY want to kill the chip with a downloaded file. > > Legal way: Include bus fights with tristates. AFAIK, not possible in Virtex-derived parts.Article: 43521
In article <6f3a4943.0205220403.376ca445@posting.google.com>, Angus Thompson <angusthompson@hotmail.com> wrote: >I understand the Xilinx 6200 had a similar architecture. I suppose the >longer lines could be used to cross signals, but it doesn't seem >reasonable to have such a serious limitation for an FPGA. Is there >anyone out there who did designs with the 6200 that can tell me what >I'm missing? I think the 6200 had a few farther interconnects, but it was generally low. In order to be "safe" in the event of misconfiguration, all switching was muxes, so that it was impossible to create a configuration which would drive a wire both high and low. The net result was the interconnect was very poor and inflexible, and thus found little commercial interest. It got a lot of academic interest because the reconfiguration mechanisms were very powerful, and it was safe so a bad reconfiguration wouldn't burn the chip. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 43522
Ray Andraka wrote: > I think it is a library or use clause problem. I've run into a similar thing with > the mapped VHDL output from synplicity for code that had ROM32s instantiated. The > synplicity mapped output uses the synplify library, and as it turns out the ROM32 > is missing from that libarry. In order to get around it, I had to add library > unisim; use unisims.all; to the vhm file for the components that had instantiated > ROM32's. Once that was done, the functional simulation of the mapped code is fine. Thanks for your suggestion, I'll try to play around with it. -=Czaj-nick=-Article: 43523
I use Xilinx ISE 4.1 (FPGA Express 3.6.1) + Active-HDL.
Target chip: XC4003E
1. I/OPADS problem.
Should I place PADS or PORTS next to I/OBUFs ? PADS are a little
uncomfortable to me, as I can't use such entity for simulation,
thus I use ports everywhere. I've tried to use FPGA Express option to
inert I/O pads but it doesn't seem to work.
Finally I've found similar option in the implementation tools ("Create
I/O Pads from Ports"), and it works, but I'm not
sure if it's a right solution.
2. How to use GSR ?
I've placed STARTUP component on my toplevel schematic, connected IBUF
and port to it, it seems to be ok -
I can see these components connected together in FPGA Editor. But GSR
option is disabled in STARTUP block :(
I don't know what to do next. There's a net that sets/resets all the
flipflops (I've checked it in post-synth EDIF netlist),
but I don't know what to do with it - place IBUF/port on it ?
3. Clocks
I use 2 clocks in my design, one external and OSC4 output. I pass the
clocks through BUFGS.
During implementation I get the following warning:
Timing - Clock nets using non-dedicated resources were found in this
design....
Why ? Both clocks uses dedicated global nets !
-=Czaj-nick=-
Article: 43524nweaver@CSUA.Berkeley.EDU (Nicholas Weaver) writes: > In article <6f3a4943.0205220403.376ca445@posting.google.com>, > Angus Thompson <angusthompson@hotmail.com> wrote: > >I understand the Xilinx 6200 had a similar architecture. Sort of. It had far more selection ability. It had 4 outputs (one to each direction) which could all be derived from inputs (one via processing element, the others just pass through switches. It also had 8 inputs (neighbor and long distance from each direction). - X1, X2, X3 are selected from Inputs N, S, E, W or the 4 longs - F is generated from X1, X2, X3 by processing element - Nout, Sout, Eout, Wout are selected from N, S, E, W or F > >I suppose the > >longer lines could be used to cross signals, but it doesn't seem > >reasonable to have such a serious limitation for an FPGA. Long lines were just for faster signal propagation. Crossing was done in the output 4 selection muxes. > >Is there > >anyone out there who did designs with the 6200 that can tell me what > >I'm missing? The XC62xx data sheet? I once found a copy at: http://www.vcc.com/Papers/6200.pdf VCC was once the manufacturer of an XC6216 based prototyping board. > low. In order to be "safe" in the event of misconfiguration, all > switching was muxes, so that it was impossible to create a > configuration which would drive a wire both high and low. This also reduced the amount of config bits memory. > The net result was the interconnect was very poor and inflexible, and > thus found little commercial interest. Looks like that to me also. The Atmel AT600 looks like a far more flexible SoG architecture. > It got a lot of academic interest because the reconfiguration > mechanisms were very powerful, and it was safe so a bad > reconfiguration wouldn't burn the chip. Not to mention, that the entire bitstream description was published in the data sheet. Academics like fully documented stuff, that gives them full flexibility of designing their systems from ground up. -- Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/ Hacker, Unix Guru, El Eng HTL/BSc, Sysadmin, Archer, Roleplayer - Make your code truely free: put it into the public domain
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z