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I have been having trouble creating hard macros with Xilinx's FPGA Editor. I am working on a large design targetted for a XC2V4000 in which one particular component is used several times. I am trying to reduce the time it takes PAR to complete and still meet timing. So, I have been trying to create a hard macro out of the P&R'ed component but have run into problems with the Xilinx suite of tools. The design contains a VCC which apparently is a known bug in FPGA Editor's macro generation. I have been talking with Xilinx support, but they have not offered me any practical solutions. Does anyone out there have any suggestions? Is there perhaps another way of reducing my PAR times. I am not locked into this hard macro thing and am open up to suggestions. Week long P&R times do not appeal to me. Thanks, JeffArticle: 42826
Manfred, you are describing DDS, Direct Digital Synthesis, and that can give you impressive values for the average output frequency, down to milliHertz granularity. But you pay for that with output jitter. In the particular case, about 30 MHz was requested with mHz resolution. The period of 30 MHz is roughly 30 ns. The difference in period length for a 1 Hz deviation is 1 femtosecond. For 1 mHz it is thousand times less... Running the phase accumulator at 500 MHz would create an output time granularity of 2 ns. This means the output transition would often be up to 1 ns away from the right moment. In other words, there is 1 ns of peak jitter, thousand times the required timing resolution at 1 Hz granularity, a million times the required resolution at 1mHz granularity. I have big doubts that this circuit would come even close to the desired goal. Greetings Peter Alfke ===================================== Manfred Kraus wrote: > Hi Noddy, > > I think my solution maybe wont work for you because > your reference and output frequencies are too high. > Anyway. I will try to describe it. > > In my application the reference signal is between 5 kHz and 50 kHz. > A counter running at a very high frequency is used > to measure the number of Systemclock cycles between > the edges of the reference signal (Reference Period). > I constructed an entity that takes the Systemclock and the > actual Period value as input and produces an output clock > (I call it FineClock) with a frequency of ReferenceFreq * 2**n. > The FineClock feeds an Akkumulator. It adds a constant at every > SystemClock cycle. The highest bit of the akkumulator is the > output frequency. The Akkumulator constant defines the relation > between the reference frequency and the final output frequency. > For this design it is very important that there are no "dead" SystemClock > cycles. For ex. the SCLK edge that latches the period value must also count > for > the next period measurement. Otherwise the error adds up and the whole > thing > will not "lock". I have used this type of PLL in many designs for different > customers > and I am really very pleased with the results. > > If you want to contact me, use "mkraus" instead of "newsreply" in the Email > address below. > > - Manfred Kraus > > ---------------------------------------------------------------------------- > ---------------- > CESYS Gesellschaft für angewandte Mikroelektronik mbH > Buchenstr. 13 > D-91074 Herzogenaurach > > Tel. +49 9132 733 400 > Fax. +49 9132 733 401 > Email: newsreply@cesys.com > URL: http://www.cesys.com > ---------------------------------------------------------------------------- > ---------------- > > "Noddy" <g9731642@campus.ru.ac.za> schrieb im Newsbeitrag > news:1020370492.898003@turtle.ru.ac.za... > > Hi Manfred, > > > > My output frequency range is very small... between about 31.5MHz and > > 32.5Mhz, although I need mHz precision. It should use a 5MHz reference > > signal. > > > > Adrian > > > > > Hi Adrian, > > > I developed a digital PLL some years ago > > > and found some unknown tricks. > > > Maybe I can help you. > > > What is your desired output frequency range ? > > > > > > -Manfred > > > > > > > > > > > > "Noddy" <g9731642@campus.ru.ac.za> schrieb im Newsbeitrag > > > news:1019660268.49750@turtle.ru.ac.za... > > > > Hi, > > > > > > > > I am trying to design a high precision (30 bit) frequency synthesiser > > > inside > > > > a Spartan II. Of course, normal way to do this is with a charge pump, > > > > voltage controlled oscillator and a phase lock loop. > > > > > > > > Can anyone point me to some good references? I have a very high > > precision > > > > 5Mhz which is generated from a hydrogen maser and will be used as the > > > input > > > > clock signal. > > > > > > > > thanks > > > > adrian > > > > > > > > > > > > > > > > > > > > > >Article: 42827
Another work around is to just accept the fact that xilinx will never update the editor tool to work properly. work around the vcc with a lut work around the slow editor performance by removing your pcf file work around the manual routing bug by turning off layer visibility Still manual routing, using schematics, and walking like an ape "Peter Alfke" <peter.alfke@xilinx.com> wrote in message news:3CD2FCD1.44A965FD@xilinx.com... > Can you use - as a work-around- the output of a LUT instead of Vcc, or the Q of > a flip-flop preset by configuration? > > Peter AlfkeArticle: 42828
When are all of the people in need on this board going to realize that I CAN HELP WITH XILINX NEEDS / SHORTAGES!!!! :o) Not only shortages, but most of the time, I can beat Mfg's Direct pricing! Just send us your requirement, price, and desired delivery date. Whoever needs help, feel free to e-mail me. I can quote on stock, availability, or if you want, I'll just let you use me as a reference point for current market pricing to see if you're getting your head ripped off. Xilinx, Altera, AMD, Intel, Samsung, Maxim, Analog Device, PMC-Sierra, and Conexant are what we specialize in. Here's a quick sample of what types of Xilinx we have available: XCV812E-6BG560C XCV600-5BG560C XCV400E-7FG676C XCV400-4BG560C XCV300E-6FG456C XCV300-5BG352CES XCV300-5BG352C XCV200-6BG352C XCV200-4BG256C XCV2000E-6FG1156C XCV1600E-6FG680C XCV150-5BG352CES XCV150-5BG352C XCV150-4BG352C XCS30XL-5VQ100C XCS20XL-4VQ100C XCS20-3VQ100VC XCS10-3VQ100C XCS05XL-4VQ100C XCS05XL-4VQ100C XCS05-3VQ100C XC9572XL-5TQ100I XC9536-7PC44C XC95288XL-10TQ144C XC95288XL-10CS280I XC95144XL-10TQ144I XC95144-10PQ160C XC95108-10PQ100C XC7372-15PC84C XC7354-7PC44C XC7354-10PC44C XC5204-6PC84C XC5204-5VQ100C-T/R XC5204-5VQ100C XC5202-6PQ100C XC4062XLA-09BG432C XC4036XLA-09BG352I XC4010E-1PQ208C XC4010-4PQ160C XC4005XL-2TQ1441 XC4005-5PQ100C167 XC3342A-PC84C XC2S100-5PQ208C XCS30-3VQ100C Regards, Jeff Wallace Pro-Tech Solutions, Inc Primary: (949) 498-4301 Ext. 40 Toll Free: (888) 690-8899 Fax: (949) 498-4302 / 4372 "Magnus Homann" <d0asta@mis.dtek.chalmers.se> wrote in message news:ltoffzzw7u.fsf@mis.dtek.chalmers.se > rickman <spamgoeshere4@yahoo.com> writes: > > > We have slipped a month on our schedule already due to changes in the > > design. Now we will have to slip another two months, maybe more due to > > lack of availability of the Xilinx parts. > > Buy a bigger one while you wait? > > Homann -- Posted via Mailgate.ORG Server - http://www.Mailgate.ORGArticle: 42829
When are all of the people in need on this board going to realize that I CAN HELP WITH XILINX NEEDS / SHORTAGES!!!! :o) Not only shortages, but most of the time, I can beat Mfg's Direct pricing! Just send us your requirement, price, and desired delivery date. Whoever needs help, feel free to e-mail me. I can quote on stock, availability, or if you want, I'll just let you use me as a reference point for current market pricing to see if you're getting your head ripped off. Xilinx, Altera, AMD, Intel, Samsung, Maxim, Analog Device, PMC-Sierra, and Conexant are what we specialize in. Here's a quick sample of what types of Xilinx we have available: XCV812E-6BG560C XCV600-5BG560C XCV400E-7FG676C XCV400-4BG560C XCV300E-6FG456C XCV300-5BG352CES XCV300-5BG352C XCV200-6BG352C XCV200-4BG256C XCV2000E-6FG1156C XCV1600E-6FG680C XCV150-5BG352C XCV150-5BG352C XCV150-4BG352C XCS30XL-5VQ100C XCS20XL-4VQ100C XCS20-3VQ100VC XCS10-3VQ100C XCS05XL-4VQ100C XCS05XL-4VQ100C XCS05-3VQ100C XC9572XL-5TQ100I XC9536-7PC44C XC95288XL-10TQ144C XC95288XL-10CS280I XC95144XL-10TQ144I XC95144-10PQ160C XC95108-10PQ100C XC7372-15PC84C XC7354-7PC44C XC7354-10PC44C XC5204-6PC84C XC5204-5VQ100C-T/R XC5204-5VQ100C XC5202-6PQ100C XC4062XLA-09BG432C XC4036XLA-09BG352I XC4010E-1PQ208C XC4010-4PQ160C XC4005XL-2TQ1441 XC4005-5PQ100C167 XC3342A-PC84C XC2S100-5PQ208C XCS30-3VQ100C -- Posted via Mailgate.ORG Server - http://www.Mailgate.ORGArticle: 42830
It appears that on a fully utilized XC2V6000, there is no solution to be able to run the FPGA Editor. The program hits the 2GB memory limit and quits. How did Xilinx test there code? I know that the memory limit is imposed by Microsoft, and it is what it is, and there is no changing that any time soon. So why can't Xilinx recode to use the available memory space more efficiently or store data on the HD so at least I can run (albeit more slowly). And another thing, guess I can accept waiting 30 minutes to load a database into a tool, but it seems crazy to have to wait another 30 minutes to exit without even saving just to get my memory back.Article: 42831
"Jay" <kayrock66@yahoo.com> wrote in message
news:d049f91b.0205031510.71927d02@posting.google.com...
> It appears that on a fully utilized XC2V6000, there is no solution to
> be able to run the FPGA Editor. The program hits the 2GB memory limit
> and quits. How did Xilinx test there code? I know that the memory
> limit is imposed by Microsoft, and it is what it is, and there is no
> changing that any time soon. So why can't Xilinx recode to use the
> available memory space more efficiently or store data on the HD so at
> least I can run (albeit more slowly).
Interesting!
If I recall correctly:
1. Some versions of Windows NT and follow ons allow 3 GB user space
addressing. There is a /3GB boot.ini flag. I don't know if Xilinx software
would have to be rebuilt to target it. This would be a reasonable interim
workaround if 2 GB is too confining.
2. Some versions of Windows 2000 and follow ons allow windowed access to
more than 4 GB of RAM per process. Shudder, too much like 1980's era bank
switching and overlays.
3. AMD Opteron and Intel Itanium are right around the corner. Both allow
flat 64 bit addressing, and both will be supported by a forthcoming Windows
XP. I bet you'll see Opteron systems for sale by 1Q03.
4. However, traditionally it has taken Xilinx a relatively long time
(relative to other ISVs) to adopt and support the latest Windows platforms.
For example, the Win32 PDC was in Dec'92 but Xilinx didn't support Win32
until several years later. So don't hold your breath.
.
On the other hand, IF devices grow too large to place and route in 2, 3, or
even 4 GB, Xilinx would certainly be highly motivated to:
1. continue to invest in more modular flows so you don't need to P&R the
whole design at one time;
2. ("" "" "" "" "" "" "" so you can employ P&R server farms -- not a memory
issue, just a design spin time issue)
3. adopt more memory efficient data structures, as you suggest;
4. make their code 64-bit safe NOW so they can ride the 64-bit Windows wave
just as soon as it becomes commercially available.
Oh yeah:
5. Xilinx ISE 4.2 implementation tools supposedly run on WINE on Red Hat
Linux 7.2. Xilinx has also announced plans to ship Linux-native tools in
2003. When they do, 64-bit Linux should also be ready to apply to this
problem.
[Disclaimer: this merely summarizes news articles that I have read.]
Jan Gray, Gray Research LLC
Article: 42832Jay wrote > And another thing, guess I can accept waiting 30 minutes to load a > database into a tool, but it seems crazy to have to wait another 30 > minutes to exit without even saving just to get my memory back. Close the design before exiting the program. Seems to be at least 10 times faster than just exiting.Article: 42833
>3. AMD Opteron and Intel Itanium are right around the corner. Both allow >flat 64 bit addressing, and both will be supported by a forthcoming Windows >XP. I bet you'll see Opteron systems for sale by 1Q03. >4. make their code 64-bit safe NOW so they can ride the 64-bit Windows wave >just as soon as it becomes commercially available. >5. Xilinx ISE 4.2 implementation tools supposedly run on WINE on Red Hat >Linux 7.2. Xilinx has also announced plans to ship Linux-native tools in >2003. When they do, 64-bit Linux should also be ready to apply to this >problem. 64 bit Linux is has been running fine for many years on Alphas from Compaq/Digital. No excuse for not porting code now if they are seriously interested. SGI has 64 bit gear and they jumped on the Linux bandwagon a while ago. I also see a sparc64 section in the Linux kernel source tree. I haven't used either. -- These are my opinions, not necessarily my employer's. I hate spam.Article: 42834
Jeff <jeff@Despammed_Domain.com> wrote: > I have been having trouble creating hard macros with Xilinx's FPGA > Editor. I am working on a large design targetted for a XC2V4000 in > which one particular component is used several times. I am trying to > reduce the time it takes PAR to complete and still meet timing. So, I > have been trying to create a hard macro out of the P&R'ed component > but have run into problems with the Xilinx suite of tools. The design > contains a VCC which apparently is a known bug in FPGA Editor's macro > generation. I have been talking with Xilinx support, but they have not > offered me any practical solutions. Does anyone out there have any > suggestions? Is there perhaps another way of reducing my PAR times. I > am not locked into this hard macro thing and am open up to > suggestions. Week long P&R times do not appeal to me. Hi - may be this is a another question. I want to know how you create your hard macro. I have a component with only primitives and fully RLOCed in VHDL. also, a netlist is generated from these codes. is there a way to reduce the time to create the hard macro by using these information? Thanks in advance. ---- Brittle btw: I am working on XCV1000E chip and it take me 20 hrs. to finish a design. how many logics are there in your week long design?Article: 42835
Do Someone has info or Good reference for Pointer processor ? ThanksArticle: 42836
On Tue, 30 Apr 2002 15:03:45 +0200, Laurent Gauch
<laurent.gauch@amontec.com> wrote:
>I am searching an EDIF parser for automatic documentation generation.
>
>where can I get some scripts?
A full EDIF parser is quite hard in Perl. You might be better off
using a language like Lisp.
OTOH, if this is just for "automatic documentation generation" then a
few simple Perl REs will be able to extract the information you are
after.
Perhaps something like this would do:
my $filename = "file.edf";
open (EDIF, "<$filename") or print "Can't open EDIF file $filename
$!\n";
while ( <EDIF> )
{
if ( m/\(\s*property PART \(string ([^\)]+)\)/ ) {
print "part : $1\n";
}
elsif ( m/\(\s*timeStamp ([^\)]+)\)/ ) {
print "timestamp : $1\n";
}
elsif ( m/\(\s*program ([^\)]+)\)/) {
my $edif_program = $1;
$edif_program =~ s/\(//;
print "program : $edif_program\n";
}
}
close EDIF;
Regards,
Allan.
Article: 42837Kevin Brace <ihatespam99kevinbraceusenet@ihatespam99hotmail.com> wrote: > I don't think that's an excuse for messing up the datasheet. > How many people will actually read the library guide compared to the > datasheet? If I was going to instantiate an OBUFT in my design, I would head straight for the libraries guide. I wouldn't even think to look in the data sheet for the device - it's a library issue, not a device issue. Hamish -- Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>Article: 42838
Jay <kayrock66@yahoo.com> wrote: > It appears that on a fully utilized XC2V6000, there is no solution to > be able to run the FPGA Editor. The program hits the 2GB memory limit > and quits. How did Xilinx test there code? I know that the memory How full is your design? I'm working on a 2V6000 design at the moment (about 50% full) and haven't seen FPGA editor use anything like that much RAM - PAR either, for that matter. > And another thing, guess I can accept waiting 30 minutes to load a > database into a tool, but it seems crazy to have to wait another 30 > minutes to exit without even saving just to get my memory back. There's a Xilinx answer (at support.xilinx.com) on how to speed up FPGA editor load time - I tried it the other day and it makes a huge difference. Hamish -- Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>Article: 42839
>If I was going to instantiate an OBUFT in my design, I would head >straight for the libraries guide. I wouldn't even think to look >in the data sheet for the device - it's a library issue, not >a device issue. But what if you didn't design it. Suppose you are reviewing or helping to debug something that somebody else wrote? It's all obvious after you know the secret. In the old days, TTL chips mostly had low true output-enables. The typical drawing said "OE" and had a bubble. If that's what you are used to, it would be real easy to get confused by noticing one change (OE to T, bubble to no-bubble) but not the other when you were trying to check the polarity of the control signal. "This looks wrong. Oh, I see. No bubble." We all understand now. We just have to remember whenever we are suspicious of something like that. We don't even have to remember the answer - we can look that up. We just have to remember to be suspicious of output buffers with an enable. -- These are my opinions, not necessarily my employer's. I hate spam.Article: 42840
A couple of problems: 1- SelectRAM being used for FIFO memory. The application in question has the read side of the FIFO read input data in packets. The input side signals the output side when packets are available. No problems there. Under certain conditions (startup, reset, etc.) both the write and read pointers will be looking at the same memory and the write side will write a word. The read side, as I understand it, will either read corrupt data or old data while parked at this address waiting for a packet to be available. This is not a problem as long as valid data is actually written to that initially common location such that when I go to use it, some 128 writes later, the data read will be valid. The Virtex II documentation isn't all that clear on this particular condition. Anybody know if I'll have problems? 2- DCM frequency synth. The Virtex II "Detailed Description" document states that the M and D parameters have a range of 1 to 4095. Somebody at Xilinx is telling me that the range is 2 to 32 ... he sounds like a junior guy 'cause he has to go check and research every answer. Could an experienced DCM end-user let me know which it is? Also, what is the precision of the resulting frequency? If I set M to 2000 and D to 367 and the input frequency is 25 MHz, what do I get? How much jitter? Thanks, -- Martin E. To send private email: 0_0_0_0_@pacbell.net where "0_0_0_0_" = "martineu"Article: 42841
"Vernon L. Stant" wrote: > > Has anyone used the MicroBlaze? How did it work out? Strange, that not one of the 9000 users cares to comment ;-)Article: 42842
Heya,
I have a signal that comes from a pin and goes to the D input on 4 latches.
Ideally, any edge on the signal would reach the latches at exactly the
same time.
How do I properly constrain the signal so that the Xilinx place/route
tool minimises the skew across the 4 imputs?
Cheers,
--
. . Iain Waugh
. o ._o .o \#/. o. o_. o . iain@zip.com.au
`) /\ =) .-kai- )= /\ )' http://www.zip.com.au/~iain
/< < < /#\ . > > >\ :.::.:TAG.:.::.
.
Article: 42843"Iain Waugh" <iain@zip.com.au> schrieb im Newsbeitrag news:3CD3BD47.7020404@zip.com.au... > Heya, > > I have a signal that comes from a pin and goes to the D input on 4 latches. > > Ideally, any edge on the signal would reach the latches at exactly the > same time. Do they really need very good aligned to each other? In most applications, you just need to make sure that the input signals reach the flipflop/latches a short time before the clock arrives. Anyway, to tell the software about the skew constraint, write this into the UCF NET my_netname maxskew=1ns; -- MfG FalkArticle: 42844
"sympatico" <zakhama@sympatico.ca> schrieb im Newsbeitrag news:8dGA8.18926$1k5.2961236@news20.bellglobal.com... > Do Someone has info or Good reference for Pointer processor ? What do you mean with "pointer-processor" ? SDH pointer processors? For this, go to www.pmc-sierra.com, they have lots of good informations (but nothing down to VHDL, more the general functions) -- MfG FalkArticle: 42845
"Peter Alfke" <peter.alfke@xilinx.com> schrieb im Newsbeitrag news:3CD2FBFC.1B511E99@xilinx.com... > Manfred, you are describing DDS, Direct Digital Synthesis, and that can give you > impressive values for the average output frequency, down to milliHertz > granularity. > But you pay for that with output jitter. > In the particular case, about 30 MHz was requested with mHz resolution. > The period of 30 MHz is roughly 30 ns. The difference in period length for a 1 > Hz deviation is 1 femtosecond. For 1 mHz it is thousand times less... > > Running the phase accumulator at 500 MHz would create an output time granularity > of 2 ns. This means the output transition would often be up to 1 ns away from > the right moment. In other words, there is 1 ns of peak jitter, thousand times > the required timing resolution at 1 Hz granularity, a million times the required > resolution at 1mHz granularity. Why reinvent the wheel? The problem described here is common and , since it is already present for a while, solved in many way. DDS can give you mHz resolution for almost no cost and phase continuity when modulated. BUT you have a big amout of jitter when it comes to high frequencyies (whatever high means here). A classig analog PLL can give you superior jitter performance (ok, not the best know to man, but much better than plain digital DDS). So simply combine both. Generate a high frequency resolution using a DDS and smooth out the jitter using an analog PLL. There are special tricks possible to transform the jitter (phase noise) of the DDS into high frequency regions, so it is easier for the PLL, to clean up the signal. -- MfG FalkArticle: 42846
We are a SOPC and SOC development organization. We have a number of softcores available and numerous peripherals and supports both Xilinx and Altera FPGAs. This includes - 8051 core - pic core - sparc core - AMBA bus - SDRAM controller - DMA engine - Digital Signal processing blocks - etc. Please visit our website at www.mobileune.com to have more detailsArticle: 42847
> For example, the Win32 PDC was in Dec'92 ... Correction (not that anyone else really cares): After some googling, I recall there was a Win32 PDC (Professional Developer's Conference), featuring NT, in SF in 7/92, and another Win32 PDC, featuring 'Chicago' (aka Win95), in Anaheim in 12/93 (I attended that one). Jan Gray, Gray Research LLCArticle: 42848
In article <3CD3B0E8.DAA9F6A1@ecubics.com>, emanuel stiebler <emu@ecubics.com> wrote: >"Vernon L. Stant" wrote: >> >> Has anyone used the MicroBlaze? How did it work out? > >Strange, that not one of the 9000 users cares to comment ;-) We've comitted to it (but haven't gotten it yet) I'm getting worried... Should we have gone with NIOS??!?Article: 42849
kayrock66@yahoo.com (Jay) writes: > It appears that on a fully utilized XC2V6000, there is no solution to > be able to run the FPGA Editor. The program hits the 2GB memory limit > and quits. How did Xilinx test there code? I know that the memory Maybe on a SUN UltraSPARC III under 64-bit Solaris :-) I pray for a native ISE running under X86-64 Linux soon. Check out http://www.x86-64.org. Petter -- ________________________________________________________________________ Petter Gustad 8'h2B | (~8'h2B) - Hamlet in Verilog http://gustad.com
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