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A few weeks back I noticed a posting regarding salary information for Hardware Engineers and I checked it out. www.hitechsalary.com At the time, I was entertaining new opportunities and needed to know what my salary should be for the two areas I was interviewing in, this site worked great. It gave me the information I was looking and negotiated a better salary. I was able to get an extra $4k in my package. ---------- Scullen HW EngArticle: 30726
mike wrote: > > hi all, > i want to configure my fpga on a pci card via the jtag pins > on the pci connector, but i dont know how to access these pins. > can you help me? hi These pins are here only for test purpose. I think they're linked to some test port on the board but you can't access them through any component of the board, unless you add a cable between the parallel port and this JTAG port (if you can find it) -- Nicolas MATRINGE IPricot European Headquarters Conception electronique 10-12 Avenue de Verdun Tel +33 1 46 52 53 11 F-92250 LA GARENNE-COLOMBES - FRANCE Fax +33 1 46 52 53 01 http://www.IPricot.com/Article: 30727
Hi, can any one point me towards some manufacturers of programmable FIR chips (not Graychip or Intersil - I have data on them). I want to contrast performance & price vs implementation in FPGAs. The sort of speeds & resolution I'm looking for a probably the killer - 175MHz & 16 bits (yes I know, an FPGA really is the way to go, but, I gotta look!) regards, Paul T.Article: 30728
say i want to route a signal vertically form y1 to y2 coordinates, is it faster to route it through the carry logic, or just using the dedicated routing ressources thanks <.>~<.> CATHY _________________________________________________________________________ Get Your Private, Free E-mail from MSN Hotmail at http://www.hotmail.com. -- Posted from [216.104.228.116] by way of f6.law14.hotmail.com [64.4.21.6] via Mailgate.ORG Server - http://www.Mailgate.ORGArticle: 30729
Hi,
I discovered that the loadBitFile method does not work for bit files created
by bitgen with the option "-g Security:Level2" (a default option in
foundation). By setting "-g Security:None" I have resolved the problem.
Vivian
"Vivian" <vivian.bessler@ucd.ie> wrote in message
news:newscache$qwuacg$uv4$1@weblab.ucd.ie...
> Hi,
>
> I'm using the rc1000pp board from celoxica with a virtex 1000 fpga.
> Currently I'm trying to configure it using the XHWIF interface instead of
> the c libraries that came with the board.
>
> The following c code works:
>
> PP1000SetClockRate(Handle, PP1000_VCLK, 10e6);
> PP1000ConfigureFromFile(Handle, "config.bit");
>
> However the following java code does not:
>
> XHWIFwEvents.setClockFrequency(10);
> XHWIFcon.loadBitFile("config.bit",0);
> xhwif.clockOn();
> con.softReset(0);
>
> The problem only seems to occur when the design requires a global reset.
>
> Does anyone know the difference between: PP1000ConfigureFromFile and
> XHWIFcon.loadBitFile ?
>
> Thanks,
> Viv
>
>
Article: 30730My info is dated but: Harris (now intersil), Graychip, LSI Logic, TRW (Raytheon), GEC Plessey all make or made FIR chips. None are as flexible or powerful as what you can do in an FPGA. Paul Teagle wrote: > > Hi, > > can any one point me towards some manufacturers of programmable FIR chips > (not Graychip or Intersil - I have data on them). I want to contrast > performance & price vs implementation in FPGAs. > > The sort of speeds & resolution I'm looking for a probably the killer - > 175MHz & 16 bits (yes I know, an FPGA really is the way to go, but, I gotta > look!) > > regards, > > Paul T. -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.comArticle: 30731
On Thu, 26 Apr 2001 06:37:58 GMT, William Lenihan <lenihan3we@earthlink.net> wrote: > >I've heard various concerns & comments raised about unusually large >power >supply currents before FPGA configuration is completed. What's the real >story on this issue .... there was an other thread around the 20th feb. I am told by a xilinx employee that an app note regarding this with some circuit suggestion will be posted on this newsgroup > >Are these current surges happening > ____ during power-up (as Vcc's ramp up) ? that is what I understand . A significant peak in current demand : if the supply cannot provide the demanded current , the device just sits there and does not go on to configuration . There is also a voltage vs time template for the time between 2ms & 50 ms in the data sheet (spartan ii , i have not checked the virtex) the required circuit in the previous thread suggested using a large capacitor at the input of a ldo and turning on the ldo when it's input voltage was stable . > ____ After Vcc ramp-up, but before configuration ? before ramp-up > ____ during configuration ? no > >Are these current surges happening on core Vcc(s) or I/O Vcc(s) or both from what i understand on the core vcc >? > Henri wireless@NOSPAMdacafe.com remove the nospam to use emailArticle: 30732
Zhen Luo schrieb: > > Hello, > > I am trying to map my design to a board (with VirtexE chip on that) with a > few SRAM banks. I need to both read and write the data from/to the SRAM. > Because of this, I am hoping to use input/output pins. I am trying to find a > core for the bidirectional I/O, but it seems there is not any. > > I would greatly appreciate it if you could share your experience with the > bidirectional I/O pins on VirtexE chips with me. I am wondering if the > following code fragments would be enough to let the tools know what I want. > Thanks a lot! > > bi_io <= out_reg when out_en = '1' > 'Z' when others; > > process (clock, reset) > begin > if (reset = '1') then > in_reg <= '0'; > out_reg <= '0'; > elsif (clock'event and clock = '1') then > out_reg <= some_internal_signal; > if (out_en = '0') then -- read from bio_io > in_reg <= bi_io; > end if; > end if; > end process; This is the right way. -- MFG FalkArticle: 30733
Hi, I am using the Altera PCI developement Kit (PCI-BOARD/A4E). It has 1 APEX20K400E device. But I don't know .... Is there any PCI core inside the FPGA or not ? Beaucse... 1>The sales told me, There are no PCI core in it and if I want I should may US10000 for Altera MageCore ! 2>on the other side. I download a file to the on board FLASH memory. (This file is under the Altera install directory. It is already there). After that, I can do PCI target write test from Altera's demo software !? ( the PCI slot DEVSEL pin has wavefor !!) BTW, How can I add my circuit into the FLASH file, and not erase that "core" ? AjackArticle: 30734
Hi I am trying to simulate a biodirection port, however the simulation result is always not right IO is my bidirection port Here is my script file: wfm CLK @0=0 5ns=1 15ns=0 assign EN 1 wfm IO @0=ABCD\H 120=F\H wfm RW @0=0 200=1 sim 40ns time =20ns release IO When RW=1 at 20ns, I hope IO could be the Value of Q, so I release IO at 20ns however the simulator says" Illegal Macro name time" What is wrong? Also usually how do u simulate such bidirection port? Thanks a lot!Article: 30735
"Helen Long" <madisonfff@usa.net> writes: > I have another question about it > I got the maxium clock frequency from the fe.log file, > There says that maxium frequency is **MHz > Does that mean the real maxium frequency is **Mhz? The maximum frequence the design _can_ run on without breaking. What it runs at is what you provide on the clock input. > I had an empty UCF file Bad. If you don't tell the tools what you want, you wont get it! Homann -- Magnus Homann, M.Sc. CS & E d0asta@dtek.chalmers.seArticle: 30736
Hello,
I am trying to map my design to a board (with VirtexE chip on that) with a
few SRAM banks. I need to both read and write the data from/to the SRAM.
Because of this, I am hoping to use input/output pins. I am trying to find a
core for the bidirectional I/O, but it seems there is not any.
I would greatly appreciate it if you could share your experience with the
bidirectional I/O pins on VirtexE chips with me. I am wondering if the
following code fragments would be enough to let the tools know what I want.
Thanks a lot!
bi_io <= out_reg when out_en = '1'
'Z' when others;
process (clock, reset)
begin
if (reset = '1') then
in_reg <= '0';
out_reg <= '0';
elsif (clock'event and clock = '1') then
out_reg <= some_internal_signal;
if (out_en = '0') then -- read from bio_io
in_reg <= bi_io;
end if;
end if;
end process;
Article: 30737Hi, I have a question about the timing constraint in Xilinx Virtex II. I have 8 DFF outputs going to output pads, and how can I make the clock to pad delay about the same for all these 8 outputs? Thanks a lot.Article: 30738
Well, You use the global clock to clock the FF's. In Virtex II, the global clock nets are engineered to have less than +/- 100 ps of skew from any FF IOB clock pin from a global clock bus, to any pad on any package. In the largest devices (>2V4000) the skew is nominally larger (+/- 120ps). There is no advantage to keeping the IOB's near each other, other than the obvious routing advantage of traces escaping the area of the part. This includes the package trace flight time differences as well. I know the trace report will say "400 ps" but that is only because we have not finished all speeds file parameters based on silicon which we have received and tested. The reason for all of this wonderful matching is apparent when you implement a 16 bit clock forwarded DDR interface operating at 622 Mb/s. Austin FPGA Lab Manager Xilinx tiderh wrote: > Hi, > I have a question about the timing constraint in Xilinx Virtex II. I have 8 DFF outputs going to output pads, and how can I make the clock to pad delay about the same for all these 8 outputs? > Thanks a lot.Article: 30739
maybe your FPGA could recive its code via a configuration device (EPC2 or a PLD with a eeprom hanginging off it) and you could build in a funtion of your pci fpga - maybe some set target memory that you could load with new code that would realy get put in your configuration device ready for your next reboot? cyber_spook mike wrote: > hi all, > i want to configure my fpga on a pci card via the jtag pins > on the pci connector, but i dont know how to access these pins. > can you help me? > mikeArticle: 30740
I am having a problem with my XESS XS40 board and making a UCF file in XILINX Foundation. I've gotten my design to synthesize properly using 2 input pins I described in my user constraints file (UCF), but when I try to add another input pin, I get the following WARNING during the synthesis phase: "Dpm: Warning: Port 'rdin' has no net attached to it- no pad cells inserted at this port. (FPGA-PADMAP-2) And when I try to implement the design, I get the following ERROR: "ERROR:NgdHelpers:18 - Could not find NET "rdin" in design "newcnt3". NET entry is "NET rdin LOC=P28;" However, the input is described in my verilog file (along with 2 other inputs) as follows: "module top (clkin, data_out, reset, rdin); //BEGIN (TOP) parameter n = 17; input clkin; input reset; input rdin;" and in my UCF file as follows: "NET reset LOC = P44; NET clkin LOC=P13; NET rdin LOC=P28;" so I'm not exactly sure what the problem is, since the reset and clkin inputs worked just fine with no errors, but when I added rdin, I started getting this error, Any help would be greatly appreciated. VikArticle: 30741
You are only 'allowed' one signal source/destination connected to (most) each PCI signal. You would have to use a bridge... Unless it's in an embedded system, you really don't want to break the rules. "cyber_spook" <pjc@cyberspook.freeserve.co.uk> wrote in message news:3AE8879E.17752893@cyberspook.freeserve.co.uk... > maybe your FPGA could recive its code via a configuration device (EPC2 > or a PLD with a eeprom hanginging off it) and you could build in a > funtion of your pci fpga - maybe some set target memory that you could > load with new code that would realy get put in your configuration device > ready for your next reboot? > > cyber_spook > > mike wrote: > > > hi all, > > i want to configure my fpga on a pci card via the jtag pins > > on the pci connector, but i dont know how to access these pins. > > can you help me? > > mike >Article: 30742
> "cyber_spook" <pjc@cyberspook.freeserve.co.uk> wrote in message
> news:3AE8879E.17752893@cyberspook.freeserve.co.uk...
> > maybe your FPGA could recive its code via a configuration device (EPC2
> > or a PLD with a eeprom hanginging off it) and you could build in a
> > funtion of your pci fpga - maybe some set target memory that you could
> > load with new code that would realy get put in your configuration device
> > ready for your next reboot?
> >
"Austin Franklin" <austin@dark87room.com> wrote in message
news:9caid1$8m6$1@nntp9.atl.mindspring.net...
> You are only 'allowed' one signal source/destination connected to (most)
> each PCI signal. You would have to use a bridge... Unless it's in an
> embedded system, you really don't want to break the rules.
No need to use a bridge. One merely needs to have two sets of
configuration data on the card, and a mode to change from the first to the
second.
Configuration number one will be non-volatile, and used to boot the card.
It
will contain a PCI core, and only three functions:
Say "hello" to BIOS for allocation of resources at boot.
Read/Write conguration memory two from PCI bus.
Kickstart configuration from memory number two.
Configuration number two contains whatever you want it to, and could be
stored in a more volatile fashion, i.e. Parallel SRAM. I would boot from a
XC17xx prom, and use a small CPLD and an SRAM for the second config.
The only extra overhead that your additional configs will have to carry, is
the ability to kickstart configuration from the serial prom.
Painless reconfigurable computing. If one will be constantly switching
between configurations, just make the SRAM larger, and give every config
the ability to tell the config controller which configuration to use for the
next kickstart.
Config controller will fit a <$2 XC9536. No need for the JTAG port. No
bridge chip required. The SRAM/CPLD/XC17xx xolution is much cheaper
than those flash based config devices. And, best of all, no rules were
broken.
Regards,
Erik Widding.
--
Birger Engineering, Inc. -------------------------------- 781.481.9233
38 Montvale Ave #260; Stoneham, MA 02180 ------- http://www.birger.com
>
> > cyber_spook
> >
> > mike wrote:
> >
> > > hi all,
> > > i want to configure my fpga on a pci card via the jtag pins
> > > on the pci connector, but i dont know how to access these pins.
> > > can you help me?
> > > mike
> >
>
>
Article: 30743Hi I have a series of register,they share one date bus. according different addresses& RW signal, I can read/write data into different registers, so my data bus is bidirection, I have implemented a macro for such register, macro works fine however I could not implement it in Xilinx Foundation 3.liArticle: 30744
Hi! I remember some time ago here was a thread about getting Modelsim license. Now I have the same problem, I get only an e-mail from Xilinx where they thank me for registering, but no license. Tried twice, nothing. I remember also that about 4 months ago I was getting the license for Modelsim starter the same way, everything worked fine then, now I need license for Modelsm XE evaluation version. Has anybody any suggestions? Thanx, MeelisArticle: 30745
Hello, What exactly does mean: back annotation?Could you explain me on any example? Best regards Tomek T.Brychcy@ime.pz.zgora.plArticle: 30746
Hello, What is diferrence between cascaded logic and balanced logic? I greet Tomek T.Brychcy@ime.pz.zgora.plArticle: 30747
Hi Jeff Try using: after 20ns do (release SignalName) Best regards ivarArticle: 30748
Hi All, Could you help me for this issue? Virtex-II Data sheet show the Tiockp=3.73ns max (Ver.1.5). But the Timing Analyzer show the Tiockp=8.003ns (Tool: F3.3i SP7). Which is correct? Thanks Jinhua LiArticle: 30749
Hi ! We have a PCI board with one Virtex (for PCI) and one VirtexE (for LVDS) on it. Its running well, but it would be nice to eliminate one of the two chips. I know the VirtexE IO-pins are not 5V tolerant, you have to use a 100 ohm series resistor. This fact doesn't allow the use of VirtexE in 5V signaling PCI environments since these resistors are not allowed by the PCI specification. Now my question: Nevertheless, has anyone of you tried to run a VirtexE with series resistors in a 5V PCI slot ? Is this only violating the specs but running quite stable or will this cause face serious signal integrity problems ? Reagrds, Tobias PS: We dont have to get the "PCI compliant" sticker but the board shold run very stable.
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