Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
"Nial Stewart" <nials@sqf.hp.com> wrote in message news:3AED9371.6995F471@sqf.hp.com... > > Greg Deuerling wrote: > > > In article <3AECBB59.2C68BF6D@iprimus.com.au>, rjshaw@iprimus.com.au says... > > > > AHDL is *much* better than VHDL. > ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ > > But what happens if you decide to target a Xilinx device? > (SpartanII devices are cheap, provide a lot of resource > and the web pack software's free too). In the Xilinx Alliance and Foundation software there is a utility for translating AHDL and ABEL files to VHDL or Verilog. I have not actually used this utility on a complete design, so I will not vouch for it. It is called XPORT.EXE and is located in \xilinx\bin\nt. But from the brief tests that I did on relatively simple files, it appears to work quite well. I have no knowledge if this utility exists in the web pack software, but a basic Xilinx license, for the smallest parts is about $95. This said, I still would not recommend doing new designs using ABEL or AHDL. Regards, Erik Widding. -- Birger Engineering, Inc. -------------------------------- 781.481.9233 38 Montvale Ave #260; Stoneham, MA 02180 ------- http://www.birger.comArticle: 30851
"M.B." <martinb@magma.ca> wrote in message
news:3aeeb905.4091345@news.magma.ca...
> Hi I have a telescope and some basic experiance with VHDL, FPGAs.
> I would like to get a CCD (something common and cheap) and use a FPGA
> perhaps a xilinx or atmel with VHDL. and interface to my computer (win
> 98.
CMOS sensors are generaly easier to work with, as many provide digital
instead of analog pixels out, and TTL levels in. But they do come with
their own anomolies, which many applications can not tolerate:
Rolling shutter (not all of the array gets exposed at the same time)
Higher noise for longer exposures.
HP/Agilent, PhotoBit, FillFactory, all make CMOS sensors. You mentioned a
telescope, so I will assume that you are interested in astronomy and long
exposures. For this, an inexpensive CMOS sensor will just not do. The
maximum exposure for a CMOS sensor is generally less than a second or two.
If you choose a CCD sensor, Phillips and Exar both make very easy to use
analog front end chips that incorporate corelated double sampling, analog to
digital conversion and programmable gain control all in one chip. You will
also have to add level translators to drive the multiphase, and often
multi-level clocks on the CCD. For further information on electronics to
drive the CCD: Philips has some good ap-notes; and Sony data sheets are good
source as well.
> Has anyone done somthing like this?
> Is there a project in any books or wed sites that you have seen that
> could get me started?
>
> Or is there a development kit from one of the CCD Manufacturers that I
> could look into?
The development kits tend to be very expensive. It is usually cheaper to
buy a commercially available camera than a development kit. But often the
designs for the development kits are posted on the manufacturers web sites,
so you may be able to gain some valuable insight.
Regards,
Erik Widding.
--
Birger Engineering, Inc. -------------------------------- 781.481.9233
38 Montvale Ave #260; Stoneham, MA 02180 ------- http://www.birger.com
Article: 30852Greg Deuerling wrote: > I plan to use Foundation and a SpartanII comming up. Altera really > lost me as a high end FPGA customer when they put out that load of > crap called Quartus. They should have left MaxPlusII alone, it was > simple, fast, and easy to use. I'll get used to using VHDL, but I'll > NEVER like it, and wish I was using AHDL. Greg, You must have had one of the early releases of Quartus, I think it's much more stable now. I haven't used it for about a year now, but even then I had no problems (it was on an NT box). The Xilinx tools are a bit more mature, but I'm sure they'd problems initially. Nial.Article: 30853
Dave Feustel wrote: > I just got an Atmel FPSLIC starter kit containing a > microprocessor and a dynamically programmable > FPGA. I've looking for other companies that make > similar kits, but so far the other kits have little documentation, > cost too much or are simply not yet available. XESS makes a kit for the Triscend TE5 CSoC. It has a complete tutorial, a full version of the Triscend FastChip 1999 software, and a price of $169.95. It has been available for about 9 months. You can see it at http://www.xess.com/prod022.php3. > > > "Shawki Areibi" <sareibi@uoguelph.ca> wrote in message news:3AE442E8.7FCEAF58@uoguelph.ca... > > hi, I was wondering if someone knew about companies that sell FPGA > > prototyping kits for dynamically reconfigurable FPGAs (preferably XILINX > > > > since our students are using the XESS XS40). > > Also are there companies that develops kits for Atmel FPSLIC that > > combines > > FPGA with a microcontroller. > > I would really appreciate your comments and experience in this field > > PS: We would like to use the platforms to map Neural Net Algorithms > > on the FPGAs > > You can email me directly at sareibi@uoguelph.ca > > Shawki > > -- > > Shawki Areibi > > Assistant Professor > > School of Engineering > > University of Guelph > > Guelph, Ont, Canada N1G 2W1 > > Tel: (519) 824-4120 > > Fax: (519) 836-0227 > > > > -- || Dr. Dave Van den Bout XESS Corp. (919) 387-0076 || || devb@xess.com 2608 Sweetgum Dr. (800) 549-9377 || || http://www.xess.com Apex, NC 27502 USA FAX:(919) 387-1302 ||Article: 30854
"Austin Lesea" <austin.lesea@xilinx.com> wrote in message news:3AEDB258.DE79F5F7@xilinx.com... > Kevin, <<snip>> > All bits must be included in the channel. How else do you get them at the other > end? They too, may be in error. A rate 1/2 code means that twice as many bits > are in the channel, so that is a horrendously inefficient code (it cuts in half > your through put). > I do not agree. I'm not sure I understand Austin correctly, but assuming you are sending packets of 10 bytes each followed by 2 bytes of CRC then, it is my understanding that, you should NOT count the CRC bytes into the channel capacity C. The reason being that the CRC bits do not contribute information, they are fully predictable. The channel capacity, as far as I remember from school many years ago :)), measures the "information" flow per unit time. If all transmitted bits are completely random, then the capacity equals the bit rate. Adding fully predictable bits [FEC, CRC, constants! or otherwise predictable] does not increase the information content of your message, and therefore does not require additional channel capacity. Note that you can send 10Mbit/s of zeros through a completely "blocked" channel (S/N = 0) and recover all zeros without error, if you know that you should expect zeros! A less "trivial" or stupid example is the coding used over bad audio links, e.g. radio, where entire words are used instead of letters [alpha = a, bravo = b, charlie = c, ... zulu = z]. In this case, each word has the information content of just a single letter. Most text books about communication systems have a section about the Shannon limit. The one I have hany explains it quite well. "Digital and Analog Communication Systems", by Leon W. Couch II, published by Macmillan Publishing Company. Hope this helps, Berni. > > Kevin Neilson wrote: > > > There's something I've never quite understood about Shannon's Law. It > > states something like this: > > > > C = W*logbase2(1 + S/N) > > > > where C is channel capacity, bits/s > > W = bandwidth, Hz > > S/N = signal-to-noise ratio > > > > Theoretically, if using enough error-correction, you can transmit C bits/s > > on a channel error-free. > > > > Say you determine that the channel capacity for a particular channel is > > 1Mbit/s. Does that include the error correction bits or not? What if you No, don't include the error correction bits. > > have a 1/2 rate code, where half of the bits are parity bits. Does that > > mean you transmit 2Mbit on that channel (with 1Mbit capacity) for a net data > > throughput of 1Mbit error-free? Or does the 1Mbit include the partiy bits? 2Mbit/s of which 1Mbit/s is error correction is compatible with a 1Mbit/s channel. But Shannon won't tell you how to code it! He just says it is not impossible. > > > > -Kevin >Article: 30855
See what I mean? Still confused after all these years. If the CRC is not information, then you don't need it. If the CRC is information, then you need to send it. I rest my case. Austin Berni Joss wrote: > "Austin Lesea" <austin.lesea@xilinx.com> wrote in message > news:3AEDB258.DE79F5F7@xilinx.com... > > Kevin, > > <<snip>> > > > All bits must be included in the channel. How else do you get them at > the other > > end? They too, may be in error. A rate 1/2 code means that twice as > many bits > > are in the channel, so that is a horrendously inefficient code (it cuts > in half > > your through put). > > > > I do not agree. > > I'm not sure I understand Austin correctly, but assuming you are sending > packets of 10 bytes each followed by 2 bytes of CRC then, it is my > understanding that, you should NOT count the CRC bytes into the channel > capacity C. > The reason being that the CRC bits do not contribute information, they are > fully predictable. > > The channel capacity, as far as I remember from school many years ago :)), > measures the "information" flow per unit time. If all transmitted bits are > completely random, then the capacity equals the bit rate. > Adding fully predictable bits [FEC, CRC, constants! or otherwise > predictable] does not increase the information content of your message, and > therefore does not require additional channel capacity. > > Note that you can send 10Mbit/s of zeros through a completely "blocked" > channel (S/N = 0) and recover all zeros without error, if you know that you > should expect zeros! > A less "trivial" or stupid example is the coding used over bad audio links, > e.g. radio, where entire words are used instead of letters [alpha = a, > bravo = b, charlie = c, ... zulu = z]. In this case, each word has the > information content of just a single letter. > > Most text books about communication systems have a section about the > Shannon limit. The one I have hany explains it quite well. "Digital and > Analog Communication Systems", by Leon W. Couch II, published by Macmillan > Publishing Company. > > Hope this helps, > Berni. > > > > > Kevin Neilson wrote: > > > > > There's something I've never quite understood about Shannon's Law. It > > > states something like this: > > > > > > C = W*logbase2(1 + S/N) > > > > > > where C is channel capacity, bits/s > > > W = bandwidth, Hz > > > S/N = signal-to-noise ratio > > > > > > Theoretically, if using enough error-correction, you can transmit C > bits/s > > > on a channel error-free. > > > > > > Say you determine that the channel capacity for a particular channel is > > > 1Mbit/s. Does that include the error correction bits or not? What if > you > > No, don't include the error correction bits. > > > > have a 1/2 rate code, where half of the bits are parity bits. Does > that > > > mean you transmit 2Mbit on that channel (with 1Mbit capacity) for a net > data > > > throughput of 1Mbit error-free? Or does the 1Mbit include the partiy > bits? > > 2Mbit/s of which 1Mbit/s is error correction is compatible with a 1Mbit/s > channel. But Shannon won't tell you how to code it! He just says it is not > impossible. > > > > > > > -Kevin > >Article: 30856
Hi, We´re an University searching team and we´re working on FPGA technology. We´ve developed a program to be downloaded into our FPGA desing by the Xchecker cable. Now, we´d like to keep our program in a PROM. But, unfortunately, we don´t know how to translate our FPGA file into a PROM file to be downloaded to the PROM. We´re looking for information about a translator program (SW) and any useful tips related to that. Do you know something about that? Would you mind helping us? Thank you so much for your help!. Best regards, Segismundo Alonso P.S. Send your reply to segisweb@jazzfree.comArticle: 30857
I'm glad as both a good VHDL Hardware engineer with *many* years of C under my belt that I'm not afended by what you have written. I think that mush of your comments regarding softies is true of the Uni manufactuared engineers that have no understanding of a microcomputer system However I would like to point out that there are a LARGE number of software engneers (Embeded) that are very good. Some time ago I had never touched VHDL but found it very easy to pick up having a understanding of hardware AND software 'C'. I now work with hardware engineers that have no software experiance - and I find that my software experiance has helped us look at different approches to solving a problem. Also - as you may have guessed from my spelling - I'm dislexic! This belive it or not has also give me an advantage. I was once told that there are more left handed hardware than softies (Lefties have a similur brain layout as dislexics), is this true? cyber_spook Austin Franklin wrote: > > > > Anyway, I'm convinved that the company will be better off teaching HW > > > > design to the programmer. If he's a good programmer, that wont be a > > > > big problem. > > > > > > I have learned programmers do not necessarily make good hardware > engineers. > > > It is a different mind set and discipline. There is much background > that is > > > not required for programming that is required for digital design. > > > > Depends on how you define a good programmer... :-) > > > > I'm curious what you mean when you say "make". Does that mean before > > or after appropriate training? > > I do not believe most are trainable ;-) > > Digital engineering requires a certain mind-set. There are obviously, some > very good programmers out in the world. For the most part, it is not near > as skilled a task as hardware engineering, IMO. Programming languages are > but a tool. You can be a pretty lousy programmer, and still create a > program that, well, 'works'. That is not necessarily true with hardware > engineering. This is why I question generally calling programmers, > engineers. I do not see the engineering in most cases. That is not to say > some aren't great engineers, but in general, most are not.Article: 30858
Ok, I was not that clear when I wrote the first message. I want to measure the time of a pulse between two pulses. The pulses are not periodic, ie I can not phase lock to the pulses. (The pulses origin from an ultra sonic flow meter application). I understand that I need a counter to count the number of clock cycles. But I need better accuracy than 1/F... in an ASIC I would probably design a ring oscillator in order to get at high frequency clock. But as far as I know this is not recommended in a FPGA. Instead I was thinking of using multiple phases of the reference clocks derived from a DLL inside a Virtex II for instance. Btw I need to perform some arithmetics as well so a CPLD would not be an option here. Thanks! / Jonas On Wed, 2 May 2001 09:55:59 +0200, "Victor Schutte" <victors@mweb.co.za> wrote: >What do you want measure seconds, ms, us? This will determine the number of >bits in your counter. A 16 bit counter will only count from 0 to 65535. >Using a 10MHz clock you will get a range of about 6.5ms. A 32bit counter at >10MHz will give about 430 seconds window, but will chew up more gates. > >More accurate than 1/F? You will never get better than 1/F accuracy. To >get better than 1/F accuracy you will need multiple 1/Fs which will mean a >higher reference clock. If you need better than 1/10E6 you can use a higher >clock, such as 50MHz. This will give a 1/50E6 which is 5 times better than a >10MHz clock. > >FPGA? I don't think so. Rather use a CPLD. One flipflop for start and stop >(counter enable signal), nbit counter with clear and registered outputs. The >clock freq. can be much higher than a FPGA. It is also cheaper and easier to >use than a FPGA. Even the slowest 10ns CPLDs should do the trick. Look at >the Altera (don't actually know much of the Xilinx products) 7000MAX series. >For jobs like these I would recommend the MAX7128SLC84 -10. It is fast >enough, contains a decent amount of gates, is in-circuit programmable and >comes in an easy to use PLCC package(plus you can get free software over the >internet (www.altera.com )and build your own downloadcable for the price of >a hamburger).Article: 30859
Jonas Thor wrote: > Ok, I was not that clear when I wrote the first message. I want to > measure the time of a pulse between two pulses. The pulses are not > periodic, ie I can not phase lock to the pulses. (The pulses origin > from an ultra sonic flow meter application). Can you describe the pulses and the resolution that you need in a litte bit more detail? There was a patent on bountyquest a while ago that flattened the pulse so that the pulse edge was multiple clock cycles long. If you then sample the input pulse with an ADC you can use your ADC voltage resolution to achieve sub clock cycle timing resolution. The NA49 Experiment do somthing similar: They know that the pulse shape is gaussian. They can use this to obtain very high resolution. Kolja SulimmaArticle: 30860
Here is a small digital CMOS camera that you could interface to a FPGA: http://www.quasarelectronics.com/cmos_cameras.htm#cdc / Jonas Thor On Tue, 01 May 2001 13:33:08 GMT, martinb@magma.ca (M.B.) wrote: >Hi I have a telescope and some basic experiance with VHDL, FPGAs. >I would like to get a CCD (something common and cheap) and use a FPGA >perhaps a xilinx or atmel with VHDL. and interface to my computer (win >98. > >Has anyone done somthing like this? >Is there a project in any books or wed sites that you have seen that >could get me started? > >Or is there a development kit from one of the CCD Manufacturers that I >could look into? >Article: 30861
Jonas, Oh, that's completely different! A technique I see used today is the following: you start charging a capacitor from a very good regulated current source when the first edge occurs. You then sample (and hold) the voltage on the next pulse rising edge detected. The time between pulses is then found by knowing the current, the voltage difference, and the capacitance (dt = C * dv/I). Better is to start the charging before the first pulse, and sample the voltage at the first, and then on the next pulse (this requires using a fixed delay line so that you can start the process before the pulse even gets there). Such analog systems benefit from using 16 bit A/D's, sample and hold circuits, and frequent auto-calibration cycles based on fixed known reference clocks. I have seen systems like this achieve +/- 3 ps resolution in pulse to pulse measurement over many pulses. Controlling jitter becomes a big problem, and some averaging is done to get these kinds of results. I doubt you could do much better than +/- 30 ps on a single pulse measurement without some serious expensive engineering and components. Austin Jonas Thor wrote: > Ok, I was not that clear when I wrote the first message. I want to > measure the time of a pulse between two pulses. The pulses are not > periodic, ie I can not phase lock to the pulses. (The pulses origin > from an ultra sonic flow meter application). > > I understand that I need a counter to count the number of clock > cycles. But I need better accuracy than 1/F... in an ASIC I would > probably design a ring oscillator in order to get at high frequency > clock. But as far as I know this is not recommended in a FPGA. Instead > I was thinking of using multiple phases of the reference clocks > derived from a DLL inside a Virtex II for instance. > > Btw I need to perform some arithmetics as well so a CPLD would not be > an option here. > > Thanks! > > / Jonas > > On Wed, 2 May 2001 09:55:59 +0200, "Victor Schutte" > <victors@mweb.co.za> wrote: > > >What do you want measure seconds, ms, us? This will determine the number of > >bits in your counter. A 16 bit counter will only count from 0 to 65535. > >Using a 10MHz clock you will get a range of about 6.5ms. A 32bit counter at > >10MHz will give about 430 seconds window, but will chew up more gates. > > > >More accurate than 1/F? You will never get better than 1/F accuracy. To > >get better than 1/F accuracy you will need multiple 1/Fs which will mean a > >higher reference clock. If you need better than 1/10E6 you can use a higher > >clock, such as 50MHz. This will give a 1/50E6 which is 5 times better than a > >10MHz clock. > > > >FPGA? I don't think so. Rather use a CPLD. One flipflop for start and stop > >(counter enable signal), nbit counter with clear and registered outputs. The > >clock freq. can be much higher than a FPGA. It is also cheaper and easier to > >use than a FPGA. Even the slowest 10ns CPLDs should do the trick. Look at > >the Altera (don't actually know much of the Xilinx products) 7000MAX series. > >For jobs like these I would recommend the MAX7128SLC84 -10. It is fast > >enough, contains a decent amount of gates, is in-circuit programmable and > >comes in an easy to use PLCC package(plus you can get free software over the > >internet (www.altera.com )and build your own downloadcable for the price of > >a hamburger).Article: 30862
HELLO, I AM LOOKING FOR A FREE USB (v.2.0) CORE WRITTEN IN VHDL. REGARDS GR -- Posted from 217.32.135.174 by way of mercury.ukc.ac.uk [129.12.21.10] via Mailgate.ORG Server - http://www.Mailgate.ORGArticle: 30863
The macrocells in a FPGA vs the xOPS of a DSP/uP don't really allow comparison of the performance achievable with an optimised algorithm, it all depends on what you are trying to achieve. If the algorithm can be written to use massive data parallelism or instruction parallelism (pipelining) then the benefit in favour of the FPGA can easily be 1000-10,000:1. There are applications (for example a 30gbit/s memory bus and image pre-processor, for radar, sonar, CAT or whatever) that require a single FPGA or ASIC but would require 3,000+ DSPs to achieve the i/o bandwidth and process every data pair. In a more normal application the benefit of the FPGA is much smaller, and the system cost: $300 for a DSP and support chips, $2000 for a P4 and support chips, $1000 for a FPGA; and speed of implementation become much more important. DaveArticle: 30864
I should also have added: If the algorithm requires a lot of branching with if,then,elses or case structures then the execution speed advantage usually lies with a RISC processor maybe 10:1 over a FPGA, and it would be normal to purchase a RISC core and include it in your FPGA or ASIC. DaveArticle: 30865
> However I would like to point out that there are a LARGE number of software > engneers (Embeded) that are very good. I absolutely agree. Just like realtors and lawyers, there are some good ones out there. > Some time ago I had never touched VHDL but found it very easy to pick up having > a understanding of hardware AND software 'C'. I now work with hardware > engineers that have no software experiance - and I find that my software > experiance has helped us look at different approches to solving a problem. Agreed. I believe a top notch engineer will be fluent in both hardware and software, in order to design hardware systems that are better designed. There is some hardware engineering that does not benefit from this, but most, today, does.Article: 30866
Erik Widding wrote: > > "Nial Stewart" <nials@sqf.hp.com> wrote in message > news:3AED9371.6995F471@sqf.hp.com... > > > Greg Deuerling wrote: > > > > In article <3AECBB59.2C68BF6D@iprimus.com.au>, rjshaw@iprimus.com.au > says... > > > > > AHDL is *much* better than VHDL. > > ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ > > > > But what happens if you decide to target a Xilinx device? > > (SpartanII devices are cheap, provide a lot of resource > > and the web pack software's free too). > > In the Xilinx Alliance and Foundation software there is a utility for > translating AHDL and ABEL files to VHDL or Verilog. I have not actually > used this utility on a complete design, so I will not vouch for it. It is > called XPORT.EXE and is located in \xilinx\bin\nt. But from the brief tests > that I did on relatively simple files, it appears to work quite well. I > have no knowledge if this utility exists in the web pack software, but a > basic Xilinx license, for the smallest parts is about $95. > > This said, I still would not recommend doing new designs using ABEL or AHDL. Is that $95 permanent, or only for one year? Over here, that'll be AUS$200. -- ___ ___ / /\ / /\ / /__\ / /\/\ /__/ / Russell Shaw, B.Eng, M.Eng(Research) /__/\/\/ \ \ / Victoria, Australia, Down-Under \ \/\/ \__\/ \__\/Article: 30867
Austin Lesea wrote: > Pioneer 10 just went beyond the capacity of its ever changing and adapting > channel. For years now, scientists and mathemeticians have uploaded new error > correction encoding schemes to Pioneer 10 while it flew out of our Solar > System. Who is to say that with a little more work, they couldn't talk to it a > little longer? Pioneer 10 Mission Status April 29, 2001 Distance from Sun : 77.67 AU Speed relative to the Sun: 12.24 km/sec (27,380 mph) Distance from Earth: 11.74 billion kilometers (7.29 billion miles) Round-trip Light Time: 21 hours 45 minutes Good News!! Pioneer 10 lives on. At GMT 17:27:30, Saturday, 4/28/01, the signal from Pioneer 10 was received at station 63 in Madrid, the first time since August 19 of last year. As Samuel Clemens (AKA Mark Twain) once reported to the newspaper - "The report of my death was an exaggeration" could be applied to the premature reports of the demise of Pioneer 10. -- rk "There is nothing like real data stellar engineering, ltd. to f' up a great theory." stellare@erols.com.NOSPAM -- me, circa 1995 Hi-Rel Digital Systems DesignArticle: 30868
Does anyone know of where I can find a free Verilog source code for a Serial UART that can be used in a Xilinx XC4005XL FPGA? I am in need of such code to add to a FPGA design I am making for remote access to the FPGA CPU... Thanks, MarkArticle: 30869
David Abbott wrote: > > I should also have added: If the algorithm requires a lot of > branching with if,then,elses or case structures then the execution > speed advantage usually lies with a RISC processor maybe 10:1 over > a FPGA, and it would be normal to purchase a RISC core and include > it in your FPGA or ASIC. Hmm, I'm not conviced about that. I still think an FPGA design would win on speed. But IMHO all this talk of which is faster misses one important point. For real designs you're not trying to exploit every possible opportunity for parallelisation in order to score brownie points in some arbitrary benchmark competition. What you're trying to do is implement the most economic solution (in terms of gate/interconnect/power consumption say) which gives you the speed required by the application. This seems like a much harder problem to me, especially if you want to automate this process so you don't have to manually design 10 different FFT processor architectures, each offering a different solution to the speed vs. cost equation. Regards -- Adrian HeyArticle: 30870
A similar technique is time stretching. It is used for example by LeCroy. You charge a capacitor during the time interval that you want to measure. Then you discharge using a smaller current source an measure that time. The main advantage is that you do not need to control the capacitor value very acurately. Also, if you want to get the accuracies that Austin is talking about, you would probably need oven stabilization, that is heating all critical components to a known temperature. Kolja Austin Lesea wrote: > Jonas, > > Oh, that's completely different! > > A technique I see used today is the following: you start charging a capacitor > from a very good regulated current source when the first edge occurs. You then > sample (and hold) the voltage on the next pulse rising edge detected. The time > between pulses is then found by knowing the current, the voltage difference, and > the capacitance (dt = C * dv/I). Better is to start the charging before the > first pulse, and sample the voltage at the first, and then on the next pulse > (this requires using a fixed delay line so that you can start the process before > the pulse even gets there). > > Such analog systems benefit from using 16 bit A/D's, sample and hold circuits, > and frequent auto-calibration cycles based on fixed known reference clocks. > > I have seen systems like this achieve +/- 3 ps resolution in pulse to pulse > measurement over many pulses. Controlling jitter becomes a big problem, and some > averaging is done to get these kinds of results. I doubt you could do much > better than +/- 30 ps on a single pulse measurement without some serious > expensive engineering and components. > > Austin > > Jonas Thor wrote: > > > Ok, I was not that clear when I wrote the first message. I want to > > measure the time of a pulse between two pulses. The pulses are not > > periodic, ie I can not phase lock to the pulses. (The pulses origin > > from an ultra sonic flow meter application). > > > > I understand that I need a counter to count the number of clock > > cycles. But I need better accuracy than 1/F... in an ASIC I would > > probably design a ring oscillator in order to get at high frequency > > clock. But as far as I know this is not recommended in a FPGA. Instead > > I was thinking of using multiple phases of the reference clocks > > derived from a DLL inside a Virtex II for instance. > > > > Btw I need to perform some arithmetics as well so a CPLD would not be > > an option here. > > > > Thanks! > > > > / Jonas > > > > On Wed, 2 May 2001 09:55:59 +0200, "Victor Schutte" > > <victors@mweb.co.za> wrote: > > > > >What do you want measure seconds, ms, us? This will determine the number of > > >bits in your counter. A 16 bit counter will only count from 0 to 65535. > > >Using a 10MHz clock you will get a range of about 6.5ms. A 32bit counter at > > >10MHz will give about 430 seconds window, but will chew up more gates. > > > > > >More accurate than 1/F? You will never get better than 1/F accuracy. To > > >get better than 1/F accuracy you will need multiple 1/Fs which will mean a > > >higher reference clock. If you need better than 1/10E6 you can use a higher > > >clock, such as 50MHz. This will give a 1/50E6 which is 5 times better than a > > >10MHz clock. > > > > > >FPGA? I don't think so. Rather use a CPLD. One flipflop for start and stop > > >(counter enable signal), nbit counter with clear and registered outputs. The > > >clock freq. can be much higher than a FPGA. It is also cheaper and easier to > > >use than a FPGA. Even the slowest 10ns CPLDs should do the trick. Look at > > >the Altera (don't actually know much of the Xilinx products) 7000MAX series. > > >For jobs like these I would recommend the MAX7128SLC84 -10. It is fast > > >enough, contains a decent amount of gates, is in-circuit programmable and > > >comes in an easy to use PLCC package(plus you can get free software over the > > >internet (www.altera.com )and build your own downloadcable for the price of > > >a hamburger).Article: 30871
The OV7620 evaluation module by omnivision is about 25% less expensive. Jonas Thor wrote: > Here is a small digital CMOS camera that you could interface to a > FPGA: > > http://www.quasarelectronics.com/cmos_cameras.htm#cdc >Article: 30872
Hi all, I'am currently designing a PC104 slave card, and for cost reasons I use an Xilinx Spartan-XL housed in a TQFP144 having 112 IO's available. Well some of these 112 IO's are a little bit tricky to use, since for example JTAG is on this pins also... Actually I'am running out of pins, and now I just wanna make shure that I do NOT connect any redundant information on that FPGA ...Now the Questions: The Slave Card has 8 Bit read/write capability for the IO-Section and 16 Bit only for the memory section. Location for the memory section can be somewhere in the 16Meg area of the isa bus. -- We have SA[0..19] and LA[17..23] I now that LA may be driven earlier, but do I need both SA[17..19] and LA[17..19]?? -- We do have standard memory read/write signals on the XT part of the connector and two other signals memory read/write on the AT part of the connector. Is that not redundant information here?? Any hint, help would be appreciated ... markus ******************************************************************** ** Meng Engineering Telefon 056 222 44 10 ** ** Markus Meng Natel 079 230 93 86 ** ** Bruggerstr. 21 Telefax 056 222 44 10 ** ** CH-5400 Baden Email meng.engineering@bluewin.ch ** ******************************************************************** ** Theory may inform, but Practice convinces. -- George Bain **Article: 30873
On Mon, 30 Apr 2001 17:03:09 GMT, "Kevin Neilson" <kevin_neilson@yahoo.com> wrote: >There's something I've never quite understood about Shannon's Law. It >states something like this: > >C = W*logbase2(1 + S/N) > >where C is channel capacity, bits/s > W = bandwidth, Hz > S/N = signal-to-noise ratio > >Theoretically, if using enough error-correction, you can transmit C bits/s >on a channel error-free. > >Say you determine that the channel capacity for a particular channel is >1Mbit/s. Does that include the error correction bits or not? What if you No, the 1 MBit/s its the rate for usable information. >have a 1/2 rate code, where half of the bits are parity bits. Does that >mean you transmit 2Mbit on that channel (with 1Mbit capacity) for a net data >throughput of 1Mbit error-free? Or does the 1Mbit include the partiy bits? > >-Kevin > You must not think in terms of parity and CRC, Shannons law applies to a much more generic principle. It states, that given a noisy channel (where the signals at the end of the channel are not in their ideal form anymore, but there is some added noise), you are not able to exceed the information rate C. The used information coding scheme in the channel it's at your decision and you can and will use any trick you want. (AM, FM, QA[Modulation], Viterbi coding ....). Best regards. Klaus Falser Klaus R&D Electronics Department Company : Durst Phototechnik AG Vittorio Veneto Str. 59 I-39042 Brixen Voice : +0472/810235 : +0472/810111 FAX : +0472/830980 Email : kfalser@IHATESPAMdurst.itArticle: 30874
On Tue, 1 May 2001 20:42:08 +0200, "Berni Joss" <berni_13@yahoo.com> wrote: > >"Austin Lesea" <austin.lesea@xilinx.com> wrote in message >news:3AEDB258.DE79F5F7@xilinx.com... >> Kevin, > ><<snip>> > >> All bits must be included in the channel. How else do you get them at >the other >> end? They too, may be in error. A rate 1/2 code means that twice as >many bits >> are in the channel, so that is a horrendously inefficient code (it cuts >in half >> your through put). >> > >I do not agree. > >I'm not sure I understand Austin correctly, but assuming you are sending >packets of 10 bytes each followed by 2 bytes of CRC then, it is my >understanding that, you should NOT count the CRC bytes into the channel >capacity C. >The reason being that the CRC bits do not contribute information, they are >fully predictable. > >The channel capacity, as far as I remember from school many years ago :)), >measures the "information" flow per unit time. If all transmitted bits are >completely random, then the capacity equals the bit rate. >Adding fully predictable bits [FEC, CRC, constants! or otherwise >predictable] does not increase the information content of your message, and >therefore does not require additional channel capacity. > >Note that you can send 10Mbit/s of zeros through a completely "blocked" >channel (S/N = 0) and recover all zeros without error, if you know that you >should expect zeros! In this case you can not talk about information anymore, at least not in the sense Shannon ment it. If you can expect a symbol with 100 % certainity you have no information at all. Your symbol rate however can be as high as you like. >A less "trivial" or stupid example is the coding used over bad audio links, >e.g. radio, where entire words are used instead of letters [alpha = a, >bravo = b, charlie = c, ... zulu = z]. In this case, each word has the >information content of just a single letter. > >Most text books about communication systems have a section about the >Shannon limit. The one I have hany explains it quite well. "Digital and >Analog Communication Systems", by Leon W. Couch II, published by Macmillan >Publishing Company. > >Hope this helps, >Berni. > > > > >> >> Kevin Neilson wrote: >> >> > There's something I've never quite understood about Shannon's Law. It >> > states something like this: >> > >> > C = W*logbase2(1 + S/N) >> > >> > where C is channel capacity, bits/s >> > W = bandwidth, Hz >> > S/N = signal-to-noise ratio >> > >> > Theoretically, if using enough error-correction, you can transmit C >bits/s >> > on a channel error-free. >> > >> > Say you determine that the channel capacity for a particular channel is >> > 1Mbit/s. Does that include the error correction bits or not? What if >you > >No, don't include the error correction bits. > >> > have a 1/2 rate code, where half of the bits are parity bits. Does >that >> > mean you transmit 2Mbit on that channel (with 1Mbit capacity) for a net >data >> > throughput of 1Mbit error-free? Or does the 1Mbit include the partiy >bits? > >2Mbit/s of which 1Mbit/s is error correction is compatible with a 1Mbit/s >channel. But Shannon won't tell you how to code it! He just says it is not >impossible. > >> > >> > -Kevin >> > > Falser Klaus R&D Electronics Department Company : Durst Phototechnik AG Vittorio Veneto Str. 59 I-39042 Brixen Voice : +0472/810235 : +0472/810111 FAX : +0472/830980 Email : kfalser@IHATESPAMdurst.it
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z