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This is really a moot discussion. There is no exact scientific relationship between an ASIC gate count and the logic implemented on a LUT-based FPGA. The value of a LUT can vary from 0 to 20 gates! And what's the value of a RAM bit? And what if it's dual-ported? No, I mean True Dual-Ported ! And there are lots of things ( DLLs, carry logic, multipliers, Clock multiplexers etc ) that would not show up in any "gate count". This leaves the field wide open to Creative Marketing, and the two main players try to outdo each other. If you want to compare different architectures and different manufacturers, forget about all gate counts, compare the number of LUTs and associated flip-flops, (Xilinx started the concept of Logic Cells years ago, Altera recently re-invented it) Then evaluate the "goodies": RAM, Carry, Multipliers, Clock Management, I/O flexibility, packaging options, etc. Check what it's worth to you. That is the only thing that counts. Device size cannot be represented by a single number. Even the Miss America contest has given up on their obsession about numbers. There is more to beauty than 38-24-36 (inches, not centimeters), and there is much more to an FPGA than "2 million gates", whatever a gate is supposed to be. "Gate count" is just a figure of goodness within any one product family. The more the bigger, and the more expensive... (Marketing loves me already.) Peter Alfke =============================== Vivek Sood wrote: > Virtex E system gate count mentioned in the data sheet is different from the one I found somewhere on the Xilinx website(Probably : FAQ's on Virtex E). In fact the system gates for Virtex E , mentioned in the article on the website was same as the system gates for Virtex(2.5 V), while they were different in the datasheet for Virtex E. > > Can anyone please tell me this disceperancy. Also how do you calculate the system gate count?I mean what % age of BRAM etc. The details in xapp #059 are for devices specifcally containing no BRAM . What about devices containing BRAM? > > Altera mentions in it's Datasheet Maximum system gate count which includes all ESB's used for memory and all LE's used for logic. What is the Xilinx equivalent for this??Article: 31201
Hi Peter, I completely agree with the tenor of you message, but I would like to comment on some of the issues: Peter Alfke wrote: > This is really a moot discussion. > There is no exact scientific relationship between an ASIC gate count and the logic implemented on a LUT-based FPGA. Hmm. There are some consistent Definitions. Most count the number of gate INPUTS when the circuit is represented by primitive gates. Usualy AND and OR gates, sometimes counting inverters, sometimes not. Sometimes XOR gates are allowed. By counting this way, a 2 input AND gate has a gate count of two. Twice of what most people would expect. An XOR is six gates when only AND and OR are allowed. > The value of a LUT can vary from 0 to 20 gates! 6 gates is a typical gate equivalent value for a flip-flop. This way you can pack 96 gates into a LUT in shift register mode :-) Thats probably a large portion of the gate discounting between XC4K and Virtex. > And what's the value of a RAM bit? And what if it's dual-ported? No, I mean True Dual-Ported ! > And there are lots of things ( DLLs, carry logic, multipliers, Clock multiplexers etc ) that would not show up in any "gate count". You are sure that the multipliers are not counting at a rate of 6 gates per XOR? (12 gates per full adder) > If you want to compare different architectures and different manufacturers, forget about all gate counts, compare the number of LUTs and associated flip-flops, (Xilinx started the concept of Logic Cells years ago, Altera recently re-invented it) Thats why marketing counts Slices, CLBs, logic-cells, ... Try to avoid using the same metric twice. > Then evaluate the "goodies": RAM, Carry, Multipliers, Clock Management, I/O flexibility, packaging options, etc. Check what it's worth to you. That is the only thing that counts. Then check the tools and find out, if you can use the feature that you need. The check the distributor to find out if the part is available in your country. > Device size cannot be represented by a single number. Kolja SulimmaArticle: 31202
Duane Clark wrote: > > Has anyone used both? I'm used to the Xilinx toolchain and devices > > but a client wants a project done using Actel antifuse. Are there any > > objective comparisons anywhere on the web or does anyone have any > > opinions as to how hard it would be to make the change? > > Is this for space stuff, using the radhard parts, perhaps? I prefer the > Xilinx parts but have done several designs with the radhard Actel 1020s > and 1280s. I have not tried the newer Actel parts, so I don't know > anything about those. The basic Actel Desktop tools are very easy to > use, and you should have no problem migrating to Actel from Xilinx. They > are very basic "click the go button" style of tools. I do not use the > Veribest design tools that come with it, so cannot comment on that. > > The most annoying difference is that these parts do not have a built in > power on reset. So you often need to put a little extra effort into > reset circuitry, even if it is sometimes solely to make the simulation > work well. The structure of the 1020s and 1280s is basic muxes and > flipflops, with none of the carry chains and RAM cells of the Xilinx > parts. Arithmetic functions are significantly more cumbersome and slower > because of that. Floorplanning probably is not necessary, as I can often > achieve well over 90% utilization at reasonable speeds without it. The > chip viewer/editor is just about useless in my opinion. Just a few notes: 1. Some of the models they make do have dual-port RAM. The first model was a derivative of the Act 2 parts (i.e., 1280) and was called the 3200DX series. The 42MX series was derived from that and has dual-port. Their A500K series (I think I remembered that correctly) also has RAM, although the programmable element technology is flash, not antifuse. 2. I have found their chip editor quite useful. The newer releases also have some new functions, such as showing the connections between modules, similar to what you see when the PCB guy shows you the board layout and signal connections. It sure beats the older techniques of doing placement or even seeing what the placer did. 3. The Quicklogic architecture, in some models, also has RAM. These are also antifuse parts, using an amorphous silicon antifuse. -- rk How the hell do I know? I'm just a stellar engineering, ltd. common, ordinary, simple savior of stellare@erols.com.NOSPAM America's destiny. Hi-Rel Digital Systems Design -- Pat PaulsenArticle: 31203
Hi ! We are product to HDTV CG(character generater). We are want a design for a HDTV(1920) PLL logic We want to application databook for vertex echo chip. look forward to your replyArticle: 31204
Thanks, it worked! Just out of curiosity, why? Why is it necessary to specify those parameters in a different way for simulation and synthesis? Why couldn't life be easier.... ? ;-) Meelis "Brian Philofsky" <brian.philofsky@xilinx.com> wrote in message news:3B0004C2.18FE8DFA@xilinx.com... > > > Hello Meelis, > > The attribute you are setting is for synthesis only. Unfortuanately, you > must apply one attribute for synthesis and one for simulation to get this to > simulate and implement properly. ...Article: 31205
Hi folks
does anybody know where I can find a pdf Virtex Handbook? (not the Virtex-II
Handbook)
Thanks
Marcel
--
_ _ ___ ___ HSR Hochschule Rapperswil
| || / __| _ \ Wireless Lab EMAIL: mwatting@hsr.ch
| __ \__ \ / Marcel Wattinger WWW : www.hsr.ch
|_||_|___/_|_\ Oberseestrasse 10 Phone: +41 (0)55 253 20 89
8640 Rapperswil Switzerland Fax : +41 (0)55 253 20 70
Article: 31206
Hi,
are you looking for the databook?
if so, look at
http://www.xilinx.com/partinfo/databook.htm
there you will find the Virtex databooks, not only Virtex-II
bye norbert
Marcel Wattinger wrote:
>
> Hi folks
>
> does anybody know where I can find a pdf Virtex Handbook? (not the Virtex-II
> Handbook)
>
> Thanks
>
> Marcel
>
> --
> _ _ ___ ___ HSR Hochschule Rapperswil
> | || / __| _ \ Wireless Lab EMAIL: mwatting@hsr.ch
> | __ \__ \ / Marcel Wattinger WWW : www.hsr.ch
> |_||_|___/_|_\ Oberseestrasse 10 Phone: +41 (0)55 253 20 89
> 8640 Rapperswil Switzerland Fax : +41 (0)55 253 20 70
--
---------------------------------------------------------------
Jim Davis (Garfield: his 31st book):
Garfield (to a robin): There's a cat in the neighborhood!
Quick hide in my mouth! (robin fly away)
Garfield: Where is the trust? Where IS the trust?
---------------------------------------------------------------
Norbert Bierlox / Universitaet Karlsruhe (TH)
Dipl.-math. / Institut fuer Angewandte Mathematik
fon: +49 721 608 8331 / D-76128 Karlsruhe
fax: +49 721 608 8319 / Norbert.Bierlox@ieee.org
---------------------------------------------------------------
Article: 31207This is a multi-part message in MIME format. --------------3AC6E514C174A4A348527C2F Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit What is the difference between Level 1 and Level 3 Version in Leonardo Spectrum (Exemplar Logic)? --------------3AC6E514C174A4A348527C2F Content-Type: text/x-vcard; charset=us-ascii; name="roy.vcf" Content-Transfer-Encoding: 7bit Content-Description: Card for Roy Shoshani Content-Disposition: attachment; filename="roy.vcf" begin:vcard n:Shoshani;Roy tel;cell:972-54-380850 tel;fax:972-4-6230151 tel;work:972-4-6230150 ext120 x-mozilla-html:TRUE org:Harmonic Lightwaves (Israel) LTD.;Hardware R&D <P> <IMG SRC=http://www.geocities.com/SiliconValley/Hardware/8614/hl1.gif> version:2.1 email;internet:roy@harmonic.co.il adr;quoted-printable:;;19 Alon Hatavor St., Zone 3=0D=0AP.O Box 36000=0D=0A;Caesarea ;;389000;Israel x-mozilla-cpt:;25944 fn:Roy Shoshani end:vcard --------------3AC6E514C174A4A348527C2F--Article: 31208
Eric <erv_nospam@sympatico.ca> wrote in <3B001F54.2FB89B97@sympatico.ca>: >You'll find exactly what you're looking for in this Xilinx Application >note : > >http://www.xilinx.com/xapp/xapp012.pdf Does it really work? I tried some test patterns and found it is working not as beautiful as expected. - it detects only one edge of the input waveforms - the detection of the direction does not work properly my test pattern: 2 waves of A,B clockwise, 2 waves counterclockwise 1st wave CW: DIR=Low 2st wave CW: DIR=Low 1st wave CCW: DIR=High, but in the last 4th of the wave the DIR goes Low unexpectedly for 1/4th of the wave 2st wave CCW: DIR=High This error should not influence your up/down count, because there is no count pulse in the error case of the DIR signal (if you do not count with the H/L edge). Well, nevertheless it is possible to create a 4 times quad decoder with the same number of cells and the same architecture. M.Article: 31209
Where do I get a FREE IP-core for PCI 2.1 besides www.maxlock.com ? T.i.a. JohnArticle: 31210
Patrick Muller <patrick at scs dot com> wrote: > Try to attatch different BLKNM attributes to the flip flops that should not > be maped together. This can be done either in the .ucf file or in the VHDL > code, what would look something like this: > attribute BLKNM : string; > attribute BLKNM of MyFF0 : label is "MyFF0"; > attribute BLKNM of MyFF1 : label is "MyFF1"; > More about this attribute can be found in the Xilinx Foundation > documenation.... Hmmm. Thanks for the suggestion. Will this help in the case where the synthesis tool is fanning out the signals? It will need to propagate the attributes to the duplicated signals, but it'll need to modify them to avoid duplicates. I find the perl script solution works quite well. I call it Fixify :-) Hamish -- Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au> Greets to Allan.. :-)Article: 31211
Meelis Kuris <matiku@hot.ee> wrote: > So, what other free/shareware simulator can I use for simulation > where I can also use Virtex2 specific things like DCM? Use the UNISIM library (supplied with Alliance and presumably also Foundation) for simulating Xilinx primitives, in whatever simulator you like. It's not ModelSim specific. Hamish -- Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>Article: 31212
Eric wrote: > > You'll find exactly what you're looking for in this Xilinx Application note : > > http://www.xilinx.com/xapp/xapp012.pdf > > Hope this helps, > > Eric. > > -------------------------- > vi wrote: > > > Anyone have a quadrature decoder in a schematic format to share? I have > > done it with D F/Fs and it work under simulation, but it did not work very > > well under real test. I used Xilinx and Orcad schematic capture. > > Here's one in VHDL. It differs from the xapp012 one in that it will increment or decrement the count on every input transition. http://www.sigda.org/Archives/NewsGroupArchives/comp.lang.vhdl/Aug1998/14320.txt Here's something similar, in ascii art schematic form: http://groups.google.com/groups?ic=1&selm=3718E491.D607BA80%40kom.auc.dk The OP (vi) didn't say what didn't work very well under real test... it could have something to do with noise on the inputs. You might need to use some sort of filtering. Regards, Allan.Article: 31213
Rick Filipkiewicz <rick@algor.co.uk> wrote: > extends to V2-4 <=> V-E-7 then I'll gladly pay the extra price. Is that roughly right? Virtex-II -4 equivalent to a Virtex-E -7? Hamish -- Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>Article: 31214
Hi again, This time the problem is that after 16.000 ns of simulation DCM just stops, clk0 output still works ok but CLKFX output just goes low. All status and locked signal don't change, input signals are the same. I'm using this DCM to multiply 54MHz clock by 5 to get 270MHz. The problem is in sinulation, I don't have possibility to test this in silicon at the moment. I'm using Modelsim XE. Thanks, MeelisArticle: 31215
Hello everyone:
I divided a clock input and use the output of the dividor as a clock
input to another block.
According to XILINX PAR report, this clock did not used the special rounting
resource and its slew will be big. So I connect the dividor output to a BUFG
and use the BUFG output as clock. But the result shows it is not better than
previous one. The block that used the divided clock is still unstable.
How could I make it stable when I use internal generated clocks? Any advice
would be appreciated.
Thanks
Article: 31216Maybe to this constraint helps: NET "blabla" USELOWSKEWLINES; Meelis "norman yang" <norman_yang@sina.com> wrote in message news:9drani$1i2r$1@news.cz.js.cn... > Hello everyone: > I divided a clock input and use the output of the dividor as a clock > input to another block. > > According to XILINX PAR report, this clock did not used the special rounting > resource and its slew will be big. So I connect the dividor output to a BUFG > and use the BUFG output as clock. But the result shows it is not better than > previous one. The block that used the divided clock is still unstable. > > How could I make it stable when I use internal generated clocks? Any advice > would be appreciated. > > Thanks > > >Article: 31217
Hi, Sorry, new at designing on FPGA's. I have made a design with two macro symbols, the first driving the second. Simulation by themselves works fine, but as soon as I connect the first macro to the second, it appears the the outputs of the first symbol can't drive the second - could be due to excess circuitry etc. Thus, the outputs just go to X when they are supposed to go high. What is the most common technique on FPGA's to rectify this problem? adrianArticle: 31218
This is a multi-part message in MIME format. --------------CD66E3F25A9BD9266163ACB7 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Meelis, If figured this question would be asked. Trust me, I too would like life to be easier and I personally am looking into ways of improving this but it is not going to happen any time soon unfortunately. The only way I can explain this divergance is to say that synthesis tools went one way to pass attributes and simulation went another and right now, the two can not meet. As far as I know, VHDL attributes are ignored by most simulators and therefore can not pass information to simulation models however generics can. Synthesis tools ignore or error out when they see generics but use attributes to pass this same sort of information. Unless there is a way for the simulation models to use these attributes to configure those properties, synthesis tools will need to read generics or else yet another medium will be needed for attribute passing. Also keep in mind, when I say synthesis tools, I am talking about several different companies here (Synopsys, Exemplar, Synplicity, to name just three), not just Xilinx and the same is true for simulators. A change like this in a synthesis or simulation tool will not come easy. Verilog has these same issues except substitue the word "generic" above for parameter/defparam and the word "attribute" with synthesis directives. Exact same problem however. If anyone has ideas on how this can be improved, please feel free to pass on your ideas to me. As I said earlier, I too would like to make life easier if possible but do not see a simple solution to this problem. Regards, -- Brian Meelis Kuris wrote: > Thanks, it worked! > > Just out of curiosity, why? Why is it necessary to specify > those parameters in a different way for simulation and synthesis? > Why couldn't life be easier.... ? > ;-) > > Meelis > > "Brian Philofsky" <brian.philofsky@xilinx.com> wrote in message > news:3B0004C2.18FE8DFA@xilinx.com... > > > > > > Hello Meelis, > > > > The attribute you are setting is for synthesis only. Unfortuanately, > you > > must apply one attribute for synthesis and one for simulation to get this > to > > simulate and implement properly. > ... --------------CD66E3F25A9BD9266163ACB7 Content-Type: text/x-vcard; charset=us-ascii; name="brian.philofsky.vcf" Content-Transfer-Encoding: 7bit Content-Description: Card for Brian Philofsky Content-Disposition: attachment; filename="brian.philofsky.vcf" begin:vcard n:Philofsky;Brian x-mozilla-html:TRUE url:http://www.xilinx.com org:Xilinx Software Marketing;SLAM adr:;;2300 55th St;Boulder;CO;80301;USA version:2.1 email;internet:brian.philofsky@xilinx.com title:Sr Technical Marketing Engineer fn:Brian Philofsky end:vcard --------------CD66E3F25A9BD9266163ACB7--Article: 31219
Miha Dolenc schrieb: > > Hi! > > As I can see on this newsgroup, there is a lot of interest in FREE IP > cores for different purposes. Hi Miha, you are right, there is a lot of interest in FREE IP cores on this newsgroup. why? First: There are some vhdl-experts(?) how don't realy like to write vhdl (this is not good news). Instead they are using free ip cores in the designs the are owned for. (this is very bad news). Second: this newsgroup is read by most students. Sometimes they don't like to write there homework, given by their teachers.(bad news). As a typical example: a simple crc-generator. Please, ask them to write there own code. It's the only way to learn vhdl. my opinion. michael strothjohannArticle: 31220
On Tue, 15 May 2001 11:21:33 +0200, Roy Shoshani <roy@harmonic.co.il> wrote: >What is the difference between Level 1 and Level 3 Version in Leonardo >Spectrum (Exemplar Logic)? Level 3 has asic synthesis option. Level 1 & 2 are for strictly fpga. 1&2 probably has optimization capability differences. Muzaffer FPGA DSP Consulting http://www.dspia.comArticle: 31221
Michael Strothjohann <strothjohann@rheinahrcampus.de> writes: > you are right, there is a lot of interest in FREE IP cores > on this newsgroup. why? > > First: There are some vhdl-experts(?) how don't realy > like to write vhdl (this is not good news). > Instead they are using free ip cores in the > designs the are owned for. (this is very bad news). You seem to be arguing against code reuse? If there's a perfectly good free core already available, why should someone write a new one? This doesn't sound like "very bad news" to me. > Second: this newsgroup is read by most students. > Sometimes they don't like to write there homework, > given by their teachers.(bad news). As a typical example: > a simple crc-generator. Please, ask them to write there > own code. It's the only way to learn vhdl. If you're suggesting that having free cores for CRC generators is bad for that reason, I think you're facing an uphill battle. Sure, students like to get out of doing work. But so do engineers. Instructors need to give homework assignments whose results can be distinguished from publicly available code. For instance, the famous traffic light and vending machine problems. These work well as homework assignments precisely because in the real world no one designs either in HDL; they are both microprocessor based. Have you seen the responses in this newsgroup or in comp.lang.vhdl when students ask for traffic light or vending machine code? It can be quite entertaining.Article: 31222
Make sure that the DCM is set to high frequency mode. Otherwise this application will violate the CLKFX output frequency range spec. Meelis Kuris wrote: > Hi again, > > This time the problem is that after 16.000 ns of simulation > DCM just stops, clk0 output still works > ok but CLKFX output just goes low. > All status and locked signal don't change, > input signals are the same. > > I'm using this DCM to multiply 54MHz clock by 5 to get 270MHz. > > The problem is in sinulation, I don't have possibility to test this > in silicon at the moment. I'm using Modelsim XE. > > Thanks, > > MeelisArticle: 31223
I think you want to use the DLL. It can produce a divide by 2 or 4 clock that aligns with the input clock. "norman yang" <norman_yang@sina.com> wrote in message news:9drani$1i2r$1@news.cz.js.cn... > Hello everyone: > I divided a clock input and use the output of the dividor as a clock > input to another block. > > According to XILINX PAR report, this clock did not used the special rounting > resource and its slew will be big. So I connect the dividor output to a BUFG > and use the BUFG output as clock. But the result shows it is not better than > previous one. The block that used the divided clock is still unstable. > > How could I make it stable when I use internal generated clocks? Any advice > would be appreciated. > > Thanks > > >Article: 31224
I have a question regarding the bit of PCI outside the chip - the bus!? I know that running at 33/66 Mhz is entering the RF range of problems - but how far can I push it, and it still work? It should reay have a short bus with minimal stubs to each card / device as you see in a standard pc, with good grouding and tracks layed correctly. corret? But..... and here are my questions:- How long can the bus be at 66Mhz? How much veriation in track length can I have? (1 inch, 5 inch, 10inch difference?) How long can a stub be? (1 inch, 5 inch?) How close can I lay tracks to each other or other data lines without cross talk? What problems am I ligthy to see? bit errors, parity etc? also... If I have one device that is 32bit and three that are 64bit - should the 32bit device sit in the middle or can it sit off one end (ie extending the lower part of the bus beond the top 32bits)? And lastly - is there somwhere I can find this information? Many - Many thanks cyber_spook_man
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Compare FPGA features and resources
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