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Matthias Fuchs schrieb: > > Hi, > > is it possible to use a normal (non clock) pad from a Spartan II FPGA to > drive an internal clock net ? Automatic implementation cannot do that > and aborts with an error ! Is it possible to force a connection from PAD > to INBUF to BUFGP by hand ? Clock skew or the delay from the clock pad > to the FFs is not that critical for this design ! > > Has anybody an idea how to do this ? In the synthesis constraints (click on the version panel, right click the version) got to the ports section, choose for your clock nets "Dont use", which prohibites the use of global clock nets. In the UCF you should write NET clocknet uselowskewlines; where colcknet is the name of your clocknet, this will cause route to use fast longlines for your clock net. -- MFG FalkArticle: 31101
Hi All, Just wanted to post this position, in case anyone out there has been affected by the layoffs. This is a great new company in Austin, that we have been working with for over a year. It was rated in the top ten best new companies in Austin. Great salary, benefits, and options. As they are a fairly new company, the relo is minimal. Thanks for your time. Jo Parmer Senior FPGA Design Engineer Qualifications: The Senior FPGA Design Engineer is responsible for the conceptual design, specification, implementation and debug of complex FPGA's. The Engineer hired for this position will have a solid background in server and networking based systems. PCI and ATM SAR functionality is highly recommended. A good knowledge base of FPGA simulation using Verilog, synthesis, and place & route is required. Experience with Exemplar's Leonardo, Synplicity's Synplify and Model Technology's ModelSim is required. The selected individual will have extensive experience debugging FPGA's in system in the lab. The selected individual will work closely with other senior design engineers to implement production logic. Individual will be responsible for component selection, I/O pinouts and optimal layout floorplanning. The candidate will have good interpersonal skills and have the ability to negotiate, influence, and lead others to consensus decision. The candidate will have a BS/MS EE and a minimum of 10 years experience in digital design. _____________________________ Jo Parmer jparmer@pedley-richard.com Research Consultant Pedley-Richard & Associates, Inc. ph: 512.418.3253 www.pedley-richard.com -- Posted from ps01.directhire.com [207.170.85.2] via Mailgate.ORG Server - http://www.Mailgate.ORGArticle: 31102
Kolja wrote: > > I am not familiar with the Altera tools, but I am wondering why Xilinx has no > ambitions to port their software. > It should be quite easy. Hmm, maybe good news: seems that xilinx programmers have already taken notice about the existence of linux: ... #endif /***** end SYSWin32 ***********************************************************/ /***** LINUX ******************************************************************/ #ifdef SYSLinux #endif /***** end SYSLinux ***********************************************************/ (An excerpt from the JDrive code, "the world's first IEEE Std 1532 Programming Engine") Perhaps somebody should point out to xilinx managers that "the world's first Open Source FPGA/CPLD Development Suite for Linux" sounds also very sexy and automatically implies "the world's most user friendly FPGA/CPLD Chips". MartinArticle: 31103
I've had the same problem many times, with unused pins being changed to an output for some internal signal, and it seems to be an infortunate trick used by the router when it can't complete operations (looks like a minor bug). If you carefully look at the bitgen report, you'll see a warning about it. Spent the morning on it the first time it happened, now part of routine checks whenever something goes wrong. ----------- Talking about getting crazy with a Spartan, I recently had a design where a controller loaded the configuration in a spartan, and it all worked well as long as a ROM simulator was plugged. As soon as I started using a "real" Eprom, the Spartan chip could not be configured anymore. I tried anything I could think about, like tweaking the bitstream upload software, buffering the signals, adding an external latch, a serie resistor to prevent gliches, slowing down the processor clock. Nothing helped. Somewhat confused, I hooked a second identical Spartan chip with only PROGRAM, CCLK & DIN connected , and this one just got configured well, while the one on the board still refused to work. I finally discovered that 2 of the IO lines that were connected to the processor's data bus also had "TDI" and "TCK" as an alternate function (oups!). Since I did not use JTAG at all, I overlooked the fact that during configuration, these alternate functions are active and *will* badly interfere with the device bitstream loading, if the timing is "right". As usual, the problem lied between the keyboard and the screen ... Eric. ---------------------------------- John Larkin wrote: > Hi, > > we've just shipped a new product that uses 5 Spartan-XL chips, and had > a fair amount of grief getting things up. We're using the basic > Foundation schematic-entry stuff, with service packs duly installed. > > The worst thing we found is that, if we connect a signal to a pin and > don't reference it on the schematic, the pin will sometimes become an > output and do weird things. In one case, we ran the VME signal AS* > (address strobe) into the chip and decided later we didn't need it, so > ignored it. It then began hanging the VME bus by pulling AS* low, but > only when certain VME addresses were used! > > In another case, all 5 FPGAs shared the DIN common config data pin; > once the first chip was configured, it started driving its own DIN as > an output, and trashed the config of the other four chips. This was > compile dependant (ie, random on different compiles). > > The fix is to run all unused inputs into a huge AND gate and run the > output to an unconnected output pin, just to keep the compiler happy. > > We never had such problems with 4000XL's. Any experience/ideas with > this one? > > John > > ps: the Spartan chips seem to have enough muscle to be a damned fine > VMEbus driver! > > pps: the AND gate trick works, if there's an output pin available. > What if not? Then you'd have to invent a circuit with N inputs and no > outputs, but that was complex enough that the compiler couldn't figure > out that it's useless hence wouldn't strip it out!Article: 31104
Kolja Sulimma wrote: > But hey, wait, you can do all your designs with JBits. You will use a couple of > month with respect to > time-to-market, but everything will be hand optimized and fine tuned to get very > good results. > > Kolja Sulimma This is an interesting spin on things. Most companies I have worked for would gladly trade off FPGA utilization to gain a couple months to market. The project I am currently working on costs the company $500,000 in lost sales every month we delay product ship. They focus on making their designs portable between different vendors so that they can use that as a lever to get pricing even lower than a vendor's "best" price. Kinda like the time I was car shopping and the dealer said that was his "best" possible price. When I said I was leaving, he dropped the price a few more hundred, (back in the days when you could get a car for $7000). So they actually waste silicon in the sense of not using much of the "special" features so that they are not locked into a single vendor. So size optimization is not important to some companies since they use a business model that maximizes profits in a different way. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 31105
Hi all ! I'll appreciate if anyone could facilitate me with some idea to implement LUT (4096 words depth with 10 bits width) in Vertex-E (Part: V1000EBG 560) for FPGA. Thanks in advance, ------- KhanArticle: 31106
martin capitanio <martin@capitanio.org> writes: > Perhaps somebody should point out to xilinx managers that > "the world's first Open Source FPGA/CPLD Development Suite for Linux" > sounds also very sexy and automatically implies "the world's most > user friendly FPGA/CPLD Chips". It would, but I harbor no fantasies of Xilinx releasing any tools as open source. Even JBits is not open source. I'll be reasonably happy if they just release Linux versions as plain old closed-source. At least JBits will work on Linux, since it's written in Java, although the damn Linux installer that Xilinx used for the latest version won't run properly on my system with Red Hat Linux 7.0 and Sun's latest JDK. AFAIK, all the JBits installer does is extract files from an archive, so it seems like it should be even easier for them to simply supply a .tar.gz file. Sigh.Article: 31107
I'm using a XILINX XC4010E FPGA to generate a clock signal using one of the bits of a counter. Here's the problem: When I view the output on an oscilloscope, I don't see a very clear clock signal, instead I see a waveform with the periodicity of a clock signal, but the positive parts of the waveform look very fuzzy like short spurts of noise. I'm wondering if maybe I'm doing something wrong with the outputs here. Are I/O pins of the FPGA open-collector? Do I need pull-up resistors on the outputs in order to generate a clock waveform? Or can you think of any other reasons for this problem? Thanks for any help you can provide! VikArticle: 31108
It's so easy to experiment. Get a 470 Ohm resistor, tie it to Vcc and hold the other end against the pin in question. Then do the same thing with the resistor connected to ground. That's an easy way to find out whether the output impedance is the 10 to 50 Ohm that it is supposed to be. Peter Alfke =================================== vikram m n rao wrote: > I'm using a XILINX XC4010E FPGA to generate a clock signal using > one of the bits of a counter. Here's the problem: When I view the output > on an oscilloscope, I don't see a very clear clock signal, instead I see a > waveform with the periodicity of a clock signal, but the positive parts of > the waveform look very fuzzy like short spurts of noise. > > I'm wondering if maybe I'm doing something wrong with the outputs here. > Are I/O pins of the FPGA open-collector? Do I need pull-up resistors on > the outputs in order to generate a clock waveform? Or can you think of any > other reasons for this problem? > > Thanks for any help you can provide! > > VikArticle: 31109
I'm having a similar problem on the XC4028XL. I have a clk in the port list, so a pad should get inferred. But I get this error... Same error if I remove the BUFG and use clk directly. I'm told the error does NOT occur when synthesized by FPGA Express, but I'm using fpga compiler 2. The error: Checking expanded design ... ERROR:NgdBuild:455 - logical net 'clk_in' has multiple drivers ERROR:NgdBuild:461 - logical net 'clk_in' has multiple pad connections The code: module blink(reset_n, led, clk); input clk; input reset_n; output led; wire clk_int; BUFG bufg0 (.I(clk), .O(clk_int)); //synopsys attribute LOC "P63" Matthias Fuchs wrote: > > Hi, > > is it possible to use a normal (non clock) pad from a Spartan II FPGA to > drive an internal clock net ? Automatic implementation cannot do that > and aborts with an error ! Is it possible to force a connection from PAD > to INBUF to BUFGP by hand ? Clock skew or the delay from the clock pad > to the FFs is not that critical for this design ! > > Has anybody an idea how to do this ? > > Matthias > -- > ------------------------------------------------- > \ Matthias Fuchs \ > \ esd electronic system design Gmbh \ > \ Vahrenwalder Straße 205 \ > \ D-30165 Hannover \ > \ email: matthias.fuchs@esd-electronics.com \ > \ phone: +49-511-37298-0 \ > \ fax: +49-511-37298-68 \ > -------------------------------------------------- -- ______________________________________________________________________ Ken Barr (617) 225-1605 kbarr@mit.edu www.mit.edu/~kbarr MIT Laboratory for Computer Science Computer Architecture GroupArticle: 31110
Virtex E system gate count mentioned in the data sheet is different from the one I found somewhere on the Xilinx website(Probably : FAQ's on Virtex E). In fact the system gates for Virtex E , mentioned in the article on the website was same as the system gates for Virtex(2.5 V), while they were different in the datasheet for Virtex E. Can anyone please tell me this disceperancy. Also how do you calculate the system gate count?I mean what % age of BRAM etc. The details in xapp #059 are for devices specifcally containing no BRAM . What about devices containing BRAM? Altera mentions in it's Datasheet Maximum system gate count which includes all ESB's used for memory and all LE's used for logic. What is the Xilinx equivalent for this??Article: 31111
If counter A steps into a value about the same time counter B steps out of the same value, there will be a glitch. You could have an up counter and a down counter pass each other without registering an equality if they both transition at the same time (6->5 and 5->6 for instance... 6!=5 and 5!=6). Happily, applications like the FIFO Peter Alfke just illustrated don't care much about glitches in a properly implemented system.Article: 31112
I construct the RAM in my VHDL program by the basic unit 16x1 which is
provided by the xc4000x
library, but when I do the synthesis stpe using FPGA_Express, it always says
16x1 RAM are unlinked Cell, how can I solve this problem?
Thank you very much!
Here is my code for a 16x4 single port RAM
-----------
library IEEE;
use IEEE.std_logic_1164.all;
library xc4000x;
library synplify;
use synplify.attributes.all;
entity ram_16x1s is
--generic (init_val : string := "0000" );
port (O : out std_logic;
D : in std_logic;
A3, A2, A1, A0: in std_logic;
WE, CLK : in std_logic);
end ram_16x1s;
architecture xilinx of ram_16x1s is
--attribute xc_props: string;
--attribute xc_props of u1 : label is "INIT=" & init_val;
component RAM16x1s
port (D : in std_ulogic;
WE : in std_ulogic;
WCLK : in std_ulogic;
A0 : in std_ulogic;
A1 : in std_ulogic;
A2 : in std_ulogic;
A3 : in std_ulogic;
O : out std_ulogic);
end component;
begin
U1 : RAM16X1s port map (O =>O,
d=>d,
WE => WE,
WCLK => CLK,
A0 => A0,
A1 => A1,
A2 => A2,
A3 => A3
);
end xilinx;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity ram_16x4s is
port (o: out std_logic_vector(3 downto 0);
we : in std_logic;
clk : in std_logic;
d: in std_logic_vector(3 downto 0);
a: in std_logic_vector(3 downto 0));
end ram_16x4s;
architecture xilinx of ram_16x4s is
component ram_16x1s
--generic (init_val: string := "0000");
port (o : out std_logic;
D : in std_logic;
A3, A2, A1, A0: in std_logic;
WE, CLK : in std_logic);
end component;
begin
U0 : ram_16x1s-- generic map ("FFFF")
port map (O =>O(0),
WE => we,
CLK => clk,
D => d(0),
A0 => a(0),
A1 => a(1),
A2 => a(2),
A3 => a(3));
U1 : ram_16x1s-- generic map ("ABCD")
port map (O =>O(1),
WE => we,
CLK => clk,
D => d(1),
A0 => a(0),
A1 => a(1),
A2 => a(2),
A3 => a(3));
U2 : ram_16x1s-- generic map ("BCDE")
port map (O =>O(2),
WE => we,
CLK => clk,
D => d(2),
A0 => a(0),
A1 => a(1),
A2 => a(2),
A3 => a(3));
U3 : ram_16x1s --generic map ("CDEF")
port map (O =>O(3),
WE => we,
CLK => clk,
D => d(3),
A0 => a(0),
A1 => a(1),
A2 => a(2),
A3 => a(3));
end xilinx;
----------------
Article: 31113We are using VirtexII XC2V1000FG456 in our design.the development software is Foundation iSE3.3i,Simulation tool is ModelSim We have passed Place and route,and found no timing errors,the minimum slack is about 0.3ns(clocked at 200MHz). but in doing post timing,We find the following error: ** Error: C:/XILINX/verilog/src/simprims/X_FF.v(55): $setup( negedge RST:1372716 ps, posedge CLK &&& (CE == 1):1372907 ps, 479 ps ); # Time: 1372907 ps Iteration: 0 Instance: /tf/FPGA/\pts_unit0/shifter_low[24]\ # ** Error: C:/XILINX/verilog/src/simprims/X_FF.v(55): $setup( negedge RST:1372716 ps, posedge CLK &&& (CE == 1):1372907 ps, 479 ps ); # Time: 1372907 ps Iteration: 0 Instance: /tf/FPGA/\pts_unit0/shifter_low[9]\ # ** Error: C:/XILINX/verilog/src/simprims/X_FF.v(55): $setup( negedge RST:1372716 ps, posedge CLK &&& (CE == 1):1372907 ps, 479 ps ); # Time: 1372907 ps Iteration: 0 Instance: /tf/FPGA/\pts_unit0/shifter_low[8]\ # ** Error: C:/XILINX/verilog/src/simprims/X_FF.v(55): $setup( negedge RST:1372505 ps, posedge CLK &&& (CE == 1):1372908 ps, 479 ps ); # Time: 1372908 ps Iteration: 0 Instance: /tf/FPGA/\pts_unit5/shifter_low[7]\ # ** Error: C:/XILINX/verilog/src/simprims/X_FF.v(55): $setup( negedge RST:1372505 ps, posedge CLK &&& (CE == 1):1372908 ps, 479 ps ); # Time: 1372908 ps Iteration: 0 Instance: /tf/FPGA/\pts_unit5/shifter_low[6]\ Where the problem lies? Thank you.Article: 31114
In article <u0KK6.11$09.832@news2.bora.net> ejhong@future.co.kr "Ben" writes: > Hi, > > I have a PCI device whose interface is not compatible with CardBus standard. > But I want to build a CardBus PC Card with the PCI device. > In this case, is it possible to build a CardBus PC Card by integrating > CardBus-to-PCI bridge and the PCI device? > I wonder if there exists any CardBus-to-PCI bridge. > By the way, does it make sense to build a CardBus PC Card with a PCI device? TI's PCI-1225 I think may be one of the chips you are looking for. It features in my Dell Laptop and reports as a Cardbus-PCI bridge to FreeBSD. I haven't looked further than that yet. Maybe http://www.ti.com/ will be a suitable starting point. -- ******************************************************************** Paul E. Bennett ....................<email://peb@amleth.demon.co.uk> Forth based HIDECS Consultancy .....<http://www.amleth.demon.co.uk/> Mob: +44 (0)7811-639972 .........NOW AVAILABLE:- HIDECS COURSE...... Tel: +44 (0)1235-814586 .... see http://www.feabhas.com for details. Going Forth Safely ..... EBA. www.electric-boat-association.org.uk.. ********************************************************************Article: 31115
> At least JBits will work on Linux, since it's written in Java, although > the damn Linux installer that Xilinx used for the latest version won't > run properly on my system with Red Hat Linux 7.0 and Sun's latest JDK. > AFAIK, all the JBits installer does is extract files from an archive, > so it seems like it should be even easier for them to simply supply a > .tar.gz file. Or a JAR file.... Kolja SulimmaArticle: 31116
> martin capitanio <martin@capitanio.org> writes: > > Perhaps somebody should point out to xilinx managers that > > "the world's first Open Source FPGA/CPLD Development Suite for Linux" > > sounds also very sexy and automatically implies "the world's most > > user friendly FPGA/CPLD Chips". > > It would, but I harbor no fantasies of Xilinx releasing any tools as > open source. Even JBits is not open source. I can see that JBits contains trade secrets. I know that Steve Guccione has very serious research interests in JBits generators, but I believe that to most of Xilinx JBits is only a way how they can make academia happy without publishing details about the bitstream. But this is not true for many other tools. How much is there to gain for Xilinx from keeping the hardware debugger source code secret? But there is something to gain from making it open source: Peter Alfke send me a code snippet a while ago and I found a bug within 30 seconds. Kolja SulimmaArticle: 31117
A. I. Khan schrieb: > > Hi all ! > > I'll appreciate if anyone could facilitate me with some idea to > implement LUT (4096 words depth with 10 bits width) in Vertex-E (Part: > V1000EBG 560) for FPGA. Sounds like you need a 4096x10bit ROM?? Just use the Core-Generator to get 8 512x8bit ROMS made of BlockRAM (gives you 4096x8bits) plus 2 2048x2bit ROMS. Add an appropiate chip select decoder and you are done. You can also use 10 4096x1bit ROMS (no chip select decoder required),this depends a little bit on the required speed. Dont use the LUTs for such a BIG ROM. -- MFG FalkArticle: 31118
Vivek Sood schrieb: > > Virtex E system gate count mentioned in the data sheet is different from the one I found somewhere on the Xilinx website(Probably : FAQ's on Virtex E). In fact the system gates for Virtex E , mentioned in the article on the website was same as the system gates for Virtex(2.5 V), while they were different in the datasheet for Virtex E. > > Can anyone please tell me this disceperancy. Also how do you calculate the system gate count?I mean what % age of BRAM etc. The details in xapp #059 are for devices specifcally containing no BRAM . What about devices containing BRAM? > > Altera mentions in it's Datasheet Maximum system gate count which includes all ESB's used for memory and all LE's used for logic. What is the Xilinx equivalent for this?? Just forget about the system gate number, its practical useless. Have a look at the CLB and logic cells number. But be carefull, the definition of CLB depends on the family. One logic cell is usually a 4 input Look-up-table + 1 FlipFlop. 4000 & Spartan 1 CLB = 2 logic cells Spartan2 / Virtex / Virtex-E 1 CLB = 2 slices = 4 logic cells Virtex 2 1 CLB = 4 slices = 8 logic cells Beside this, the better (Virtex/Spartan2/Virtex2) families have additional functions inside the CLBs to support fast artihmetic (improved carry chain, multiplexers etc) -- MFG FalkArticle: 31119
Eric Smith wrote: > martin capitanio <martin@capitanio.org> writes: > > Perhaps somebody should point out to xilinx managers that > > "the world's first Open Source FPGA/CPLD Development Suite for Linux" > > sounds also very sexy and automatically implies "the world's most > > user friendly FPGA/CPLD Chips". > > It would, but I harbor no fantasies of Xilinx releasing any tools as > open source. Even JBits is not open source. Look at JDrive. It's possibly unusable, but OS (with the power of GPL have they yet some problems). Imho it is the first xilinx's big step in right direction (world domination in managers dictionary;-) MartinArticle: 31120
Falk Brunner wrote: > > Vivek Sood schrieb: > > > > Virtex E system gate count mentioned in the data sheet is different from the one I found somewhere on the Xilinx website(Probably : FAQ's on Virtex E). In fact the system gates for Virtex E , mentioned in the article on the website was same as the system gates for Virtex(2.5 V), while they were different in the datasheet for Virtex E. > > > > Can anyone please tell me this disceperancy. Also how do you calculate the system gate count?I mean what % age of BRAM etc. The details in xapp #059 are for devices specifcally containing no BRAM . What about devices containing BRAM? > > > > Altera mentions in it's Datasheet Maximum system gate count which includes all ESB's used for memory and all LE's used for logic. What is the Xilinx equivalent for this?? > > Just forget about the system gate number, its practical useless. Have a ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ Falk should have added that they are usually known in the trade as ``marketing gates'' whose meaning is generally only understood by engineering dept. managers during FPGA vendor presentations.Article: 31121
Eric Smith wrote: > At last, one of the programmable logic vendors gets it. They say "Linux > has enjoyed dramatic success over the last several years as a platform > for a variety of EDA point tools, such as simulation, because of the low > cost per compute cycle." An interesting contrast from Xilinx' claims > that there is no customer demand for Linux. Given a choice between a port to Linux and fixing the "Map puts logic that must go into opposite corners of the die to make timing into one CLB, so PAR can't place it" bug, I would hope that Xilinx never ever ports to Linux. Linux is just another another OS. If Xilinx really wants to port to another OS, I'd rather see Tops20. (-;) (OK, hardware availability is a problem.) Or even VMS. Really, the OS is a tiny part of the design process, as least as I see it. Most of my time doing design is spend reading documentation, running the wetware, drawing cryptic stuff on the whiteboard, filling pages of the notebook, writing documentation, doing ^x(^s^s^y^x) sorts of things in EMACS, doing do compile.do and do sim.do stuff, hitting the Run button, floorplanning one of several different ways and running the make file that makes a bit file. What does the OS really have to do with this process? Ok, once this year the OS did get involved, a process got to zombie status and failed to die until I restarted the OS. Cost me a few minutes of time. The last time I was using UNIX, however, similar stuff was a weekly event. Back when I was using Windows 3.1 this was a daily event. OS is a non issue. The MAP issue, on the other hand, bites. -- Phil HaysArticle: 31122
> What does the OS really have to do with this process? A really do not care much about what OS I am working with, but I would really prefer to work in one OS. We are currently running Foundation in a windows NT multi user enviroment. Everybody here is anoyed because the preferences are shared among all users. I of course need some software that will not run under NT, because it uses some wierd driver to talk to the parallel port. So I need a VMWare to be able to securely wun WIN95 Than we have this cadence installation around that will not run with anything but solaris. Bought an extra machine for that. The windows X-Servers suck despite their price, so I boot my PC into Linux when I want to work with the solaris machine. And hey, I am doing more and more embedded stuff, so maybe I need to install QNX as a target platform, too. The cost of maintaining five operating systems is immense. This is not the fault of any of the software vendors, but each of them has the power to solve this problem for me, so I keep asking for it. > OS is a non issue. The MAP issue, on the other hand, bites. I keep asking for that too. My favorite: Read the XC4K datasheet. It says that you can put three arbitrary independant functions (no shared inputs) of 4, 4 and 3 inputs respectively into a single CLB if one or two of these functions are fed to registers. Ever tried this? Well, you can't, unless you use the FPGA-Editor. This is a documented bug from XACT 6.1 that has never been fixed. (I last tried it with Foundation 2.1i) Kolja SulimmaArticle: 31123
"Falk Brunner" <Falk.Brunner@gmx.de> wrote in message news:3AFD127D.9460AAFC@gmx.de... > A. I. Khan schrieb: > > > > Hi all ! > > > > I'll appreciate if anyone could facilitate me with some idea to > > implement LUT (4096 words depth with 10 bits width) in Vertex-E (Part: > > V1000EBG 560) for FPGA. > > Sounds like you need a 4096x10bit ROM?? > Just use the Core-Generator to get 8 512x8bit ROMS made of BlockRAM > (gives you 4096x8bits) plus 2 2048x2bit ROMS. > Add an appropiate chip select decoder and you are done. This is not the fastest or most resource efficient way to do this. You will unnecessarily waste CLBs, and routing resources, decoding the chip selects, and then muxing the ouput data. > You can also use 10 4096x1bit ROMS (no chip select decoder > required),this depends a little bit on the required speed. This is the right way. It is faster, smaller, and... we certainly shouldn't overlook... simpler to implement. Regards, Erik Widding. -- Birger Engineering, Inc. -------------------------------- 781.481.9233 38 Montvale Ave #260; Stoneham, MA 02180 ------- http://www.birger.comArticle: 31124
Phil Hays wrote: ...snip... > Really, the OS is a tiny part of the design process, as least as I see it. Most > of my time doing design is spend reading documentation, running the wetware, > drawing cryptic stuff on the whiteboard, filling pages of the notebook, writing > documentation, doing ^x(^s^s^y^x) sorts of things in EMACS, doing do compile.do > and do sim.do stuff, hitting the Run button, floorplanning one of several > different ways and running the make file that makes a bit file. What does the > OS really have to do with this process? > > Ok, once this year the OS did get involved, a process got to zombie status and > failed to die until I restarted the OS. Cost me a few minutes of time. The > last time I was using UNIX, however, similar stuff was a weekly event. Back > when I was using Windows 3.1 this was a daily event. > > OS is a non issue. The MAP issue, on the other hand, bites. > > -- > Phil Hays I agree that an OS should have a very small effect on a design process. However, when the quality of an OS is so low that it impacts the usability of a tool, that is making a statement about the OS. I am currently using FPGA design tools under NT and I find that I need to boot the machine once every two or three days just to keep things running correctly. Many people claim that the real problems are in the various apps, which may be true. But I have never seen a Unix system that was taken down on a regular basis just to clean up problems. Just as the proof of the pudding is in the eating, the measure of an OS is in the running (or rebooting). Then again some of the tools are nothing to brag about. I find that Modelsim crashes once every 4 or 5 reloads of a design. Fortuately this is not a huge impact. If it crashed during a simulation rather than when I have ended one run and am starting another, it would be unusable. Still it costs me time and money when I have to restart and setup my simulation again perhaps 20 times a day. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX
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