Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
What do you want measure seconds, ms, us? This will determine the number of bits in your counter. A 16 bit counter will only count from 0 to 65535. Using a 10MHz clock you will get a range of about 6.5ms. A 32bit counter at 10MHz will give about 430 seconds window, but will chew up more gates. More accurate than 1/F? You will never get better than 1/F accuracy. To get better than 1/F accuracy you will need multiple 1/Fs which will mean a higher reference clock. If you need better than 1/10E6 you can use a higher clock, such as 50MHz. This will give a 1/50E6 which is 5 times better than a 10MHz clock. FPGA? I don't think so. Rather use a CPLD. One flipflop for start and stop (counter enable signal), nbit counter with clear and registered outputs. The clock freq. can be much higher than a FPGA. It is also cheaper and easier to use than a FPGA. Even the slowest 10ns CPLDs should do the trick. Look at the Altera (don't actually know much of the Xilinx products) 7000MAX series. For jobs like these I would recommend the MAX7128SLC84 -10. It is fast enough, contains a decent amount of gates, is in-circuit programmable and comes in an easy to use PLCC package(plus you can get free software over the internet (www.altera.com )and build your own downloadcable for the price of a hamburger). "Jonas Thor" <thor.NO@SPAM.sm.luth.se> wrote in message news:p1dret0hssttb4uf9meii2t0998n35b1f3@4ax.com... > Hello! > > This is a not well defined question, but I'll ask anyway... I want to > measure, with high precision, the time between two rising edges of two > pulses. I have a reference clock, frequency F, of about 5-10 MHz, but > I need measurements much more accurate than 1/F. (The rising edges are > of course asynchronous to the reference clock.) > > What can I do in a FPGA get the best precison? What's the best I can > do without a DLL and with a DLL? > > Thanks for any advice! > > / Jonas ThorArticle: 30876
About a year ago I read an article on a new image device that looks like RAM (manufactured by HP). You don't need to design high speed CCD circuitry and device drivers for Windoze. You can use something as simple as a 8051 uC, scan the device and then send the data to the PC via RS232. Unfortunately I do not know the part number or the price (which can probably be very high). I know the part exists. If anyone has more details on this please post. "M.B." <martinb@magma.ca> wrote in message news:3aeeb905.4091345@news.magma.ca... > Hi I have a telescope and some basic experiance with VHDL, FPGAs. > I would like to get a CCD (something common and cheap) and use a FPGA > perhaps a xilinx or atmel with VHDL. and interface to my computer (win > 98. > > Has anyone done somthing like this? > Is there a project in any books or wed sites that you have seen that > could get me started? > > Or is there a development kit from one of the CCD Manufacturers that I > could look into? > >Article: 30877
Hi, I've just started teaching myself how to program FPGA's... What is the difference between a LogiBLOX module, and a Core module? Thanks adrianArticle: 30878
gr6@ukc.ac.uk wrote: > > HELLO, > I AM LOOKING FOR A FREE USB (v.2.0) CORE WRITTEN IN VHDL. > REGARDS > GR > Have a look at opencores: http://www.opencores.org/cores/usb/ -- Nicolas MATRINGE IPricot European Headquarters Conception electronique 10-12 Avenue de Verdun Tel +33 1 46 52 53 11 F-92250 LA GARENNE-COLOMBES - FRANCE Fax +33 1 46 52 53 01 http://www.IPricot.com/Article: 30879
Xilinx FPGA (XC2S100-FG256) load via JTAG _and_ FPGA cable works fine, but SPROM (XC18V01) boot doesn't. I've checked all signals (DIN, CCLK, /INIT, /PROG): CCLK is glitch-free, DIN has DATA (from SPROM). After about 70% of the bits /INIT went low; DONE is stays low. (This might be the first CRC check.) I've verified pullups on DONE, /PROG, /INIT and GND on /CS and /WRITE. I've would like to try the bitgen "-g DebugBitstream:Yes" option to see if the FPGA syncs but the unfortunately the SPROM is too small. I'm even not sure if this makes any sense at all to check the sync. Beside this, has anyone an idea what else might go wrong there? OliverArticle: 30880
Probably the device is like the one in an
old BYTE-article ( over one decade ago ):
an DRAM was opened and the
precharged C's are decharged by the incoming
photons. The picture reflects the chip-structure,
but the low-cost ('home-made') device realy works.
michael strothjohann
Victor Schutte schrieb:
> About a year ago I read an article on a new image device that looks like RAM
> (manufactured by HP). You don't need to design high speed CCD circuitry and
> device drivers for Windoze. You can use something as simple as a 8051 uC,
> scan the device and then send the data to the PC via RS232.
>
> Unfortunately I do not know the part number or the price (which can probably
> be very high). I know the part exists. If anyone has more details on this
> please post.
>
> "M.B." <martinb@magma.ca> wrote in message
> news:3aeeb905.4091345@news.magma.ca...
> > Hi I have a telescope and some basic experiance with VHDL, FPGAs.
> > I would like to get a CCD (something common and cheap) and use a FPGA
> > perhaps a xilinx or atmel with VHDL. and interface to my computer (win
> > 98.
> >
> > Has anyone done somthing like this?
> > Is there a project in any books or wed sites that you have seen that
> > could get me started?
> >
> > Or is there a development kit from one of the CCD Manufacturers that I
> > could look into?
> >
> >
Article: 30881Hi, I have some problems in the configuration of virtex FPGA : I try to configure my xc300 FPGA in master serial mode with a 18v02 serial PROM in AFX-PQ-240-100 prototype board. I use the xilinx fundation software to generate the mcs file foe EPROM. The bitsteam is dowloaded in the FPGA, but no result appear !!! What happened ??? I'm completely helpless! Can anybody help me Chiheb REBAI. IXL laboratory University of Bordeaux FRANCE.Article: 30882
Hi, With this you have 2 options: 1. Use a generic to pass in a parameter which will specify which of B1 or B2 to use. In this case you need to use 'if...generate' statements to instantiate each option. You should the B1 and B2 entity/architecture pairs in separate files and use B as a 'wrapper' to choose which one to use. 2. Use a configuration declaration to specift which of B1 or B2 to use. For this you need an entity declaration (B) and the two architectures (B1 and B2). Basically, a configuration allows you to bind a specific architecture (out of many options) to an entity. Bear in mind that configurations may not be fully supported by your VHDL simulator, and by your synthesis tools....this leaves passing a generic as probably the way to go cheers, Chris "mok" <mok_3001@yahoo.com> wrote in message news:9c8v5f$hr2$1@news.qub.ac.uk... > Hi Folks, > > I would like to describe the following in VHDL: > > ----- ----- > | | | | > -->| B |--->| C | ---> > | | | | > ----- ----- > > where B can be either B1 or B2. > I have VHDL code for C, B1 and B2. B1 and B2 describe two different logic > blocks. > I would like to write one VHDL file which can describe both cases, > and choose between B1 and B2 by testing a 'generic' constant or something > like > that. > In short I do not want to write two seperate file for each case, > but one file which can describe both according to a particular > input data (either B1 or B2). > First, is using a 'generic' the way to go?if yes, How can it be > done? if not, how could i reach my goal then? Is there any other > way? > > Cheers. > > PS. I have not got much VHDL knowledge. > >Article: 30883
In article <3AEEE5FD.30C70EA1@sqf.hp.com>, nials@sqf.hp.com says...
> Greg Deuerling wrote:
>
> > I plan to use Foundation and a SpartanII comming up. Altera really
> > lost me as a high end FPGA customer when they put out that load of
> > crap called Quartus. They should have left MaxPlusII alone, it was
> > simple, fast, and easy to use. I'll get used to using VHDL, but I'll
> > NEVER like it, and wish I was using AHDL.
>
>
> Greg,
>
> You must have had one of the early releases of Quartus, I think it's
> much more stable now. I haven't used it for about a year now, but
> even then I had no problems (it was on an NT box).
>
> The Xilinx tools are a bit more mature, but I'm sure they'd problems
> initially.
Nope, I'm running QuartusII. I can pretty much crash Quartus at will.
All you have to do is switch between compile mode to simulation mode
several times and sooner or later it will crash. Altera had a VHDL
class here and I was complaining how slow and buggy Quartus was and
they did not beleive me. I crashed 4 of their computers in several
minutes with out breaking a sweat. When I started using Foundation
it was also very slow and buggy, but now its pretty nice and a whole
lot better than Quartus. I'll stick to MaxPlusII for small designs
and Foundation and Spartan's for big designs...
By the way, I use Win2000...
--
gad
=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=
= Greg Deuerling, Fermi National Accelerator Laboratory =
= P.O.Box 500 MS368 Batavia, IL 60510 (630)840-4629, FAX (630)840-5406 =
= Electronic Systems Engineering Group =
= Work: egads@fnal.gov Personal: gad@elnet.com =
=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=
Article: 30884Well, thats about the same situation as I have (see FPGA SPROM boot problem ). In my case direct JTAG and FPGA load works fine. Have you checked your ConfigClk:CCLK for bitgen? Does /INIT stays asserted for the entire loading time? Cheers Oliver rebai chiheb wrote: > Hi, > > I have some problems in the configuration of virtex FPGA : > > I try to configure my xc300 FPGA in master serial mode with a 18v02 > serial PROM in AFX-PQ-240-100 prototype board. > I use the xilinx fundation software to generate the mcs file foe EPROM. > The bitsteam is dowloaded in the FPGA, but no result appear !!! > What happened ??? > > I'm completely helpless! > > Can anybody help me > > Chiheb REBAI. > IXL laboratory > University of Bordeaux > FRANCE.Article: 30885
The Final Program for CHES 2001 in Paris can be found at
http://www.chesworkshop.org
For registration and hotel information, please also check the web site
above.
Regards,
Christof
! WORKSHOP ON CRYPTOGRAPHIC HARDWARE AND EMBEDDED SYSTEMS (CHES 2001) !
! Paris, France, May 13-16, 2001 !
! www.chesworkshop.org !
***********************************************************************
Christof Paar, Associate Professor
Cryptography and Information Security (CRIS) Group
ECE Dept., WPI, 100 Institute Rd., Worcester, MA 01609, USA
fon:(508) 831 5061 email: christof@ece.wpi.edu
fax:(508) 831 5491 www: http://www.ece.wpi.edu/People/faculty/cxp.html
***********************************************************************
Article: 30886You may want to get ahold of Shannon's paper, it explains the details better than I can. C refers the the capacity of a physical band-limited channel. By definition, C includes *all* the data carried by the channel. This includes the payload data and any overhead (parity bytes, etc) needed for the FEC layer if used. In-line comments below... "Kevin Neilson" <kevin_neilson@yahoo.com> wrote: >There's something I've never quite understood about Shannon's Law. It >states something like this: > >C = W*logbase2(1 + S/N) > >where C is channel capacity, bits/s > W = bandwidth, Hz > S/N = signal-to-noise ratio > >Theoretically, if using enough error-correction, you can transmit C bits/s >on a channel error-free. Yes, exactly as it says - bits are bits, and parity bits are information too. > >Say you determine that the channel capacity for a particular channel is >1Mbit/s. Does that include the error correction bits or not? Yes it includes error correction. >What if you >have a 1/2 rate code, where half of the bits are parity bits. Does that >mean you transmit 2Mbit on that channel (with 1Mbit capacity) for a net data >throughput of 1Mbit error-free? No, if the Shannon limit is 1Mbps, then thats all you get *including* parity. >Or does the 1Mbit include the partiy bits? Yes. > >-Kevin > Hope that helps. NemoArticle: 30887
A couple of things to check would be to monitor to see if DONE goes high, or INIT goes low. Also, do you see CCLK toggling at all? Is PROG being released properly? I would recommend walking through the Xilinx Configuration Problem Solver, it might help you get closer to the root of the problem. http://service.xilinx.com/support/cgi-bin/webcgi.exe?New,KB=config Cheers, Tom rebai chiheb wrote: > Hi, > > I have some problems in the configuration of virtex FPGA : > > I try to configure my xc300 FPGA in master serial mode with a 18v02 > serial PROM in AFX-PQ-240-100 prototype board. > I use the xilinx fundation software to generate the mcs file foe EPROM. > The bitsteam is dowloaded in the FPGA, but no result appear !!! > What happened ??? > > I'm completely helpless! > > Can anybody help me > > Chiheb REBAI. > IXL laboratory > University of Bordeaux > FRANCE.Article: 30888
In article <X1TH6.16348$482.81848@newsfeeds.bigpond.com>, murrayal@yahoo.com (auliya) wrote: > Hi, > > With this you have 2 options: > 1. Use a generic to pass in a parameter which will specify which of B1 > or B2 > to use. In this case you need to use 'if...generate' statements to > instantiate each option. You should the B1 and B2 entity/architecture > pairs > in separate files and use B as a 'wrapper' to choose which one to use. > > 2. Use a configuration declaration to specift which of B1 or B2 to use. > For > this you need an entity declaration (B) and the two architectures (B1 > and > B2). Basically, a configuration allows you to bind a specific > architecture > (out of many options) to an entity. 3. Run it through a C preprocessor first :-) That's not an entirely frivolous suggestion, either. For all its faults, the C preprocessor lets you do useful things that can't really be done in any other way, and I miss it badly in other languages. -- Steve Rencontre http://www.rsn-tech.co.uk //#include <disclaimer.h>Article: 30889
In article <3AEF11CD.CEA6992D@xilinx.com>, austin.lesea@xilinx.com (Austin Lesea) wrote: > See what I mean? > > Still confused after all these years. > > If the CRC is not information, then you don't need it. > > If the CRC is information, then you need to send it. > > I rest my case. > > Austin I disagree. The CRC (or whatever) is not information, but you do need to send it! The total message of N+CRC physical bit symbols only carries N bits of /information/, and it's that which Shannon's theorem applies to. I think the confusion arises because we automatically think that a 1 or 0 in the digital domain is a 'bit' in the Shannon sense, but it's not - it's just a symbol which can be used to encode bits. Adding a CRC increases the predictability of lost symbols, which means each 0/1 symbol carries less than one actual bit. Shannon tells us how many bits of genuine information we can transmit, but we're free to send as many symbols-which-superficially-look-like-bits-but-aren't as we like :-) -- Steve Rencontre http://www.rsn-tech.co.uk //#include <disclaimer.h>Article: 30890
In article <3af20db4.2149921@news.dtgnet.com>, nemo@dtgnet.com (Nemo) wrote: > C refers the the capacity of a physical band-limited > channel. By definition, C includes *all* the data carried by the > channel. This includes the payload data and any overhead (parity bytes, > etc) needed for the FEC layer if used. Sorry, but that doesn't add up. Shannon's Theorem says that you can carry C bps /without/ error. In that case, why have you included error detection and correction bits with the payload data?! -- Steve Rencontre http://www.rsn-tech.co.uk //#include <disclaimer.h>Article: 30891
I am looking for a prototyping board with the following characterizations: 1) TI 5408 or 548 or 5409 or 549 DSP. 2) Xilinx Virtex or Spartan-II FPGA. (Didn't find any in Optimagic or Xilinx WEB sites). Thanks for your help, Rotem.Article: 30892
Wrong. Go back and re-read his paper. This is really funny, and sad. Austin Steve Rencontre wrote: > In article <3AEF11CD.CEA6992D@xilinx.com>, austin.lesea@xilinx.com (Austin > Lesea) wrote: > > > See what I mean? > > > > Still confused after all these years. > > > > If the CRC is not information, then you don't need it. > > > > If the CRC is information, then you need to send it. > > > > I rest my case. > > > > Austin > > I disagree. The CRC (or whatever) is not information, but you do need to > send it! The total message of N+CRC physical bit symbols only carries > N bits of /information/, and it's that which Shannon's theorem applies to. > > I think the confusion arises because we automatically think that a 1 or 0 > in the digital domain is a 'bit' in the Shannon sense, but it's not - it's > just a symbol which can be used to encode bits. Adding a CRC increases the > predictability of lost symbols, which means each 0/1 symbol carries less > than one actual bit. > > Shannon tells us how many bits of genuine information we can transmit, but > we're free to send as many > symbols-which-superficially-look-like-bits-but-aren't as we like :-) > > -- > Steve Rencontre http://www.rsn-tech.co.uk > //#include <disclaimer.h>Article: 30893
Klaus, Ahhh, finally, someone who understands! Austin Klaus Falser wrote: > On Mon, 30 Apr 2001 17:03:09 GMT, "Kevin Neilson" > <kevin_neilson@yahoo.com> wrote: > > >There's something I've never quite understood about Shannon's Law. It > >states something like this: > > > >C = W*logbase2(1 + S/N) > > > >where C is channel capacity, bits/s > > W = bandwidth, Hz > > S/N = signal-to-noise ratio > > > >Theoretically, if using enough error-correction, you can transmit C bits/s > >on a channel error-free. > > > >Say you determine that the channel capacity for a particular channel is > >1Mbit/s. Does that include the error correction bits or not? What if you > > No, the 1 MBit/s its the rate for usable information. > > >have a 1/2 rate code, where half of the bits are parity bits. Does that > >mean you transmit 2Mbit on that channel (with 1Mbit capacity) for a net data > >throughput of 1Mbit error-free? Or does the 1Mbit include the partiy bits? > > > >-Kevin > > > > You must not think in terms of parity and CRC, Shannons law applies to > a much more generic principle. > It states, that given a noisy channel (where the signals at the end > of the channel are not in their ideal form anymore, but there is some > added noise), you are not able to exceed the information rate C. > > The used information coding scheme in the channel it's at your > decision and you can and will use any trick you want. > (AM, FM, QA[Modulation], Viterbi coding ....). > > Best regards. > Klaus > > Falser Klaus > R&D Electronics Department > Company : Durst Phototechnik AG > Vittorio Veneto Str. 59 > I-39042 Brixen > Voice : +0472/810235 > : +0472/810111 > FAX : +0472/830980 > Email : kfalser@IHATESPAMdurst.itArticle: 30894
Hey! Thats two (besides me) who understand...getting better. Austin Nemo wrote: > You may want to get ahold of Shannon's paper, it explains the details better > than I can. C refers the the capacity of a physical band-limited channel. By > definition, C includes *all* the data carried by the channel. This includes the > payload data and any overhead (parity bytes, etc) needed for the FEC layer if > used. In-line comments below... > > "Kevin Neilson" <kevin_neilson@yahoo.com> wrote: > > >There's something I've never quite understood about Shannon's Law. It > >states something like this: > > > >C = W*logbase2(1 + S/N) > > > >where C is channel capacity, bits/s > > W = bandwidth, Hz > > S/N = signal-to-noise ratio > > > >Theoretically, if using enough error-correction, you can transmit C bits/s > >on a channel error-free. > > Yes, exactly as it says - bits are bits, and parity bits are information too. > > > >Say you determine that the channel capacity for a particular channel is > >1Mbit/s. Does that include the error correction bits or not? > > Yes it includes error correction. > > >What if you > >have a 1/2 rate code, where half of the bits are parity bits. Does that > >mean you transmit 2Mbit on that channel (with 1Mbit capacity) for a net data > >throughput of 1Mbit error-free? > > No, if the Shannon limit is 1Mbps, then thats all you get *including* parity. > > >Or does the 1Mbit include the partiy bits? > Yes. > > > > >-Kevin > > > > Hope that helps. > > NemoArticle: 30895
> > If the CRC is not information, then you don't need it. > If the CRC is information, then you need to send it. Shannon states a theoretical bound. You can not expect to approach it with a CRC. And you will not approach it with superior schemes like reed solomon or expander codes. I believe that this line contains the source of the misconceptions in this thread: > > > Theoretically, if using enough error-correction, you can transmit C bits/s Not "enough" error-correction, but a "good enough" error correction. This means an error correction scheme that introduces the least amount of overhead for a given error rate. Shannon states, that there will never be an error correction scheme that can transport more than C usable data bits over a channel that can transport W bits if there is no noise present. > > > C = W*logbase2(1 + S/N) > > > where C is channel capacity, bits/s > > > W = bandwidth, Hz > > > S/N = signal-to-noise ratio Kolja SulimmaArticle: 30896
Victor Schutte schrieb: > > > FPGA? I don't think so. Rather use a CPLD. One flipflop for start and stop > (counter enable signal), nbit counter with clear and registered outputs. The > clock freq. can be much higher than a FPGA. It is also cheaper and easier to ??? Have a look at todays FPGAs. Virtex-E reaches 300 MHz and its cheap. Virtex II even reaches 420MHz. With the clock doubling (can be cascaded to 8x clock multiplication) in Virte-(E) you can apply a low speed clock outside the FPGA and have a nice high speed clock inside the FPGA. With Virtex II you even get a frwquncy synthesiser (DCM) with much more options. -- MFG FalkArticle: 30897
Insight Design Services has Verilog source that functions similarly to the Mot MC145428, which is a serially-interfaced UART. Not free, though. "Mark Walter" <maw@nospam.com> wrote in message news:1ALH6.226933$GV2.47295492@typhoon.san.rr.com... > Does anyone know of where I can find a free Verilog source code for a Serial > UART that can be used in a Xilinx XC4005XL FPGA? I am in need of such code > to add to a FPGA design I am making for remote access to the FPGA CPU... > > Thanks, > Mark > > >Article: 30898
I had two students build a fixed frequency UART as a one week homework. Including 16 times oversampling. If you do not need any fancy functionality, just build one yourself. Or you can download the code of my students. http://bounty.em.informatik.uni-frankfurt.de/~prak/ws0001/projekte/jan/index.html (page in german, download at the bottom) It not very good code, it had better students then them, but the UART work in its first version. Kolja Sulimma Kevin Neilson wrote: > Insight Design Services has Verilog source that functions similarly to the > Mot MC145428, which is a serially-interfaced UART. Not free, though.Article: 30899
At a certain level of abstraction, LogiBLOX and Coregen modules are essentially the same thing- pieces of customizable ip that a FPGA designer can drop into their design who's implementation details are not visible to the user. Their differences are the following: -delivery method (Coregen gives you edif cores, LogiBLOX delivers ngc files- binary netlists). -Parts supported (LogiBLOX only supports up through the 4000 family and derivatives). -Interface method (Coregen uses a slick java interface- Logiblox a simple GUI w/ pull-down menus etc.) One other thing to note is that, going forward, Coregen will continue to be a part of the Xilinx toolset and LogiBLOX will be phased out. Hope this helps, Tim Jaynes CAE Noddy wrote: > Hi, > > I've just started teaching myself how to program FPGA's... > > What is the difference between a LogiBLOX module, and a Core module? > > Thanks > adrian
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z