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Suggestion: Try and use a PIC with either a CODEC or even a cheaper Delta modulator. With Delta modulation you will achieve excellent results with 100kbit/s. Speech quality will also be acceptable with bit rates lower than 64kbit/s. With PICs running at 5mips you should be able to perform at least limited speech processing. Can't you use a simple resistor/capacitor network? Some of the best solutions sometimes cost a couple of cents. I would agree with the other people that a FPGA is too expensive for simple speech tasks. "catherina" <floreq10@hotmail.com> wrote in message news:99g823$1gb$1@news.qub.ac.uk... > hello, > > a simple question, how many bits should be allocated to cover the natural > speech signal dynamic ? > > I have never seen an implementation related to speech processing on FPGA. > Is that because there is no need for Mhz speed ? > > > > >Article: 30201
On Tue, 27 Mar 2001 17:58:30 +0100, "david garnett" <dave.garnett@metapurple.co.uk> wrote: >I've run into power up problems with the XC95288XL that are similar to those >encountered with fpga's. The power up ramp is definitely not monotonic and >has three or four quite large current spikes - my current probe says >1.5A ! >There are no numbers that I can find in the datasheet about powerup - only >an exhortation to provide a smoothly rising ramp. The end result is a chip >that just hangs up. > >So, since since some of you must have found this problem and got round it, >what did you do ? > >I'm thinking along the lines of hanging a large low esr cap or two off the >5V rail and using a low dropout regulator with shutdown (LT1528) for the 3.3 >V rail. So, turn on the +5, wait 200 ms and then turn on the LDO. > >Any comments/ideas ? > >regards >Dave > >-- >"Don't worry - I've read all about this sort of thing in books !" >Dave Garnett Metapurple Limited >dave.garnett@metapurple.co.uk > > > We are using the LM1117 3.3V LDO (only 800 mA) for powering 2 XC95288XL from the 5V line. No delay is used. Until now we had no problems, so I'm surprised about your 1.5A spikes. Best regards Falser Klaus R&D Electronics Department Company : Durst Phototechnik AG Vittorio Veneto Str. 59 I-39042 Brixen Voice : +0472/810235 : +0472/810111 FAX : +0472/830980 Email : kfalser@IHATESPAMdurst.itArticle: 30202
catherina schrieb: > I have never seen an implementation related to speech processing on FPGA. > Is that because there is no need for Mhz speed ? In real: FPGAs are not for free. Xilinx and Altera like You have to pay for them. So you will see them only in advanced ( no low cost ) speech signal processing. bye michael strothjohannArticle: 30203
"Dave Brown" <dbrown@novatel.ca> writes:
> for a given device? And finally, how big would a hex file be for an
> XCV1000E?
I'm using XC18V04's for the XCV1000E and I generate two MCS files. One
is 1441932 and the other is 822760 bytes. It takes almost one hour to
load and program these files on a DataIO 3980 programmer...
Petter
--
________________________________________________________________________
Petter Gustad 8'h2B | (~8'h2B) - Hamlet http://www.gustad.com
#include <stdio.h>/* compile/run this program to get my email address */
int main(void) {printf ("petter\100gustad\056com\nmy opinions only\n");}
Article: 30204
I'm trying to speed up my par jobs using multiple hosts. I have some
older sparc's which have two cpu's. I tried to list the host twice in
the nodenames file, but it seems like par is "smart" enough to detect
this and only start one par process on the machine. Any suggestions?
If only Xilinx could provide their software under Linux, then I could
run par on my Linux clusters :-(
Petter
--
________________________________________________________________________
Petter Gustad 8'h2B | (~8'h2B) - Hamlet http://www.gustad.com
#include <stdio.h>/* compile/run this program to get my email address */
int main(void) {printf ("petter\100gustad\056com\nmy opinions only\n");}
Article: 30205Hello! Most of the answers I get are related to one of the following: - How I could get the signal to the correct logic level without using the CPLD (As Peter is suggestion below) - How to avoid having the inputs removed by the software (There were no inputs in the first place). The best response so far was the "out <= inputX or '1'". Unfortunatly it does not work, as inputX is optimized away early in the process, as it is redundant. My current solution is the following: "out <= inputX" by using an input that has an external pullup. This solution is very unsatisfactory, because I might not allways have an handy Input like this around.. So here is the import question again: ----------- How can I implement the following VHDL code in the XC95xx family without using bogus extra inputs: out <= '1'; ----------- One application for this, is to program the frequency of an ICS525-01 via JTAG. Of course I can replace the CPLD with a dip switch and pullup, as Peter suggests below. And I also can replace my Spartan-II by a PLX PCI bridge, and I can replace my Virtex by TI DSP, and wow! I suddently got rid off all my Foundation problems :-) Another application is to set the outputs of an CPLD that is allready soldered but not used yet to a known level. Overall this error of the foundation software falls in the category "Errors that really should be warnnigs". Kolja Peter Alfke wrote: > Yes, since the outputs are 3-stated ( with a week pull-up, I assume ), you can > generate a High by connecting 10 kilohm pull-ups on the pins in question. Once the > chip is active, the driver will easily override these external resistors. > > Peter Alfke, Xilinx ApplicationsArticle: 30206
Hello I am a student who work on the xilinx virtexe XCV100EPQ240, when I use the project manager I have the following error message _________________________________________________________________________ JTAG Programmer Started 2001/03/28 11:13:19 Cable Hardware: 1 Cable Firmware: 101 Cable FPGA: c Cable Algorithm: 100 Loading Boundary-Scan Description Language (BSDL) file 'C:/Xilinx/virtexe/data/xcv100e_pq240.bsd'.....completed successfully. Checking boundary-scan chain integrity...ERROR:JTag - Boundary-scan chain test failed at bit position '3' on instance 'toto(Device1)'. A problem may exist in the hardware configuration. Check that the cable, scan chain, and power connections are intact, that the specified scan chain configuration matches the actual hardware, and that the power supply is adequate and delivering the correct voltage. ERROR:JTag - Boundary scan chain has been improperly specified. Please check your configuration and re-enter the boundary-scan chain information. Boundary-scan chain validated unsuccessfully. ERROR:JTag - : The boundary-scan chain has not been declared correctly. Verify the syntax and correctness of the device BSDL files, correct the files, reset the cable and retry this command. ERROR:JTag - : The boundary-scan chain has not been declared correctly. Verify the syntax and correctness of the device BSDL files, correct the files, reset the cable and retry this command. _________________________________________________________________________ Someone could help me? I dont know if my connectic with the multilinx is correct (on the jtag port) or if my schema is right with the good pin number!Article: 30207
Hallo Petter, who about a simple shell script, which replace the par command ? #!/bin/csh ...../xilinx/bin/sol/par $* ...../xilinx/bin/sol/par $* I don't know exactly, if the computed results of the two p&r jobs are recognized. > I'm trying to speed up my par jobs using multiple hosts. I have some > older sparc's which have two cpu's. I tried to list the host twice in > the nodenames file, but it seems like par is "smart" enough to detect > this and only start one par process on the machine. Any suggestions? > > If only Xilinx could provide their software under Linux, then I could > run par on my Linux clusters :-( take the NT software and try the emulation software wine. ciao JoergArticle: 30208
It depends on how much processing you are doing. Audio is slow enough that you can easily do bit serial for many channels through the same hardware, and even then you can get it into a SpartanII-50 with room to spare at a cost of less than $17 in small quantities. A studio mixer might be an application where an FPGA makes sense (Metalithic did something in this area about 10 years ago with FPGAs). It may also make sense where you have other functions to take care of that you can integrate into the FPGA. There are several barriers to using the FPGA in the average audio project: 1) The horsepower needed to do the task is available in cheaper microporcessors, so the more expensive FPGA is not warranted until you are doing enough processing to push you into a more expensive DSP processor. 2) FPGA talent with the systems know-how to keep the design small (ie bit serial, channel multiplexing) is hard to come by. 3) Many DSPs are already integrated with decent ADCs and DACs, so the integration with the processor may be higher, 4) the DSP processor is often needed for control/front panel applications on a part time basis anyway. Michael Strothjohann wrote: > > catherina schrieb: > > > I have never seen an implementation related to speech processing on FPGA. > > Is that because there is no need for Mhz speed ? > > In real: FPGAs are not for free. > Xilinx and Altera like You have to pay for them. > So you will see them only in advanced ( no low cost ) > speech signal processing. > bye > michael strothjohann -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.comArticle: 30209
Dear All, Does anyone have any comparison info on the P4 vs Athlon, running the typical ModelSim, Leonardo, Xilinx P&R tools? Is DDR for Athlon worth the price difference? On large designs, my simulations can take a couple of hours, so a few % can make a significant difference. Thanks, Phil Martin Convergence Media Solutions Ltd.Article: 30210
Hi, we have a problem with programming a Virtex XCV1000BG540-4 ES (engineering sample) using JTAG. The JTAG Programmer gets a wrong Device ID and does not download the bitstream. What can we do? Where are the differences between the engineering sample and a normal device? Are there differences between both devices at download via JTAG and serial or parallel download? Do you know the Device IDs? Can anybody help me? ThanksArticle: 30211
On Wed, 28 Mar 2001 14:40:30 +0100, "Phil Martin" <phil@martphil.demon.co.uk> wrote: >Dear All, > >Does anyone have any comparison info on the P4 vs Athlon, running the >typical ModelSim, Leonardo, Xilinx P&R tools? > In normal integer apps Athlon is much faster than a P4 even when the comparison is 1.2 GHz Athlon to a 1.5 GHz P4 and now you can buy a 1.33 GHz Athlon. >Is DDR for Athlon worth the price difference? > Athlon large cache hides most of the %100 bandwidth increase; the difference between PC133 and PC266 is around %7 but this might be enough for you from your description. >On large designs, my simulations can take a couple of hours, so a few % can >make a significant difference. Muzaffer FPGA DSP Consulting http://www.dspia.comArticle: 30212
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I can only comment on the Xilinx PCI-X core which is available right now at
66Mhz. The 133Mhz version of this core will be ready soon and yes . . . .
* Virtex-II device can operate PCI-X at 133Mhz.
* The core PCI-X code is encrypted
* A testbench is included which can very easily be modified to do some
powerful testing. (there are dummy targets 32bit and 64bit and the
stimulus file will simulate either single data phase transactions or
burst transactions with some slight modification.
* The interface signals are very straightforward. The Core decodes BAR
hits and informs the user application. The Core will also arbitrate
for bus access as well as verify bus mode on startup. The core uses
just a few signals to interface the PCI bus with the user application.
The user application is responsible for sourcing and sinking of data.
Chris
Chris Briggs wrote:
> I'm looking for recommendations for a PCI-X core. I'm working on a
> design which will be initially implemented in an FPGA. We're targeting a
> Virtex-II 3000. For initial development, we'll be using PCI @ 33 MHz,
> then we plan to switch to PCI-X @ 66 MHz (or faster, if possible).
> Ultimately, we want to harden the design into an ASIC and have PCI-X @
> 133 MHz. This is an embedded application, so once we switch to PCI-X, we
> won't actually need to worry
> about (plain) PCI anymore, and don't expect to need PCI @ 66 MHz.
>
> I know about and am looking into the following cores:
> 1. Xilinx LogiCORE PCI-X
> 2. inSilicon PCI-X
> 3. DCM Technologies Corex-V10 and V20
> 4. Synopsys DesignWare DW_PCIX
> 5. Compaq X-caliber (free reference implementation)
>
> Does anyone have any experience with any of these, or others, that they
> can share? I realize that most detailed info on these comes with an NDA
> attached.
>
> My main questions are these:
> 1. How fast can I do PCI-X in a Virtex-II?
> 2. Does the core include unencrypted RTL source? (looking for Verilog)
> 3. Does it come with a testbench? (And is it any good?)
> 4. What does the interface to the application logic look like?
>
> Any info is appreciated. TIA.
>
> -cb
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<!doctype html public "-//w3c//dtd html 4.0 transitional//en">
<html>
I can only comment on the Xilinx PCI-X core which is available right now
at 66Mhz. The 133Mhz version of this core will be ready soon
and yes . . . .
<ul>
<li>
Virtex-II device can operate PCI-X at 133Mhz.</li>
<li>
The core PCI-X code is encrypted</li>
<li>
A testbench is included which can very easily be modified to do some powerful
testing. (there are dummy targets 32bit and 64bit and the stimulus
file will simulate either single data phase transactions or burst transactions
with some slight modification.</li>
<li>
The interface signals are very straightforward. The Core decodes
BAR hits and informs the user application. The Core will also arbitrate
for bus access as well as verify bus mode on startup. The core uses
just a few signals to interface the PCI bus with the user application.
The user application is responsible for sourcing and sinking of data.</li>
</ul>
Chris
<br>
<p>Chris Briggs wrote:
<blockquote TYPE=CITE>I'm looking for recommendations for a PCI-X core.
I'm working on a
<br>design which will be initially implemented in an FPGA. We're targeting
a
<br>Virtex-II 3000. For initial development, we'll be using PCI @ 33 MHz,
<br>then we plan to switch to PCI-X @ 66 MHz (or faster, if possible).
<br>Ultimately, we want to harden the design into an ASIC and have PCI-X
@
<br>133 MHz. This is an embedded application, so once we switch to PCI-X,
we
<br>won't actually need to worry
<br>about (plain) PCI anymore, and don't expect to need PCI @ 66 MHz.
<p>I know about and am looking into the following cores:
<br>1. Xilinx LogiCORE PCI-X
<br>2. inSilicon PCI-X
<br>3. DCM Technologies Corex-V10 and V20
<br>4. Synopsys DesignWare DW_PCIX
<br>5. Compaq X-caliber (free reference implementation)
<p>Does anyone have any experience with any of these, or others, that they
<br>can share? I realize that most detailed info on these comes with an
NDA
<br>attached.
<p>My main questions are these:
<br>1. How fast can I do PCI-X in a Virtex-II?
<br>2. Does the core include unencrypted RTL source? (looking for Verilog)
<br>3. Does it come with a testbench? (And is it any good?)
<br>4. What does the interface to the application logic look like?
<p>Any info is appreciated. TIA.
<p>-cb</blockquote>
</html>
--------------F1BF8BF186D2E19DABB77D31--
Article: 30213
Hi,
I got a strange problem when trying to print a chip image from the
Xilinx FPGA editor (xilinx foundation 3.2i). After I set up the printer
correctly and press the print button Windows reports that the program
will be terminated because of errors. Does anybody know this problem and
have a solution ?
Would be nice :-)
Matthias
--
-------------------------------------------------
\ Matthias Fuchs \
\ esd electronic system design Gmbh \
\ Vahrenwalder Straße 205 \
\ D-30165 Hannover \
\ email: matthias.fuchs@esd-electronics.com \
\ phone: +49-511-37298-0 \
\ fax: +49-511-37298-68 \
--------------------------------------------------
Article: 30214
petter,
try using upper cases:
foo
Foo
FOO
FOo
this should work. if not, add aliases for the machine.
foo
foo1
foo2
foo3
.
.
brant
Petter Gustad wrote:
> I'm trying to speed up my par jobs using multiple hosts. I have some
> older sparc's which have two cpu's. I tried to list the host twice in
> the nodenames file, but it seems like par is "smart" enough to detect
> this and only start one par process on the machine. Any suggestions?
>
> If only Xilinx could provide their software under Linux, then I could
> run par on my Linux clusters :-(
>
> Petter
> --
> ________________________________________________________________________
> Petter Gustad 8'h2B | (~8'h2B) - Hamlet http://www.gustad.com
> #include <stdio.h>/* compile/run this program to get my email address */
> int main(void) {printf ("petter\100gustad\056com\nmy opinions only\n");}
Article: 30215"Phil Hays" <spampostmaster@home.com> wrote... > I would like to have a file for each type of device, with the Pin number (such > as AB22), the physical name (PIN2), the adjacent CLB (X1Y14), the bank number > and a description of the pin. A sample line, not from a real part, might look > like: > > PAD20 X1Y14 AB22 1 IO_LO1P/VREF > > Currently, for a design going into Virtex E, I am cutting and pasting out of the > .pdf pinout table to build a .ucf file. Starting with the .pdf pinout table I > get the bank and the pin name, but not the pad or the nearest CLB, unless I care > to edit them in by hand. > > Starting a file like this, I can easily edit this into ucf format, easily sort > and search by pad or by CLB location as well as pin name. This would make > creating a pinout much easier and less error prone. My question, does this sort > of file exist for Virtex E? If so, how can I get a copy? If not, why not? We have all been asking for this for ages. Even a simpler version would be useful. Does anyone out there have any leverage with Xilinx?Article: 30216
Does anyone know of test vector generation free- or shareware? Thanks. ----- Posted via NewsOne.Net: Free (anonymous) Usenet News via the Web ----- http://newsone.net/ -- Free reading and anonymous posting to 60,000+ groups NewsOne.Net prohibits users from posting spam. If this or other posts made through NewsOne.Net violate posting guidelines, email abuse@newsone.netArticle: 30217
Hi, I have this 9Ux400mm board that has one JTAG chain covering 32 devices. 12 of them are Altera devices. the oethes are TI and XILINX. Configuration information (typically Altera POF and SOF files) is sent out from a computer through the Byte-Blaster. All JTAG lines are buffered initially by a little PLD (already programmed), and in addition, TCK and TMS are buffered with the help of a TI '245, so that each TCK line only serves 4 or 5 loads. The JTAG chain has been properly configured and tested, and it DOES work (i.e. I can configure all the devices) -- most of the time. What is strange is that when it does not work, the following happens: If I press "Detect JTAG Chain Info" button, the correct information is displayed, every time, with no problem. However, if I go and try to program the device, it claims that the hardware does not match the chain information. Now remember, most of the times, it DOES work, so the solution offered in altera's solution database is not adequate. My feeling is that there may be a problem in a line, probably TCK. Maybe the IDCODE of the devices is not being reported correctly some of the time. With that in mind, I downloaded the 2nd version of IDCODE.ZIP, a little jam file that tests the chain and reads the idcode of the devices involved. I run it, and found that it NEVER fails, not even once. So the IDCODE and other chain characteristics are always being reported correctly. So what else is being checked at programming time that I am having problems with? Any ideas on how to solve the puzzle? Emanuel emachado@bu.eduArticle: 30218
Phil, Yes, we do have package pinout tables with this info. These pinout tables are available in text format for different packages for all Virtex devices. The package files has pinout in the following format Physical Row/Col-RAM Package VCCO IO Output LVDS Name Location Name Bank Type Asynchronous Call the hotline to get these package pinout in text format or let me know the exact device /package and I will email it to you. -Vikram Xilinx Applications Phil Hays wrote: > I would like to have a file for each type of device, with the Pin number (such > as AB22), the physical name (PIN2), the adjacent CLB (X1Y14), the bank number > and a description of the pin. A sample line, not from a real part, might look > like: > > PAD20 X1Y14 AB22 1 IO_LO1P/VREF > > Currently, for a design going into Virtex E, I am cutting and pasting out of the > .pdf pinout table to build a .ucf file. Starting with the .pdf pinout table I > get the bank and the pin name, but not the pad or the nearest CLB, unless I care > to edit them in by hand. > > Starting a file like this, I can easily edit this into ucf format, easily sort > and search by pad or by CLB location as well as pin name. This would make > creating a pinout much easier and less error prone. My question, does this sort > of file exist for Virtex E? If so, how can I get a copy? If not, why not? > > -- > Phil HaysArticle: 30219
The package file format did not show up properly in my earlier mail. Physical Row/Col-RAM Package VCCO IO Output LVDS Name Location Name Bank Type Asynchronous -Vikram Vikram Pasham wrote: > Phil, > > Yes, we do have package pinout tables with this info. > These pinout tables are available in text format for different packages for all > Virtex devices. > > The package files has pinout in the following format > > Physical Row/Col-RAM Package VCCO IO Output LVDS > Name Location Name Bank Type > Asynchronous > > Call the hotline to get these package pinout in text format or let me know the > exact device /package and I will email it to you. > > -Vikram > Xilinx Applications > > Phil Hays wrote: > > > I would like to have a file for each type of device, with the Pin number (such > > as AB22), the physical name (PIN2), the adjacent CLB (X1Y14), the bank number > > and a description of the pin. A sample line, not from a real part, might look > > like: > > > > PAD20 X1Y14 AB22 1 IO_LO1P/VREF > > > > Currently, for a design going into Virtex E, I am cutting and pasting out of the > > .pdf pinout table to build a .ucf file. Starting with the .pdf pinout table I > > get the bank and the pin name, but not the pad or the nearest CLB, unless I care > > to edit them in by hand. > > > > Starting a file like this, I can easily edit this into ucf format, easily sort > > and search by pad or by CLB location as well as pin name. This would make > > creating a pinout much easier and less error prone. My question, does this sort > > of file exist for Virtex E? If so, how can I get a copy? If not, why not? > > > > -- > > Phil HaysArticle: 30220
Hi VHDL wizards, I'm using foundation 2.1i to program some xilinx XC4005E. I'm quite new to vhdl FPGA programming (up to now, I was not targeting to real devices and I was in the "everything is perfect" theoretical world). I have a piece of code but the synthetizer doesn't react as I would expect at first glance. I have to following simple code (rxready and autosync are two input ports and datamode and syncerr are output ports): process(rxready, autosync) begin if rxready='0' then syncerr <= '1'; if autosync='1' then datamode <= '0'; else datamode <= '1'; end if; else syncerr <= '0'; datamode <= '1'; end if; end process; When I synthetize it with Fpga Express I got a warning saying that no net is attached to port autosync. I dont understand why and if I modify the code the following way ( I believe that the functionnality is the same ): process(rxready, autosync) begin if rxready='0' and autosync='1' then datamode <= '0'; syncerr <= '1'; else syncerr <= not rxready; datamode <= '1'; end if; end process; Then, the synthetizer doesn't report the warning anymore. Does anybody has an idea about what I'm doing wrong ? Many thanks in advance. Jean-Marie -- _______________________________________ | | | Jean-Marie Bussat | | Lawrence Berkeley National Laboratory | | 1 Cyclotron Road - MS 50A-6134 | | BERKELEY, CA 94720 - USA | | Email: JMBussat@lbl.gov | | Phone: (510)-486-5687 | | Fax: (510)-486-5977 | |_______________________________________|Article: 30221
A pointer to the web address would be terrific. http://www.xilinx.com/support/.... <g> "Vikram Pasham" <Vikram.Pasham@xilinx.com> wrote > The package file format did not show up properly in my earlier mail. > > Physical Row/Col-RAM Package VCCO IO Output LVDS > Name Location Name Bank Type Asynchronous > <snip> > > Call the hotline to get these package pinout in text format or let me know the > > exact device /package and I will email it to you. > > > > -Vikram > > Xilinx ApplicationsArticle: 30222
Vikram Pasham wrote: > The package file format did not show up properly in my earlier mail. > > Physical Row/Col-RAM Package VCCO IO Output LVDS > Name Location Name Bank Type Asynchronous > > -Vikram > > Vikram Pasham wrote: If you have them why don't you just put them on the Web ?Article: 30223
Frederic, Try to see if you can read Device id using JTAG programmer. Also make sure all the JTAG pins are connected properly . Refer sol#8255 for some JTAG debugging tips. http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=8255 -Vikram Xilinx Applications Frederic Darre wrote: > Hello I am a student who work on the xilinx virtexe XCV100EPQ240, > when I use the project manager I have the following error message > > _________________________________________________________________________ > JTAG Programmer Started 2001/03/28 11:13:19 > Cable Hardware: 1 > Cable Firmware: 101 > Cable FPGA: c > Cable Algorithm: 100 > Loading Boundary-Scan Description Language (BSDL) file > 'C:/Xilinx/virtexe/data/xcv100e_pq240.bsd'.....completed successfully. > Checking boundary-scan chain integrity...ERROR:JTag - Boundary-scan chain > test failed at bit position '3' on instance 'toto(Device1)'. > A problem may exist in the hardware configuration. > Check that the cable, scan chain, and power connections are intact, > that the specified scan chain configuration matches the actual hardware, > and > that the power supply is adequate and delivering the correct voltage. > ERROR:JTag - Boundary scan chain has been improperly specified. Please > check your configuration and re-enter the boundary-scan chain information. > Boundary-scan chain validated unsuccessfully. > ERROR:JTag - : The boundary-scan chain has not been declared correctly. > Verify the syntax and correctness of the device BSDL files, correct the > files, > reset the cable and retry this command. > ERROR:JTag - : The boundary-scan chain has not been declared correctly. > Verify the syntax and correctness of the device BSDL files, correct the > files, > reset the cable and retry this command. > _________________________________________________________________________ > > Someone could help me? > I dont know if my connectic with the multilinx is correct (on the jtag port) > or if my schema is right with the good pin number!Article: 30224
Chris Briggs wrote: > I'm looking for recommendations for a PCI-X core. I'm working on a > design which will be initially implemented in an FPGA. We're targeting a > Virtex-II 3000. For initial development, we'll be using PCI @ 33 MHz, > then we plan to switch to PCI-X @ 66 MHz (or faster, if possible). > Ultimately, we want to harden the design into an ASIC and have PCI-X @ > 133 MHz. This is an embedded application, so once we switch to PCI-X, we > won't actually need to worry > about (plain) PCI anymore, and don't expect to need PCI @ 66 MHz. > > I know about and am looking into the following cores: > 1. Xilinx LogiCORE PCI-X > 2. inSilicon PCI-X > 3. DCM Technologies Corex-V10 and V20 > 4. Synopsys DesignWare DW_PCIX > 5. Compaq X-caliber (free reference implementation) > > Does anyone have any experience with any of these, or others, that they > can share? I realize that most detailed info on these comes with an NDA > attached. > > My main questions are these: > 1. How fast can I do PCI-X in a Virtex-II? > 2. Does the core include unencrypted RTL source? (looking for Verilog) > 3. Does it come with a testbench? (And is it any good?) > 4. What does the interface to the application logic look like? > > Any info is appreciated. TIA. > > -cb Could someone enlighten me ? Is PCI-X just a clock speed uprated 66MHz PCI or are there any fundamental differences ? As far as I can see the only significant change is to allow split cycles.
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