Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Find the latest electrical/electronic engineering jobs http://a1ajobs.com/ee/ Use our archives to find your next job.. Easy keyword search engine. ASIC,RF,DSP,FPGA VHDL etc.. thanks for letting us post here..Article: 30276
hello ! i've used "initial" command in Verilog language but the program can't run . Now i use the software Xilinx Foundation 2.1i . Please tell me more . Thank you very muchArticle: 30277
You did not give me very much to go on. You will admit, that your description of your problem is very limited. There is a small chance that your problem is that the "initial" statement is not synthesizable. In Verilog, you can use initial statements for simulations but not for synthesis, which is something that the language itself poorly explains. The Foundation software does not allow you to do pre-synthisis simulation. If my memory serves me correctly, you have to synthesize first before the simulation will run. This is very limiting and it is the reason that I had to purchase a real verilog simulator. So, if your objective was a pre-synthesis simulation, where the "initial" statement was a valid option, you would not be able to do it using Founadation tools by themselves. I hope that this helps. Tom luu thanh trung wrote: > hello ! > i've used "initial" command in Verilog language but the program can't run . Now i use the software Xilinx Foundation 2.1i . > Please tell me more . > Thank you very muchArticle: 30278
Hi My name is Fredrik Theander I'm working on my exam thesis. My topic is programmable analog devices I currently evaluating Anadgims FPAA. I wonder if anyone have had any experience with it? I would be glad to find someone who i can swap ideas with. regards Fredrik TheanderArticle: 30279
"Peter Alfke" <peter.alfke@xilinx.com> wrote in message news:3AC4BC03.7161A17D@xilinx.com... > Virtex-II additionally offers read-before-write as a configuration option. Amongst other applications, this is great for speeding up stores into data caches. Jan Gray, Gray Research LLCArticle: 30280
Hi, I you follow the link, you can have a good idea of what the thing is. I think that the word "hypercomputer" is somewhat inapropriate. This developpment may lead to a kind of hypercomputer but for now, this is just something that uses the old idea of using FPGAs as reconfigurable coprocessors. On the picture http://acmb.larc.nasa.gov/olaf/inhal34.jpg you can clearly see that HAL is in fact a "normal" PC motherboard (you can just see the edge of the board but I dont think that there is anything special on it) connected to a PCI expansion board filled with FPGA. Unless there is something else not described, that's it. The few snapshots of the "user interface" to HAL show a GUI where it seems that you can place functional blocks such as mathematical functions and connect them together. I think that there should be a kind of "compiler" that should use a set of pre-written vhdl/verilog libraries where each functional block is described. Kept hidden from the user, there should be a Xilinx synthetizer/optimizer that should compile the resulting vhdl code and download the bitstream to the FPGAs. I guess they should also have written a set of standard functions to interface the HAL board to the PC. By the way, everything here is pure extrapolation from the few amount of available information. This is also how I saw things when I started to think about reconfigurable coprocessor made using FPGA (but in my case I was thinking about neural networks applications). Anyway, I think that this stuff should work and giving enough time to them to finalize the interface, they should be able to produce something that would completely hide the FPGAs to the end user. But we are still far from a 100% FPGA based "hypercomputer"... Jean-Marie -- _______________________________________ | | | Jean-Marie Bussat | | Lawrence Berkeley National Laboratory | | 1 Cyclotron Road - MS 50A-6134 | | BERKELEY, CA 94720 - USA | | Email: JMBussat@lbl.gov | | Phone: (510)-486-5687 | | Fax: (510)-486-5977 | |_______________________________________|Article: 30281
Steven Sanders <sanders@imec.be> writes: > What I`m looking for is a R/S ENcoder with following fixed > specifications (VHDL, no IP cores or netlists): If you can find a decoder that supports erasure pointers, it is possible to use it as an encoder by setting the error control symbols to zero, setting the erasure pointers for each error control symbol, and doing a decode (correction). This works because RS requires two ECC symbols to locate and correct an error, but only one symbol to correct an error at a known location.Article: 30282
Yo! On Fri, 30 Mar 2001 11:14:36 +0200, "Victor Schutte" <victors@mweb.co.za> wrote: >This reply deviates slightly from your question but these are some of the >answers I give when people ask FPGA vs CPLD questions. Since your answers deviate a bit from what I have learned I add some coments. >You use the same tools and languages but the end products differ quite a >lot. CPLDs tend to be faster than FPGAs because of the internal structure. >The signals in an FPGA usually have to travel through various gates, thus >adding delays. Routing is less complex in a CPLD but FPGA "signals" do not travel through various "gates". Routing may add delays, but not "gates". >If a CPLD is specified as a 10ns device it indicates the total (minimum) >time from an input to output pin. Example: If you want to build a high freq. >oscillator a CPLD would be the choice(if you are looking at PLDs). Using a >10ns device you can theoretically clock up to 100MHz (one of my friends did >this a few weeks ago) I don't think anyone should build an oscillator from a CPLD or FPGA. >The delays in an FPGA is specified from gate to gate. If you use a 3ns FPGA >you might think whatever you design will clock 300MHz but looking >internally at all the different gates the signal has to travel the maximum >frequency drops considerally. My one CPU design runs on -3 FPGA device but >the final max clock frequency is only 20MHz. By reading the datasheet you learn that the physical limitation of the device is a 3 ns delay, this is the short path. But you have to consider the longest combinational path. This may well be more than 3 ns, in fact this depends on how well you have designed the circuit. My 1 cent / JonasArticle: 30283
--------------7B0D70B883DDDD60C93BAF9A Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Dave, Poor designs operate equally poor across architectures. Improperly constrained designs tend to operate unreliably regardless of target. People sometimes choose a part because it is "foolproof" only to discover just how foolish life can be sometimes. A rule I used to use when I made these kinds of decisions is: if it is small enough to fit in a CPLD, and I don't have to reprogram it in the field (from a network management system for example), then use a CPLD. Else, use a FPGA. If the FPGA isn't fast enough, figure out how to use the massive parallelism of the FPGA to do the job at the speed it can operate at. I used hundreds of thousands of CPLD's in very low power (line powered telecom) applications as line coders/loopback code detectors. It was a simple circuit, used standard codes used since the dawn of T1, and I knew it could never be changed (in my lifetime at least). I also decided to use an FPGA for a fiber optic framer/codec. When we had shipped the 10,000th unit, the customer came back and said "it won't send all 0's." [ I kid you not.] All 0's is what the customer (secret governement user) wanted to send. All day, all night. They needed to know that the n-th 0 was really the n-th 0, and not the n-th plus 1 "0". It seems that the codec saw all 0's, and substituted a keep alive code instead. For some unknown reason, every 0 in its proper place and order was critically important to the national security! They told me it was encrypted. Wow, some encryption algorithm! We had to reprogram those units for this one site (no 0 substitution). We could put out a notice that if anyone else needed this "feature" we would update them. No one else did, and we were all heros due to the zeroes. Numerically yours, Austin (the zero hero) Speedy Zero Two wrote: > All, > > I've been told that logic designs implemented within FPGA's are more > temperamental than CPLD's. > > Any insight ? > > Cheers > Dave --------------7B0D70B883DDDD60C93BAF9A Content-Type: text/html; charset=us-ascii Content-Transfer-Encoding: 7bit <!doctype html public "-//w3c//dtd html 4.0 transitional//en"> <html> Dave, <p>Poor designs operate equally poor across architectures. <p>Improperly constrained designs tend to operate unreliably regardless of target. <p>People sometimes choose a part because it is "foolproof" only to discover just how foolish life can be sometimes. <p>A rule I used to use when I made these kinds of decisions is: if it is small enough to fit in a CPLD, and I don't have to reprogram it in the field (from a network management system for example), then use a CPLD. <p>Else, use a FPGA. If the FPGA isn't fast enough, figure out how to use the massive parallelism of the FPGA to do the job at the speed it can operate at. <p>I used hundreds of thousands of CPLD's in very low power (line powered telecom) applications as line coders/loopback code detectors. It was a simple circuit, used standard codes used since the dawn of T1, and I knew it could never be changed (in my lifetime at least). <p>I also decided to use an FPGA for a fiber optic framer/codec. When we had shipped the 10,000th unit, the customer came back and said "it won't send all 0's." <b>[ I kid you not.]</b> All 0's is what the customer (secret governement user) wanted to send. All day, all night. They needed to know that the n-th 0 was really the n-th 0, and not the n-th plus 1 "0". It seems that the codec saw all 0's, and substituted a keep alive code instead. For some unknown reason, every 0 in its proper place and order was critically important to the national security! They told me it was encrypted. Wow, some encryption algorithm! <p>We had to reprogram those units for this one site (no 0 substitution). We could put out a notice that if anyone else needed this "feature" we would update them. No one else did, and we were all heros due to the zeroes. <p>Numerically yours, <p>Austin (the zero hero) <br> <p>Speedy Zero Two wrote: <blockquote TYPE=CITE>All, <p>I've been told that logic designs implemented within FPGA's are more <br>temperamental than CPLD's. <p>Any insight ? <p>Cheers <br>Dave</blockquote> </html> --------------7B0D70B883DDDD60C93BAF9A--Article: 30284
> My name is Fredrik Theander I'm working on my exam thesis. My topic is > programmable analog devices I currently evaluating Anadgims FPAA. I wonder > if anyone have had any experience with it? > I would be glad to find someone who i can swap ideas with. We have bought a eval kit at the Motorola time, short before they stopped that thing. Since Anadigm has taken over the technology we play around again with MPAA020 in the students lab to demonstrate switched capacitor principles, aliasing and the different circuit ideas. Also discussing, what the future use will be. regards, Bertram -- Bertram Geiger, bgeiger@aon.at HTL Bulme Graz-Goesting - AUSTRIAArticle: 30285
In article <3AC47780.F512E811@imec.be>, sanders@imec.be says...
> Hello,
>
> What I`m looking for is a R/S ENcoder with following fixed
> specifications (VHDL, no IP cores or netlists):
>
> n=255
> k=239
> GF(256)
> p(x)=1 + x^2 + x^3 + x^4 + x^8 (DVB standard)
> g(x)=(x+alpha^0)...(x+alpha^15)
>
> Does someone have any VHDL, architecture descriptions, references
> for this coder?
>
> Thanx in advance!
>
> Steven
>
Near simple problem :-)
Michal Meloun
`timescale 1ns / 1ps
//
// TX Reed-Solomon encoder
//
module tx_rs (
Reset,
Clk,
ClkEna,
FrameStart,
FrameEna,
DataIn,
FrameStartOut,
FrameEnaOut,
DataOut
);
input Reset; // Global reset
input Clk; // Global clock
input ClkEna; // Clock Enable
input FrameStart; // Start of Frame
input FrameEna; // Active frame enable
input [7:0]DataIn;
output FrameStartOut;
output FrameEnaOut;
output [7:0]DataOut;
wire Reset;
wire Clk;
wire ClkEna;
wire FrameStart;
wire FrameEna;
wire [7:0]DataIn;
reg FrameStartOut;
reg FrameEnaOut;
reg [7:0]DataOut;
//
// Nodes
//
/*********************************************************************/
//
// DVB-S Reed-Solomon encoder
//
parameter BLOCK_SIZE = 204;
parameter CHECK_SYMBOLS = 16;
wire [7:0]GPol0, GPol1, GPol2, GPol3, GPol4, GPol5,
GPol6, GPol7, GPol8, GPol9, GPol10, GPol11,
GPol12, GPol13, GPol14, GPol15, GPol16;
// Galois polymonials
assign GPol0 = 1; // Root polynom - not used yet
assign GPol1 = 59;
assign GPol2 = 13;
assign GPol3 = 104;
assign GPol4 = 189;
assign GPol5 = 68;
assign GPol6 = 209;
assign GPol7 = 30;
assign GPol8 = 8;
assign GPol9 = 163;
assign GPol10 = 65;
assign GPol11 = 41;
assign GPol12 = 229;
assign GPol13 = 98;
assign GPol14 = 50;
assign GPol15 = 36;
assign GPol16 = 59;
// Polynom selection
function [7:0]GPol;
input [7:0]x;
begin
case (x)
0: GPol = GPol1;
1: GPol = GPol2;
2: GPol = GPol3;
3: GPol = GPol4;
4: GPol = GPol5;
5: GPol = GPol6;
6: GPol = GPol7;
7: GPol = GPol8;
8: GPol = GPol9;
9: GPol = GPol10;
10: GPol = GPol11;
11: GPol = GPol12;
12: GPol = GPol13;
13: GPol = GPol14;
14: GPol = GPol15;
15: GPol = GPol16;
endcase
end
endfunction
//
// Galois field general multiplier
//
// Use realy good synthesis tool with
// resource sharing optin enabled :-)
//
function [7:0]gfmul;
input [7:0]aa;
input [7:0]bb;
begin
gfmul[0] = (aa[0] & bb[0]) ^ (aa[7] & bb[1]) ^ (aa[6] & bb[2]) ^ (aa[5]
& bb[3]) ^
(aa[4] & bb[4]) ^ (aa[3] & bb[5]) ^ (aa[7] & bb[5]) ^ (aa[2]
& bb[6]) ^
(aa[6] & bb[6]) ^ (aa[7] & bb[6]) ^ (aa[1] & bb[7]) ^ (aa[5]
& bb[7]) ^
(aa[6] & bb[7]) ^ (aa[7] & bb[7]);
gfmul[1] = (aa[1] & bb[0]) ^ (aa[0] & bb[1]) ^ (aa[7] & bb[2]) ^ (aa[6]
& bb[3]) ^
(aa[5] & bb[4]) ^ (aa[4] & bb[5]) ^ (aa[3] & bb[6]) ^ (aa[7]
& bb[6]) ^
(aa[2] & bb[7]) ^ (aa[6] & bb[7]) ^ (aa[7] & bb[7]);
gfmul[2] = (aa[2] & bb[0]) ^ (aa[1] & bb[1]) ^ (aa[7] & bb[1]) ^ (aa[0]
& bb[2]) ^
(aa[6] & bb[2]) ^ (aa[5] & bb[3]) ^ (aa[7] & bb[3]) ^ (aa[4]
& bb[4]) ^
(aa[6] & bb[4]) ^ (aa[3] & bb[5]) ^ (aa[5] & bb[5]) ^ (aa[7]
& bb[5]) ^
(aa[2] & bb[6]) ^ (aa[4] & bb[6]) ^ (aa[6] & bb[6]) ^ (aa[7]
& bb[6]) ^
(aa[1] & bb[7]) ^ (aa[3] & bb[7]) ^ (aa[5] & bb[7]) ^ (aa[6]
& bb[7]);
gfmul[3] = (aa[3] & bb[0]) ^ (aa[2] & bb[1]) ^ (aa[7] & bb[1]) ^ (aa[1]
& bb[2]) ^
(aa[6] & bb[2]) ^ (aa[7] & bb[2]) ^ (aa[0] & bb[3]) ^ (aa[5]
& bb[3]) ^
(aa[6] & bb[3]) ^ (aa[4] & bb[4]) ^ (aa[5] & bb[4]) ^ (aa[7]
& bb[4]) ^
(aa[3] & bb[5]) ^ (aa[4] & bb[5]) ^ (aa[6] & bb[5]) ^ (aa[7]
& bb[5]) ^
(aa[2] & bb[6]) ^ (aa[3] & bb[6]) ^ (aa[5] & bb[6]) ^ (aa[6]
& bb[6]) ^
(aa[1] & bb[7]) ^ (aa[2] & bb[7]) ^ (aa[4] & bb[7]) ^ (aa[5]
& bb[7]);
gfmul[4] = (aa[4] & bb[0]) ^ (aa[3] & bb[1]) ^ (aa[7] & bb[1]) ^ (aa[2]
& bb[2]) ^
(aa[6] & bb[2]) ^ (aa[7] & bb[2]) ^ (aa[1] & bb[3]) ^ (aa[5]
& bb[3]) ^
(aa[6] & bb[3]) ^ (aa[7] & bb[3]) ^ (aa[0] & bb[4]) ^ (aa[4]
& bb[4]) ^
(aa[5] & bb[4]) ^ (aa[6] & bb[4]) ^ (aa[3] & bb[5]) ^ (aa[4]
& bb[5]) ^
(aa[5] & bb[5]) ^ (aa[2] & bb[6]) ^ (aa[3] & bb[6]) ^ (aa[4]
& bb[6]) ^
(aa[1] & bb[7]) ^ (aa[2] & bb[7]) ^ (aa[3] & bb[7]) ^ (aa[7]
& bb[7]);
gfmul[5] = (aa[5] & bb[0]) ^ (aa[4] & bb[1]) ^ (aa[3] & bb[2]) ^ (aa[7]
& bb[2]) ^
(aa[2] & bb[3]) ^ (aa[6] & bb[3]) ^ (aa[7] & bb[3]) ^ (aa[1]
& bb[4]) ^
(aa[5] & bb[4]) ^ (aa[6] & bb[4]) ^ (aa[7] & bb[4]) ^ (aa[0]
& bb[5]) ^
(aa[4] & bb[5]) ^ (aa[5] & bb[5]) ^ (aa[6] & bb[5]) ^ (aa[3]
& bb[6]) ^
(aa[4] & bb[6]) ^ (aa[5] & bb[6]) ^ (aa[2] & bb[7]) ^ (aa[3]
& bb[7]) ^
(aa[4] & bb[7]);
gfmul[6] = (aa[6] & bb[0]) ^ (aa[5] & bb[1]) ^ (aa[4] & bb[2]) ^ (aa[3]
& bb[3]) ^
(aa[7] & bb[3]) ^ (aa[2] & bb[4]) ^ (aa[6] & bb[4]) ^ (aa[7]
& bb[4]) ^
(aa[1] & bb[5]) ^ (aa[5] & bb[5]) ^ (aa[6] & bb[5]) ^ (aa[7]
& bb[5]) ^
(aa[0] & bb[6]) ^ (aa[4] & bb[6]) ^ (aa[5] & bb[6]) ^ (aa[6]
& bb[6]) ^
(aa[3] & bb[7]) ^ (aa[4] & bb[7]) ^ (aa[5] & bb[7]);
gfmul[7] = (aa[7] & bb[0]) ^ (aa[6] & bb[1]) ^ (aa[5] & bb[2]) ^ (aa[4]
& bb[3]) ^
(aa[3] & bb[4]) ^ (aa[7] & bb[4]) ^ (aa[2] & bb[5]) ^ (aa[6]
& bb[5]) ^
(aa[7] & bb[5]) ^ (aa[1] & bb[6]) ^ (aa[5] & bb[6]) ^ (aa[6]
& bb[6]) ^
(aa[7] & bb[6]) ^ (aa[0] & bb[7]) ^ (aa[4] & bb[7]) ^ (aa[5]
& bb[7]) ^
(aa[6] & bb[7]);
end
endfunction
reg [7:0]Cnt; // Data Counter
reg [7:0]Regs[0:CHECK_SYMBOLS - 1]; // CRC Registers
reg Shift; // Data / CRC
wire [7:0]FeedBack; // Feedback
assign FeedBack = (Shift | FrameStart) ? DataIn ^ Regs[0] : 0;
// Count down block counter
always @(posedge Clk or posedge Reset)
begin
if (Reset)
begin
Cnt <= BLOCK_SIZE;
Shift <= 1;
end
else if (FrameStart)
begin
Cnt <= BLOCK_SIZE;
Shift <= 1;
end
else if (ClkEna)
begin
if (Cnt > 0)
Cnt <= Cnt - 1;
Shift <= Cnt > (CHECK_SYMBOLS + 2);
end
end
integer i;
// Registers and output data
always @(posedge Clk or posedge Reset)
begin
if (Reset)
begin
for(i = 0; i < CHECK_SYMBOLS; i = i + 1)
Regs[i] <= 0;
DataOut <= 0;
FrameStartOut <= 0;
FrameEnaOut <= 0;
end
else if (ClkEna)
begin
for(i = 0; i < CHECK_SYMBOLS - 1; i = i + 1)
Regs[i] <= Regs[i + 1] ^ gfmul(FeedBack, GPol(i));
Regs[CHECK_SYMBOLS - 1] <= gfmul(FeedBack, GPol(CHECK_SYMBOLS - 1));
DataOut <= (Shift | FrameStart) ? DataIn : Regs[0];
FrameStartOut <= FrameStart;
FrameEnaOut <= FrameEna;
end
end
endmodule
Article: 30286Austin Franklin wrote: > > Could someone enlighten me ? Is PCI-X just a clock speed uprated 66MHz PCI > > or are there any fundamental differences ? As far as I can see the only > > significant change is to allow split cycles. > > It's basically registered. More clock cycles for control, but given it can > support much higher clock rates, it's faster. Just after I posted my question I went & looked at your, Xilinx's, PCI-X data & deduced the reg2reg nature from the fact that the setup/hold timings are the standard ones for a virtex => all signals have to be registered before being used. Are there any other eletrical/functional differences ? Can we use the PCI-66 SelectIO ?Article: 30287
Simon Bacon wrote: > > OTOH, you may be claiming that the band of brothers who work on > FPGA designs are a tempermental bunch... No Simon you must not give the guy the wrong impression. We are of course calm, rational, gentle citizens of the digital world who help people across the road and are very kind to all fellow creatures of this lovely planet. We only become temperamental, irrational, demented scary monster types when faced with: o The imminent arrival of the design which we have been working on for months, o The cancellation of the project ditto, o The sudden non-availability of parts we have designed into ditto, o The appearence on this NG of opinions contrary to our most deeply held beliefs, ... o Yet another MAP/PAR bug.Article: 30288
Hi, I already disabled the DCHP Media Sense as written in Quartus Readme, but I still can't start Quartus, as the software doesn't detect the License Type and the HostID. Is it possible to get Quartus running on W2K system, where the Network card isn't used for a TCP/IP connection at all? TIA, CarlhermannArticle: 30289
Hi, First of all, excuse my limited english (and spelling mistakes). Reinoud wrote: > > Hi Jean-Michel, > > > I've wanted to start playing with FPGAs for a long time, but never got > > to start a real project with these due to home-computers limitations : > > none of my computer have the resources/hard disk space to get win9x > > running (ie I do not want to dedicate one of my higher grade computers > > to fpga development by installing win9x on it as I would have no other > > use for that OS). > > Well, you can run Xilinx back-end tools under WINE on Linux, if that is > what you are running, see http://www.polybus.com/xilinx_on_linux.html. WINE is in alpha state. It takes quite a lot of work to make a WinX program to behave (and even start) properly. I whouln't try that alternative (unless you have the time). If I were you, I whould try the dual boot alternative Reinoud suggests. If you got WebPACK working propperly over WINE, please tell me how you did it (garana@sinectis.com.ar or gonzaloa@sinectis.com.ar). > Xilinx has fairly hefty tools, WEBPack, available for free (somewhere at > http://www.xilinx.com/). I'm not sure the HDL synthesis works under WINE; > you could try hacking Icarus Verilog (http://icarus.com/eda/verilog/) to > target Virtex/Spartan-II for synthesis instead (it targets XC4k now). I did use WEBPack. It's excellent (as deep as I used it), free and available. Lately Xilinx seems to have some problems on its web site: I tried lately to download the Device Programmer Tools -a "module" of WebPACK ISE-). You should try it. You may get it on following the links: www.xilinx.com -> products -> Design Tools -> Free WebPOWERED Software. > > Somehow, getting a bigger disk (that's cheap nowadays), installing > Windows, and dual-booting to run WEBPack seems less work (even though it > s*cks)... > > > 1/ how does one get from a VHDL document to a "binary" (or whatever > > it is called in the FPGA world) file ? With the altera tool, one had > > part AHDL subroutines, part graphical interface for connecting these > > subroutines tougether, click on "build" and there you get your compiled > > file. Is there anything similar in the open-source world ? I seem to > > understand alliance will compile early Xilinx 4000 series EPLD, but I > > don't even know if these are still available. > > I don't really follow you here. You need a HDL synthesis tool to turn > your HDL xource into a netlist, and a place&route back-end to map it onto > the physical device. The final device programming data goes into some > bitstream file, your 'binary' if you like. > > Note that Altera's (free) tools also run on Windows. Alliance runs on > Solaris (SPARC) and HP-UX, last time I checked; no synthesis front-ends > included. As far as I know, you may program you design in VHDL and/or Verilog (that depends on the software tool), and then get the misterious "bit stream". You need to get that to a serial EEPROM. That bit stream gets loaded into the FPGA when power is supplied. > > > 2/ once I get by "binary" file, I used to send it to the EPLD via the > > JTAG port. I suppose I could program an HC11 to get the files sent from > > the PC through RS232 and send whatever signal is required by the JTAG > > protocol > > Xilinx FPGAs support a dead simple serial protocol. I'll post a download > utility for Linux tomorrow or so. Is there a download utility for Linux?. Please, I would need that!! > > Have fun, > > - Reinoud > > ---- > > Spam goes to wanabe, mail to wanadoo. Hope it helps, Gonzalo AranaArticle: 30290
Hi, Is there a PCI interface (master & target) coded in VHDL? That would be of great help. Thank you very much, GonzaloArticle: 30291
Can anyone tell me if the Xilinx Foundation 1.5 Software can take Verilog and generate printable schematics?Article: 30292
All,
I'm using synopsys with the Xilinx Foundation tools (3.3i I believe) and I'm
seeing some strange behavior with a particular construct...
I include IEEE.std_logic_unsigned.all so that I can add std_logic_vectors.
When I do something like:
SIGNAL
A, B : std_logic_vector(7 downto 0);
SIGNAL C : std_logic_vector(8 downto 0);
and then later in the architecture in a registered process:
C <= ('0' & A) + ('0' & B);
I include the '0' here on vectors A and B so that the types on the LHS and
RHS are the same (9 bit vectors), but the synthesis tool appears to trim off
the top bit of the C vector... Thus, if I add a couple numbers like
10000001 and 10000001 I should get 100000010 (which is 9 bits), but I only
get 00000010 (which is 8 bits)... I lose the MSb. It turns out that on the
very next clock cycle I subtract a constant bias (decimal 127) from C so I
never actually use the 8th bit of the C vector for any output. I could code
it differently to take the bias out of either vector A or B before I add
them, but it appears the synthesis tool isn't actually giving me what I
asked for... Any ideas?
thx
Matt
--
Matt Billenstein
mbillens (at) one (dot) net
http://w3.one.net/~mbillens/
Article: 30293Hi, I'am currently developing an IDE controller card with PCI interface to the host. I'am aware of how does a controller reads/writes to the disk. Does any body knows what does the host write/read to/from an IDE controller? Does the controller have to present a bank of registers? How many? Where? (IO port). What does each of those register mean? Thanks, GonzaloArticle: 30294
Hallo sir. How to use the distributed ram in VERTEX_E for instantiation of memoryArticle: 30295
Hi. I have read xilinx application note xapp258 and I have the following question: Regarding the independent read/write clocks; I understand the idea of the gray counter that since only 1 bit change at a time, synchronizing the counter value while passing from 1 clock domain to another the value of the counter will be either the old or the new one. I fear from the following scenario : wclk and rclk are very fast independent clocks. since the path between 2 asynchronous clock is not constrained and P&R tool is cruel, the following might occur path between bit i of counter to its synchronizer is: epsilon; path between bit j of counter to its synchronizer is: epsilon + Tcyc; under these condition the synchronizer can sample false value of the gray counter and thus give false full or empty flag. Is it possible ? Can it be avoided ? ThankX. ----- Posted via NewsOne.Net: Free (anonymous) Usenet News via the Web ----- http://newsone.net/ -- Free reading and anonymous posting to 60,000+ groups NewsOne.Net prohibits users from posting spam. If this or other posts made through NewsOne.Net violate posting guidelines, email abuse@newsone.netArticle: 30296
> >If a CPLD is specified as a 10ns device it indicates the total (minimum) > >time from an input to output pin. Example: If you want to build a high freq. > >oscillator a CPLD would be the choice(if you are looking at PLDs). Using a > >10ns device you can theoretically clock up to 100MHz (one of my friends did > >this a few weeks ago) > > I don't think anyone should build an oscillator from a CPLD or FPGA. > I live in a technologically starved part of the world. I can only get 5V compatible oscillators (I need 3.3V devices). Even RS components are quoting me 50 week lead times on some components. So to bypass at least this osc. problem we started to look if there was an alternative. It turned out that using a few spare gates and 3 pins on the CPLD (+ a cheap crystal/cer. resonator, 2 resistos and a cap.) we could synthesize a decent oscillator. The CPLD on my design is mainly used as a PPI, leaving more than half the gates unused. So the designer had another idea. He found that the 100MHz design was very stable, but we only needed a 20MHz to 30MHz clock. Implementing a simple devide-by-4 logic he derived a more stable 25MHz clock. This might sound like a waste of time but where I live an oscillator costs about the same an Altera 3064 plus crystal and related components (plus inductor). We now have a very simple oscillator design with jumper settable clock speed giving us a range of 12.5MHz, 25MHz and 50MHz. We are using it to drive the Altera NIOS CPU which can operate upto 50MHz.Article: 30297
Hi. I have read xilinx application note xapp258 and I have the following question: Regarding the independent read/write clocks; I understand the idea of the gray counter that since only 1 bit change at a time, synchronizing the counter value while passing from 1 clock domain to another the value of the counter will be either the old or the new one. I fear from the following scenario : wclk and rclk are very fast independent clocks. since the path between 2 asynchronous clock is not constrained and P&R tool is cruel, the following might occur path between bit i of counter to its synchronizer is: epsilon; path between bit j of counter to its synchronizer is: epsilon + Tcyc; under these condition the synchronizer can sample false value of the gray counter and thus give false full or empty flag. Is it possible ? Can it be avoided ? ThankX. ----- Posted via NewsOne.Net: Free (anonymous) Usenet News via the Web ----- http://newsone.net/ -- Free reading and anonymous posting to 60,000+ groups NewsOne.Net prohibits users from posting spam. If this or other posts made through NewsOne.Net violate posting guidelines, email abuse@newsone.netArticle: 30298
yorams@hywire.com writes: > Hi. > I have read xilinx application note xapp258 and I have the following > question: > > Regarding the independent read/write clocks; > > I understand the idea of the gray counter that since only 1 bit change > at a time, > synchronizing the counter value while passing from 1 clock domain to another > the value of the counter will be either the old or the new one. > > I fear from the following scenario : > wclk and rclk are very fast independent clocks. > since the path between 2 asynchronous clock is not constrained and P&R > tool is cruel, > the following might occur > > path between bit i of counter to its synchronizer is: epsilon; > path between bit j of counter to its synchronizer is: epsilon + Tcyc; > > under these condition the synchronizer can sample false value of the gray > counter and thus give false full or empty flag. > > > Is it possible ? > Can it be avoided ? I assume you're working with Xilinx. You can constrain the delay of the individual paths, using the FROM-TO constraint. Fore more info, see the documentation. Homann -- Magnus Homann, M.Sc. CS & E d0asta@dtek.chalmers.seArticle: 30299
Hello, has someone expierience with generating (pseudo) random numbers in FPGA's (XC4000XLA series) ? My first idea was to use maximal length sequences (shift registers having maximum possible period for an r-stage shift register) Is there another source of randomness of the FPGA istself which can be used ? thanks Joerg
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z