Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Is there a way to start Foundation timing simulator without user
interaction? I'd like to start a simulation with netlist and script
file. Simulation data is saved by commands in the script file. After
simulation I'd like the simulator application to quit automatically.
From my point of view this should be done by a script command ("exit"
just exits the script but not the simulator) or by a command line
parameter.
I did't find a documentation to the command parameters of "simul.exe".
Thank you,
Michael
Article: 30501
I'm wondering if thereis somebody kind enough to help me with this ABEL
syntax. I want to know the syntax so the output goes to 'High impedance' when the
OE pin = 0
here is the truth table or test vector
Thank you in advance
INPUT OUTPUT
_________________________________________________________________________
OE a15 a2 a1 a0 [D7,D6,D5,D4,D3,D2,D1,D0]
0 X X X X = High Impedance
1 0 0 0 0 = $86
1 0 0 0 1 = $06
1 0 0 1 0 = $97
1 0 0 1 1 = $A0
1 0 1 0 0 = $3e
1 0 1 0 1 = $0
1 0 1 1 0 = $0
1 0 1 1 1 = $0
1 1 0 0 0 = $0
1 1 0 0 1 = $0
1 1 0 1 0 = $0
1 1 0 1 1 = $0
1 1 1 0 0 = $0
1 1 1 0 1 = $0
1 1 1 1 0 = $0
1 1 1 1 1 = $0
--
Sent through GMX FreeMail - http://www.gmx.net
--
Posted from mx0.gmx.de [213.165.64.100]
via Mailgate.ORG Server - http://www.Mailgate.ORG
Article: 30502winmaster Winmaster schrieb: > > I'm wondering if thereis somebody kind enough to help me with this ABEL > syntax. I want to know the syntax so the output goes to 'High impedance' when the > OE pin = 0 > > here is the truth table or test vector > declarations data=[d7..d0]; equations data.oe=!oe; or: d7.oe=!oe; d6.oe=!oe d5.oe=!oe ... greetings, Bertram > > INPUT OUTPUT > _________________________________________________________________________ > OE a15 a2 a1 a0 [D7,D6,D5,D4,D3,D2,D1,D0] > > 0 X X X X = High Impedance > > 1 0 0 0 0 = $86 > 1 0 0 0 1 = $06 [...] -- Bertram Geiger, bgeiger@aon.at HTL Bulme Graz-Goesting - AUSTRIAArticle: 30503
Normally, the inferred flip-flops will initialize to zero. For an inferred flip-flop, you can make it initialize to '1' by putting an explicit global reset net in the design and force the signal to a '1' when global reset is '1'. Connect that global reset net to the ROC component I mentioned previously. If you instantiate flip-flop primitives from the Unisim library, there is an INIT generic on the element to initialize it as set or reset for simulation. You also have to add an INIT= attribute to get that to pass through to the bitstream if the init value is not the default for that component. Kolja Sulimma wrote: > > I have an additional questions to this: > > If I have no explicit reset signal in my design, how do I specify the reset value of a > DFF? > > Thanks, > Kolja > > > > The power on reset happens whether you specify a global reset or not, and > > > regardless of whether or not your logic has async resets on it or not. For > > > synthesis, you needn't do a thing if you don't have a reset pin on your design. > > > If you want to simulate it however, then use the ROC component in the unisim > > > library. It gets connected to your Global reset net. You can leave it in there > > > if you want. Synthesis will put the ROC in your design as a black box, and the > > > xilinx software will ignore it. > > > > > > yuryws@banet.net wrote: > > > > > > > > Would like to implement Power-On-Reset. Use no external Reset pin. > > > > Asynchronous RST is used throughout the design on all flops/memories. > > > > > > > > What is the procedure for tying GSR to RST during synthesis (FPGA > > > > Express user)? > > > > > > > > Thnx. > > > > > > -- > > > -Ray Andraka, P.E. > > > President, the Andraka Consulting Group, Inc. > > > 401/884-7930 Fax 401/884-7950 > > > email ray@andraka.com > > > http://www.andraka.com -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.comArticle: 30504
Bertram Geiger wrote: > Do you have the comlete ABEL reference and design manuals and als looked > at them ? I went through the whole tutorial, but I'm pretty sure I missed something in the manuals. After all I'm only beginnning to work with it. > When yes, what syntax question ist still unsolved ? > (i cannot say anything about timing issues) 1) Busses are interesting. In the SchematicEntry it's called Q[7:0], in ABEL it's [Q7..Q0], in the *.abv test vectors it's Q_7_, Q_6_, Q_5_, Q_4_, Q_3_, Q_2_, Q_1_, Q_0_ (like in the Post-Fit Pinouts). This works for FunctionalSimulation but not for TimingSimulation. WARNING 26447: In reading command, signal Q_7_ does not exist; signal in command is ignored. 2) In Fuctional Simulation I couldn't look at some internal nodes that I need for debugging. Attribute 'keep=yes' in the Schematic doesn't seem to help with this. 3) How do I create a delayed clock signal in ABEL. Hints concerning those 3 questions would be greatly appreciated. -- many thanx Richard KnispelArticle: 30505
Greetings, Our group project is presently working on an ATMEL/Xilinx FGPA-based voice synthesis system based on Klatt Synthesis software. A requirement is to convert a bit-serial result from LSB order to MSB order for input to a Delta-Sigma DAC. Because the selected target is a XC4005 device, resource utilization is critical. In order to meet our resource budget and facilitate a wide option based, I am asking anyone with experience with this task for their input. I have found the Xilinx FD-based Shift Register, however, the LSB-to-MSB functionality is a subset of this register's abilities and will break the resource budget. Thank you in advance for your advice. I look forward to your responses. Kind Regards, Michael Wirtzfeld.Article: 30506
How can I change the contents of a block ROM or select ROM in the bitstream without recompiling the code. I'd like to embed a small micro + program memory in an FPGA and I don't want to have to go through the compile/place/route process just to change some memory initializations. TIA, UrbArticle: 30507
If you generate the ROM as a black box, then perhaps you could simply re-generate it, and use a previous version as a guide for the new placement. You'd still be running through a significant part of the process, but it should be very fast given that the design would be virtually unchanged. From a Xilinx perspective, that would mean running Coregen to create a new EDN file, which will be converted to an NGO and merged by ngdbuild. Then, to specify the previous NCD as a guide for par. I haven't actually tried this, it's just a suggestion. Cheers, Jamie "Paul Urbanus" <urb@ti.com> wrote in message news:3AD4B629.373F5EB9@ti.com... > How can I change the contents of a block ROM or select ROM in the bitstream > without recompiling the code. > > I'd like to embed a small micro + program memory in an FPGA and I don't want to > have to go through the compile/place/route process just to change some memory > initializations. > > TIA, > > UrbArticle: 30508
I've heard mentioned that the 3.3 version of JTAG programmer will, at long last, support Virtex readback through the JTAG port. Does anyone know if this is correct ? Have they tried it ? Unfortunately the WebPack version seems stuck at 3.2 so I can't download & try it out myself.Article: 30509
Use the dual port CLB RAM capability and 4 bit counters to make a variable length delay queue. After the msb of the LSB first sequence goes in, the read delay tap is advanced by 2 on each clock. One Dual port CLB ram + 2 4 bit counters will handle up to 8 bit data (5 CLBs). Bit into RAM: 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 Bit from RAM 7 6 5 4 3 2 1 0 7 6 5 ... write address: 0 1 2 3 4 5 6 7 8 9 A B C D E F read address: 7 6 5 4 3 2 1 0 F E D ... M Wirtzfeld wrote: > > Greetings, > > Our group project is presently working on an ATMEL/Xilinx FGPA-based voice > synthesis system based on Klatt Synthesis software. A requirement is to > convert a bit-serial result from LSB order to MSB order for input to a > Delta-Sigma DAC. > > Because the selected target is a XC4005 device, resource utilization is > critical. In order to meet our resource budget and facilitate a wide option > based, I am asking anyone with experience with this task for their input. I > have found the Xilinx FD-based Shift Register, however, the LSB-to-MSB > functionality is a subset of this register's abilities and will break the > resource budget. > > Thank you in advance for your advice. I look forward to your responses. > > Kind Regards, > > Michael Wirtzfeld. -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.comArticle: 30510
Dear Betram, Thank you very much, you are very kind. Best regards Kaman -- Sent through GMX FreeMail - http://www.gmx.net -- Posted from mx0.gmx.de [213.165.64.100] via Mailgate.ORG Server - http://www.Mailgate.ORGArticle: 30511
This is a multi-part message in MIME format.
--------------282C7FD0E3A15D26D47E3954
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit
Some real code for you all to look at...
Cyber_Spook...
--------------282C7FD0E3A15D26D47E3954
Content-Type: text/plain; charset=us-ascii;
name="parmult.c"
Content-Transfer-Encoding: 7bit
Content-Disposition: inline;
filename="parmult.c"
/****************************************************************
* *
* Copyright 1991-2001 Celoxica Ltd. *
* All Rights Reserved *
* *
* This is "Unpublished Proprietary Source Code" of Celoxica *
* Ltd ("Celoxica"). The contents of this file may not *
* be disclosed to third parties not covered by a Celoxica *
* NDA (Non-Disclosure Agreement) or a Celoxica End User Licence *
* Agreement or other agreement. *
* *
* In addition, the source code of this file may not be *
* copied or duplicated in any form without the prior written *
* authorization of Celoxica. *
* *
* This code is protected by English and International *
* copyright laws. All use of this code is subject to the *
* End User License Agreement, Non-Disclosure Agreement, *
* or other agreement in effect with Celoxica. If a *
* licence document or agreement is not included with this *
* source code please contact Celoxica immediately for a copy of *
* the applicable licence agreement. *
* *
* Any other use of this code other than as expressly agreed *
* to by Celoxica including decompilation, *
* disassembly, or reverse engineering is unauthorised. *
* *
* Rights of confidence, trademark rights, and other *
* intellectual property rights reserved under the laws of *
* England, the United States, and the International *
* Community. *
* *
* World Wide Headquarters: *
* Celoxica Limited *
* 20 Park Gate *
* Milton Park *
* Abingdon *
* Oxfordshire *
* United Kingdom *
* OX14 4SH *
* Tel: +44 1235 863656 *
* Fax: +44 1235 863648 *
* *
* US Headquarters: *
* Celoxica Inc *
* 900 East Hamilton Ave. *
* Suite 150 *
* Campbell, CA 95008 *
* Tel: 1-408-626-9070 *
* Fax: 1-408-626-9079 *
* *
* Email : support@celoxica.com *
* *
*****************************************************************
* *
* Project : Handel-C *
* Date : 28 JUL 1997 *
* File : parmult.c *
* Author : Matthew Aubury (MA) *
* Contributors: *
* Matthew Bowen (MB) *
* Sandra Gadanho (SG) *
* *
* Description: *
* Pipelined multiplier. *
* To test open the workspace file 'Example2.hw'. *
* *
* Date Version Author Reason for change *
* *
* 28 JUL 1997 1.00 MA Created *
* 05 OCT 1998 1.10 MB Removed assignment from chan *
* 28 FEB 2000 2.00 SG Updated for version 3.0 *
* *
****************************************************************/
/*
* Include Handel-C library header file
*/
#include "stdlib.h"
/*
* Clock
*/
set clock = external "Clock";
/*
* Data path width
*/
macro expr IntWidth = 16;
/*
* Function declarations
*/
void sendOps();
void recvResult();
void parMult();
/*
* Signals for communication with the multiplier
*/
signal unsigned leftOp;
signal unsigned rightOp;
signal unsigned result;
/*
* Operands used in multiplication
*/
#define NumOps 8
rom unsigned IntWidth leftOps[NumOps] = { 12, 1, 5, 19, 31, 26, 14, 0 };
rom unsigned IntWidth rightOps[NumOps] = { 30, 8, 17, 23, 11, 5, 24, 13 };
ram unsigned results[NumOps];
/*
* Index at end of array macro
*/
#define IndexAtArrayEnd(Index, ArrayLimit) \
select(exp2(width(Index)) == (ArrayLimit), !(Index), (Index) == (ArrayLimit))
/*
* Function main
*/
void main()
{
par
{
sendOps();
recvResult();
parMult();
}
}
/*
* Function sendOps
* Send operands to multiplication
*/
void sendOps()
{
unsigned i;
/*
* Put each of the operands into the multiplier
* on consecutive clock cycles
*/
i = 0;
do
{
par
{
leftOp = leftOps[i];
rightOp = rightOps[i];
i++;
}
} while (!IndexAtArrayEnd(i, NumOps));
}
/*
* Function recvResults
* Receive results
*/
void recvResult()
{
unsigned i;
unsigned value;
/*
* Throw away dummy results from the pipeline whilst it is primed
*/
seq (j = 0; j < IntWidth + 1; j++)
{
delay;
}
/*
* Get the actual results
*/
i = 0;
do
{
par
{
value = result;
results[i] = result;
i++;
}
} while (!IndexAtArrayEnd(i, NumOps));
}
/*
* Function parmult
* Pipelined multiplication
*/
void parMult()
{
unsigned xx[IntWidth];
unsigned yy[IntWidth];
unsigned rr[IntWidth];
while (1)
{
par
{
/*
* Read operands from channels
*/
xx[0] = leftOp;
yy[0] = rightOp;
rr[0] = xx[0][0] ? yy[0] : 0;
/*
* Replicator: generates the pipeline stages of
* the long multiplier, which are done in parallel.
*/
par (i = 1; i < IntWidth; i++)
{
xx[i] = xx[i - 1] >> 1;
yy[i] = yy[i - 1] << 1;
rr[i] = rr[i - 1] + (xx[i][0] ? yy[i] : 0);
}
/*
* Return result
*/
result = rr[IntWidth-1];
}
}
}
--------------282C7FD0E3A15D26D47E3954
Content-Type: text/plain; charset=us-ascii;
name="proc.c"
Content-Transfer-Encoding: 7bit
Content-Disposition: inline;
filename="proc.c"
/****************************************************************
* *
* Copyright 1991-2001 Celoxica Ltd. *
* All Rights Reserved *
* *
* This is "Unpublished Proprietary Source Code" of Celoxica *
* Ltd ("Celoxica"). The contents of this file may not *
* be disclosed to third parties not covered by a Celoxica *
* NDA (Non-Disclosure Agreement) or a Celoxica End User Licence *
* Agreement or other agreement. *
* *
* In addition, the source code of this file may not be *
* copied or duplicated in any form without the prior written *
* authorization of Celoxica. *
* *
* This code is protected by English and International *
* copyright laws. All use of this code is subject to the *
* End User License Agreement, Non-Disclosure Agreement, *
* or other agreement in effect with Celoxica. If a *
* licence document or agreement is not included with this *
* source code please contact Celoxica immediately for a copy of *
* the applicable licence agreement. *
* *
* Any other use of this code other than as expressly agreed *
* to by Celoxica including decompilation, *
* disassembly, or reverse engineering is unauthorised. *
* *
* Rights of confidence, trademark rights, and other *
* intellectual property rights reserved under the laws of *
* England, the United States, and the International *
* Community. *
* *
* World Wide Headquarters: *
* Celoxica Limited *
* 20 Park Gate *
* Milton Park *
* Abingdon *
* Oxfordshire *
* United Kingdom *
* OX14 4SH *
* Tel: +44 1235 863656 *
* Fax: +44 1235 863648 *
* *
* US Headquarters: *
* Celoxica Inc *
* 900 East Hamilton Ave. *
* Suite 150 *
* Campbell, CA 95008 *
* Tel: 1-408-626-9070 *
* Fax: 1-408-626-9079 *
* *
* Email : support@celoxica.com *
* *
*****************************************************************
* *
* Project : Handel-C *
* Date : 12 JUN 1997 *
* File : proc.c *
* Author : Matthew Aubury (MA) *
* Contributors: *
* Sandra Gadanho (SG) *
* *
* Description: *
* Handel-C example program demonstrating simple processor. *
* To test open the workspace file 'Example5.hw'. *
* *
* Date Version Author Reason for change *
* *
* 12 JUN 19 97 1.00 MA Created *
* 28 FEB 2000 2.00 SG Updated for version 3.0 *
* *
****************************************************************/
/*
* Clock
*/
set clock = external "P1";
/*
* Processor input and output channels
*/
chan unsigned input;
chan unsigned output;
/*
* Parameterisation
*/
#define DW 32 /* Data width */
#define RAM_AW 4 /* Width of RAM address bus (data) */
#define ROM_AW 5 /* Width of ROM address bus (code) */
#define OPCW 4 /* Op-code width */
#define OPRW 5 /* Operand width */
/*
* The opcodes
*/
#define HALT 0
#define LOAD 1
#define LOADI 2
#define STORE 3
#define ADD 4
#define SUB 5
#define JUMP 6
#define JUMPNZ 7
#define INPUT 8
#define OUTPUT 9
/*
* The assembler macro
*/
#define _asm_(opc, opr) (opc + (opr << OPCW))
/*
* ROM program data
*/
rom unsigned int program[] =
{
_asm_(LOADI, 0), /* 0 */ /* Get a zero */
_asm_(STORE, 0), /* 1 */ /* Store this */
_asm_(LOADI, 1), /* 0 */ /* Get a one */
_asm_(STORE, 1), /* 1 */ /* Store this */
_asm_(STORE, 3), /* 2 */ /* ... */
_asm_(INPUT, 0), /* 3 */ /* Read value from input */
_asm_(STORE, 2), /* 4 */ /* Store this */
_asm_(LOAD, 1), /* 5 */ /* Loop entry point */
_asm_(ADD, 0), /* 6 */ /* Make a fib number */
_asm_(STORE, 0), /* 7 */ /* Store it */
_asm_(ADD, 1), /* 8 */ /* Make a fib number */
_asm_(STORE, 1), /* 9 */ /* Store it */
_asm_(LOAD, 2), /* a */ /* Decrement counter */
_asm_(SUB, 3), /* b */ /* ... */
_asm_(JUMPNZ, 6), /* c */ /* Repeat if not zero */
_asm_(LOAD, 1), /* d */ /* Load the final answer */
_asm_(OUTPUT, 0), /* e */ /* Output it */
_asm_(HALT, 0) /* f */ /* Exit */
};
/*
* Prototypes
*/
void processor();
/*
* Main program
*/
void main (void)
{
unsigned value;
chanout result;
/*
* Run the processor: request the (1+2*5)=11th Fibonnaci
* number. This is returned and stored in "value", and
* should be 89.
*/
par
{
processor();
input ! 5;
{
output ? value;
result ! value;
}
}
}
/*
* The processor
*/
void processor()
{
/*
* RAM for processor
*/
ram unsigned int DW data[1 << RAM_AW];
/*
* Processor registers
*/
unsigned int ROM_AW pc; /* Program counter */
unsigned int (OPCW + OPRW) ir; /* Instruction register */
unsigned int DW x; /* Accumulator */
/*
* Macros to extract opcode and operand fields
*/
macro expr opcode = (ir <- OPCW);
macro expr operand = (ir \\ OPCW);
pc = 0;
/*
* Processor loop
*/
do
{
/*
* Fetch
*/
par
{
ir = program[pc];
pc++;
}
/*
* Decode and execute
*/
switch (opcode)
{
case HALT : break;
case LOAD : x = data[operand <- RAM_AW]; break;
case LOADI : x = 0 @ operand; break;
case STORE : data[operand <- RAM_AW] = x; break;
case ADD : x += data[operand <- RAM_AW]; break;
case SUB : x -= data[operand <- RAM_AW]; break;
case JUMP : pc = operand <- ROM_AW; break;
case JUMPNZ : if (x != 0) pc = operand <- ROM_AW; break;
case INPUT : input ? x; break;
case OUTPUT : output ! x; break;
default : while(1) delay; /* unknown opcode */
}
} while (opcode != HALT);
}
--------------282C7FD0E3A15D26D47E3954--
Article: 30512
All,
ERROR:NgdBuild:432 - logical block 'U1/U7/U1' with type 'FD16RE' is
unexpanded
ERROR:NgdBuild:432 - logical block 'U1/U7/U2' with type 'FD16RE' is
unexpanded
ERROR:NgdBuild:432 - logical block 'U1/U7/U3' with type 'FD16RE' is
unexpanded
ERROR:NgdBuild:432 - logical block 'U1/U7/U4' with type 'FD16RE' is
unexpanded
ERROR:NgdBuild:432 - logical block 'U1/U1/U1' with type 'FD16RE' is
unexpanded
I'm getting these types of errors when I try to implement my design in
Xilinx Foundation 3.1i. These primitives are instantiated in edif netlists
which were provided to me. This component is in the Virtex library, so I
don't understand why the tool isn't finding it...
The declaration in the edn file looks like:
(instance U1
(viewRef net
(cellRef FD16RE
(libraryRef VIRTEX)
)
)
)
thx
matt
--
Matt Billenstein
mbillens (at) one (dot) net
http://w3.one.net/~mbillens/
Article: 30513You might also take a look at the JBits package from Xilinx. It's a java API that operates on bistreams: you write yourelf a little program that inserts your new code in your old bitstream. The documentation makes it sound easy, but I haven't tried it myself yet. HTH, -Kent "Jamie Sanderson" <jamie@nortelnetworks.com> writes: > If you generate the ROM as a black box, then perhaps you could simply > re-generate it, and use a previous version as a guide for the new placement. > You'd still be running through a significant part of the process, but it > should be very fast given that the design would be virtually unchanged. > <snip> > "Paul Urbanus" <urb@ti.com> wrote in message > news:3AD4B629.373F5EB9@ti.com... > > How can I change the contents of a block ROM or select ROM in the > bitstream > > without recompiling the code. > > > > I'd like to embed a small micro + program memory in an FPGA and I don't > want to > > have to go through the compile/place/route process just to change some > memory > > initializations.Article: 30514
Hi, I tried to build my *.srec by the Software Build button in QuartusII, but I always get the message, that the build was unsuccessful (with 0 errrors and 0 warnings). The same *.c code compiles in the BASH windows by using nios build (nb). I think I have to adjust my software build settings, but I don't know, what's wrong. Well I have configured the NIOS32, GNU tools for NIOS and *.srec output. No special settings for assembler or linker include... TIA, Carlhermann SchlehausArticle: 30515
I had similar problem and contacted modelsim support. They replied today and said that this bug had been fixed in release 5.5a which is ready for download. I have not tried it yet. LS. "W.Turk" <kgut@dotuy.com> wrote in message news:ee70257.-1@WebX.sUN8CHnE... > Hi Gang: > Now ,i use Modelsim5.5.When i load or run a large design,it will > always close automatic. > Why?Article: 30516
I don't use the Quartus features,only the bash window. I have several versions of the nios-build script to automatically build a project, with all the required flags. I recommend using NIOS the command line way because one day you will have to get somebody to support the software and you don't want to supply Quartus II to all your developers as well. "C.Schlehaus" <carlhermann.schlehaus@t-online.de> wrote in message news:9b36e9$pin$00$1@news.t-online.com... > Hi, > I tried to build my *.srec by the Software Build button in QuartusII, > but I always get the message, that the build was unsuccessful (with > 0 errrors and 0 warnings). The same *.c code compiles in the BASH > windows by using nios build (nb). > I think I have to adjust my software build settings, but I don't > know, what's wrong. > Well I have configured the NIOS32, GNU tools for NIOS and *.srec > output. No special settings for assembler or linker include... > > TIA, Carlhermann Schlehaus > >Article: 30517
Richard Knispel ha scritto nel messaggio <9b27ro$7jpdq$1@ID-83499.news.dfncis.de>... >2) In Fuctional Simulation I couldn't look at some internal nodes that I need >for debugging. Attribute 'keep=yes' in the Schematic doesn't seem to help with >this. You have to give also the attribute 'Preserve' for those nets. LuigiArticle: 30518
Kolja Sulimma wrote:
>
> I have an additional questions to this:
>
> If I have no explicit reset signal in my design, how do I specify the reset value of a
> DFF?
>
> Thanks,
> Kolja
In Verilog, with Synplicity, you do it like this:
module ROCBUF (I, O); //synthesis syn_black_box
input I;
output O;
endmodule
module gsr_test(q_async_reset_ff, q_async_set_ff, i, clk, strippable_reset);
input i,clk,strippable_reset;
output q_async_reset_ff, q_async_set_ff;
reg q_async_reset_ff, q_async_set_ff;
wire internal_reset;
// expect the following to be stripped by MAP
ROCBUF u1 (.I(strippable_reset), .O(internal_reset));
always @ (posedge clk or posedge internal_reset) begin
if(internal_reset) begin
q_async_reset_ff <= 0;
q_async_set_ff <= 1;
end
else begin
q_async_reset_ff <= i;
q_async_set_ff <= i;
end
end
endmodule
Philip
Philip Freidin
Fliptronics
Article: 30519Hi, all. I am learning FPGA design. I got an example writen in verilog, but I dont know how to count the clock cycles of it? and How can I know its execution speed? how to specify the clock frequency in verilog?Article: 30520
So considering all that's been said, what a VHDLer to do? Is anyone else out there slightly worried about this whole thing? Maybe we should all accept the inevitable and take a course in programming?Article: 30521
Hello Mr. Schlehaus, the Software Mode in Quartus II V1.0 supports only ARM/MIPS however doesn't support NIOS yet. As far as I know that's planned for the next major Quartus release. Regards Wolfgang Loewer /_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/ El Camino - Your Programmable Logic Design House http://www.elca.de info@elca.de /_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/ C.Schlehaus <carlhermann.schlehaus@t-online.de> wrote in message news:9b36e9$pin$00$1@news.t-online.com... > Hi, > I tried to build my *.srec by the Software Build button in QuartusII, > but I always get the message, that the build was unsuccessful (with > 0 errrors and 0 warnings). The same *.c code compiles in the BASH > windows by using nios build (nb). > I think I have to adjust my software build settings, but I don't > know, what's wrong. > Well I have configured the NIOS32, GNU tools for NIOS and *.srec > output. No special settings for assembler or linker include... > > TIA, Carlhermann Schlehaus > >Article: 30522
The free E+MAX license for MAX+plus II supports both VHDL and Verilog synthesis. You could then do a gate level simulation with the built in simulator. Regards Wolfgang Kristian Rye Vennesland <kristirv@stud.iet.hist.no> wrote in message news:3AD2BB86.2CC4BF74@stud.iet.hist.no... > Hi Soren, > > I would recommend an Altera FPGA, preferrably a MAX. They are easily > programmed trough a cable, which you can make yourself, > and the development software is free and easy > to use. I don't think the free version supports VHDL though. > > Best of luck, > > Kristian Rye Vennesland > > > -- > ----------------------------------- > > Kristian Rye Vennesland > > E-mail : Kristirv@stud.iet.hist.no > Cell.phone : +47 97 03 14 94 > > Mail Address: > > Kristian Rye Vennesland > Nonnegata 2B > 7014 Trondheim > N-7014 > NORWAY > > ----------------------------------- > >Article: 30523
Hi, dear I'm a novice in Xilinx Vertex-e device. I'd like to know how to use clock generator in Vertex-e? In XC4000XL, I could use OSC4 module in library in order to generate clock inside the device. I looked through the data book, but I could not find out the usage of clock generator. I only could find about CLKDLL, but I think CLKIN signal should be necessary to generate clock with CLKDLL. Is it right? I hope your answer. ThanksArticle: 30524
I am trying to duplicate an existing chip using VHDL. My target platform is a Xilinx Coldfire CPLD, but the design just doesn't want to fit no matter how I tweak it. It consists of: Two 16-bit down counters One 8-bit serial I/O register Two 8-bit tristateable I/O ports One interrupt register Some handshaking logic The actual chip's design includes a Time-Of-Day clock in BCD format, but I haven't put that in yet. Is it realistic to expect all of this to fit in a CPLD, or should I change my target to an FPGA? -- ::::: Dave Ross / Dr. Watson "Yesterday's technology :: === watson@enteract.com today...for a better :: === tomorrow!" ::::: http://www.enteract.com/~watson
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z