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> Software Pundits Inc. is a leading > provider of unique and innovative technology solutions for the top software > companies in the US. The likes of CISCO, Lucent, Alcatel, Bay Networks, > 3Com, Ascend, Nortel and Seimens. Hum. I thought those were all top hardware companies...Article: 30126
Christian, give us numbers. How fast do you need to run? And what is the speed-grade of your 40150? Peter Alfke, Xilinx Applications Christian Martin wrote: > Hello All, > > I have a timing problem with a 41-bit accumulator in a XC40150XV > device. Due to the long carry path in the accu, I can not reach the desired > frequency. Acually I use the accu from the Xilinx Core Generator V1.5 > >Article: 30127
Michal Kvasnicka wrote: > = > Hi Russ > = > thanks for interesting hint. Could you be so kind and suggest me some > relevant keywords regarding the NASA "TSP" resources? > = > Regards, Michal > = > "Charles Lyttle" <lyttlec@earthlink.net> p=EDse v diskusn=EDm pr=EDspev= ku > news:3AC0AC1E.ED78312C@earthlink.net... > Michal Kvasnicka wrote: > > > > Did you read my previous posts? > > > > +>Time sampling is realized by Rubidium normal (short term stability = about > > +>10^-12 ) connected with GPS time receiver for long term stability a= bout > > +>10^-13 - 10^-15. > > > > TOA is measured as absolute time distributed in the network of the > receivers > > with accuracy about 1ns. This time is not necessarily synchronized wi= th > UTC, > > because I need only time difference (TDOA multilateration method for = 3-D > > target location) TOA_1st station -TOA_2ns station =3D TDOA_1st2nd, et= c. > > > > What now? Any suggestion from your side? > > > > Regards, Michal > > > > "Jerry Avins" <jya@ieee.org> p=EDse v diskusn=EDm pr=EDspevku > > news:3AB8F776.B4D79B0A@ieee.org... > > > Please satisfy my curiosity about what goes on here. If you know no= thing > > > about the transmitter, what instant do you measure the delay from? > > > > > > Jerry > > > -- > > > Engineering is the art of making what you want from things you can = get. > > > -------------------------------------------------------------------= ---- > > > Michal Kvasnicka wrote: > > > > > > > > Dear Juri, > > > > > > > > everything what did you write down is OK, but my problem is "pass= ive" > > > > location (TDOA multilateration without sending whole pulse train = to > the > > > > central station) not standard radar measurement. So, the transmit= ted > > signal > > > > is, in general, unknown for me. I know only some apriori informat= ion > > > > (regarding transmitted signal) which mostly play role of some > boundaries > > > > regarding received signal shape. > > > > > > > > I am looking for algorithm which is able to define some unique > reference > > > > point for each pulse and this reference point will be used for pr= ecise > > TOA > > > > measurement. > > > > > > > > If you could help me with this problem I will be really very happ= y. > > > > > > > > Best regards, Michal > > > > > > > ... > It looks like you will need to take a probabilistic approach. Try > looking for literature on Kalman filters in a feedback configuration. > You are trying to estimate the time at which the received true signal > exceeds a specified level. Traditionally, the threshold is taken as the= > 90% level. NASA has worked this problem many times, so there should be > some technical literature available from them. Most university librarie= s > can get or have NASA "TSP"s > = > -- > Russ Lyttle > "World Domination through Penguin Power" > The Universal Automotive Testset Project at > <http://home.earthlink.net/~lyttlec> I have one paper "Tests of a Differential Global Positioning System" ARC-12313. It assumes the vehicle can see the sattelites that the radars see. Check for a local NASA "Technology Utilization Center". I got good results from the one in Albuquerque, NM. Gave them some requirements and they found the documents. GTRI (Georgia Tech. Research Institute) also archives many papers. Look under : radar passive positioning to start and select subtopics from there. There are articles for the space shuttle, international space station, fighters, AWACS, commercial applications, and more. = -- = Russ Lyttle "World Domination through Penguin Power" The Universal Automotive Testset Project at <http://home.earthlink.net/~lyttlec>Article: 30128
I take the "easyproj" demo program (nothing more simple 3 inputs 2 gates 1 output) I download it into the FPGA (xc4005xl) using the XChecker cable. All is OK and the verification tells that the FPGA is well configured at anytime. Problem : All the pins of
the FPGA are pulled-up to vcc (whatever they are input or output) and the simple easyproj seams to do not even be in the FPGA ! (Note that the hardware configuration pins are set to MasterSerial and the fact that I put or not an external pull-up resistor on DONE change nothing ; the /INIT pin is not connected).
Thanx
Article: 30129You must use slave serial mode. Peter Alfke, Xilinx Applications ======================================= iPierre wrote: > I take the "easyproj" demo program (nothing more simple 3 inputs 2 gates 1 output) I download it into the FPGA (xc4005xl) using the XChecker cable. All is OK and the verification tells that the FPGA is well configured at anytime. Problem : All the pins of > the FPGA are pulled-up to vcc (whatever they are input or output) and the simple easyproj seams to do not even be in the FPGA ! (Note that the hardware configuration pins are set to MasterSerial and the fact that I put or not an external pull-up resistor on DONE change nothing ; the /INIT pin is not connected). > ThanxArticle: 30130
I'm darned if I can figure out where Xilinx par tells you the placement results. I'm using Foundation 2.1i, otherwise known as the Student Edition. Specifically, I'd like to write a program which will write hex INIT contents for a BlockRAM directly into the bitstream. My xr16vx microcontroller uses BlockRAM for main memory, and it's a pain to have to go through map/par/bitgen everytime I change its C program. The .ll file has a very nice mapping between bitstream bits and BlockRAM bits. But it's physical. For example: Bit 627473 1585 210 Block=RAMB4_R2C1 Ram=B:BIT2106 I need to find out where my Verilog/EDIF bram/memb3 RAMB4_S2_S2 ended up, so I can look it up in the .ll file. I've grepped all the files written by the normal flow, and looked at all the tool invocation switches in the Ref Manual, to no avail. I don't want to do this manually, I want to find it in some file that my program can read automatically. Somebody must know how to do this. Thanks! --MikeArticle: 30131
The "official" way to do this, is to modify the bitstream with the JBits Java Tools. (JBits URL someone?) The bitstream format is secret, so if you do not like Java you must do some reverse engineering to find out, where your block ram bits go. But that shouldn't be to hard: Generate a bitstream with all '0' in your BlockRAM and another one with all '1'. The XOR of the two bitstreams should be the BlockRAM position. But JBits is nice, so forget about the reverse engineering. Kolja Sulimma Mike Butts wrote: > I'm darned if I can figure out where Xilinx par tells you > the placement results. I'm using Foundation 2.1i, otherwise > known as the Student Edition. > > Specifically, I'd like to write a program which will write > hex INIT contents for a BlockRAM directly into the bitstream. > My xr16vx microcontroller uses BlockRAM for main memory, and > it's a pain to have to go through map/par/bitgen everytime I > change its C program. > > The .ll file has a very nice mapping between bitstream bits > and BlockRAM bits. But it's physical. For example: > Bit 627473 1585 210 Block=RAMB4_R2C1 Ram=B:BIT2106 > > I need to find out where my Verilog/EDIF bram/memb3 RAMB4_S2_S2 > ended up, so I can look it up in the .ll file. > > I've grepped all the files written by the normal flow, and > looked at all the tool invocation switches in the Ref Manual, > to no avail. I don't want to do this manually, I want to > find it in some file that my program can read automatically. > > Somebody must know how to do this. Thanks! > > --MikeArticle: 30132
Mike Butts <mbutts@realizer.com> writes: > Specifically, I'd like to write a program which will write > hex INIT contents for a BlockRAM directly into the bitstream. > My xr16vx microcontroller uses BlockRAM for main memory, and > it's a pain to have to go through map/par/bitgen everytime I > change its C program. Put dummy data (known contents) into the BlockRAM using the standard tool flow. This could simply be an old version of your microcontroller code. There aren't *that* many BlockRAMs in a part, so you can simply write your own program to inspect the data stream and figure out which BlockRAM contains the known contents, and replace it with the up-to-date code. I think all the info you need to do this for Virtex, Virtex-E, and Spartan-II is in XAPP151.Article: 30133
Kolja Sulimma wrote: > The "official" way to do this, is to modify the bitstream with the JBits > Java Tools. > (JBits URL someone?) and Eric Smith wrote: > I think all the info you need to do this for Virtex, Virtex-E, and > Spartan-II is in XAPP151. No, thanks, but that's not my problem. The .ll file tells you exactly which bit in the bitstream corresponds to which bit in your BlockRAMs, and your CLB RAMs, for example: Bit 627107 1584 240 Block=RAMB4_R1C1 Ram=B:BIT6 They tell us this mainly so we can decode readback bitstreams, but it works just as well on configurations. My problem is I need to know where on in the array it placed each of my BlockRAMs, since the .ll file is in row/column terms, like "Block=RAMB4_R1C1". For example my EDIF has a RAMB4 called bram/memb3. I need to know is it RAMB4_R1C1, or RAMB4_R2C1, or what. I expected par would write its placement into a report file, but I can't find one. Thanks! --MikeArticle: 30134
Use slave-serial. Peter Alfke ======================== iPierre wrote: > I take the "easyproj" demo program (nothing more simple 3 inputs 2 gates 1 output) I download it into the FPGA (xc4005xl) using the XChecker cable. All is OK and the verification tells that the FPGA is well configured at anytime. Problem : All the pins of > the FPGA are pulled-up to vcc (whatever they are input or output) and the simple easyproj seams to do not even be in the FPGA ! (Note that the hardware configuration pins are set to MasterSerial and the fact that I put or not an external pull-up resistor on DONE change nothing ; the /INIT pin is not connected). > ThanxArticle: 30135
Mike Butts <mbutts@realizer.com> writes: > My problem is I need to know where on in the array it placed each of > my BlockRAMs, since the .ll file is in row/column terms, like > "Block=RAMB4_R1C1". Well, as I said, there aren't that many possibilities. Just put known data in, and use the .ll file to compare each BlockRAM with the known data. The one that matches is the one you want to insert your new data into.Article: 30136
Mike, You can always open FPGA Editor on your placed and routed NCD file and look at each BlockRAM to determine the name and location. Alternatively, if you like text better, you can run the command: ncdread <design_name>.ncd -o <output_file> on your NCD. I haven't done this specifically to find BlockRAM locations, but it should tell you exactly how your design was mapped and placed in the architecture. Regards, Hobson Frater Xilinx ApplicationsArticle: 30137
How fast do you need to clock it? What is the path(s) that is/are failing timing. A look ahead carry can help on long adders like this, but it is cheaper and easier to pipeline the accumulator if you can afford the latency from input to output. To pipeline the accumulator, break it in half, register the carry out of the low half and feed it into the high half. The input value and controls for the high half must be delayed by one clock with respect to the low half, and the output of the low half requires a clock cycle delay to realign it with the top half. Before you go through all that though, there is probably more you can do with the straight ripple carry accumulator. The worst case path in arithmetic designs is usually the one from a register somewhere else leading to the adder's msb through one of the lsbs and then up the carry chain. If the register driving the accumulator is not geographically close, then you are adding a considerable routing delay to the mix. Ideally, the driving function (the registers which are producing the value you are accumulating), should be located if possible in the same clb as the corresponding bit in the accumulator. If not there, then immediately adjacent horizontally. If your accumulator has a clear, then the high fanout of the clear signal may also be a problem, although probably not in the 4K architecture (in virtex, these control signals also go to the carry chain, where in 4K they only go through the LUT with the xception of an add/subtract). The register driving the control signals for the accumulator should also be located immediately adjacent to the accumulator, and in some cases may need to be duplicated to reduce the fanout. The floorplanning to do this placement shouldn't take too long. Christian Martin wrote: > > Hello All, > > I have a timing problem with a 41-bit accumulator in a XC40150XV > device. Due to the long carry path in the accu, I can not reach the desired > frequency. Acually I use the accu from the Xilinx Core Generator V1.5 > > Do someone know wether there is an alternative core module, which I can use. > I know, that there is a Carry-Lookahead Adder for faster operation. > Is it usefull to create an accumulator of this type of adder by hand, or is > there a core module available? > > Christian Martin -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.comArticle: 30138
Mike, Why don't you put location constraints on the block ram and be done with it? The PAR tools do a lousy job placing block ram anyway, and as someone mentioned there aren't that many of them. You can place them either in a UCF (label them and the hierarchy leading to them to keep the name from changing), in the floorplanner (again label it) or embed it right in the code (requires you to instantiate the BRAMs). Mike Butts wrote: > > I'm darned if I can figure out where Xilinx par tells you > the placement results. I'm using Foundation 2.1i, otherwise > known as the Student Edition. > > Specifically, I'd like to write a program which will write > hex INIT contents for a BlockRAM directly into the bitstream. > My xr16vx microcontroller uses BlockRAM for main memory, and > it's a pain to have to go through map/par/bitgen everytime I > change its C program. > > The .ll file has a very nice mapping between bitstream bits > and BlockRAM bits. But it's physical. For example: > Bit 627473 1585 210 Block=RAMB4_R2C1 Ram=B:BIT2106 > > I need to find out where my Verilog/EDIF bram/memb3 RAMB4_S2_S2 > ended up, so I can look it up in the .ll file. > > I've grepped all the files written by the normal flow, and > looked at all the tool invocation switches in the Ref Manual, > to no avail. I don't want to do this manually, I want to > find it in some file that my program can read automatically. > > Somebody must know how to do this. Thanks! > > --Mike -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.comArticle: 30139
An alternative to JBITs may be the use of the XDL tools (dont know if your student version has them). This will take the placed and routed NCD file and dump it to an ascii file. With some significant effort, this can be parsed, and you can find out almost anything about you resultant design. The Fliptronics chip-viewer uses this path for its data extraction. I believe that virtex/spartan-II devices allow partial reconfig, including only loading/reloading the BRAM, so theoretically, you might even be able to have a program running out of one BRAM, and the program is talking to the reconfiguration logic, loading a new program into another BRAM, (another part of the I address space), and then you could jump to it. Have fun see you soon at FCCM2001, Philip On Sat, 24 Mar 2001 13:46:39 -0800, Mike Butts <mbutts@realizer.com> wrote: >I'm darned if I can figure out where Xilinx par tells you >the placement results. I'm using Foundation 2.1i, otherwise >known as the Student Edition. > >Specifically, I'd like to write a program which will write >hex INIT contents for a BlockRAM directly into the bitstream. >My xr16vx microcontroller uses BlockRAM for main memory, and >it's a pain to have to go through map/par/bitgen everytime I >change its C program. > >The .ll file has a very nice mapping between bitstream bits >and BlockRAM bits. But it's physical. For example: > Bit 627473 1585 210 Block=RAMB4_R2C1 Ram=B:BIT2106 > >I need to find out where my Verilog/EDIF bram/memb3 RAMB4_S2_S2 >ended up, so I can look it up in the .ll file. > >I've grepped all the files written by the normal flow, and >looked at all the tool invocation switches in the Ref Manual, >to no avail. I don't want to do this manually, I want to >find it in some file that my program can read automatically. > >Somebody must know how to do this. Thanks! > > --Mike Philip Freidin FliptronicsArticle: 30140
Xilinx's Timing Analyzer reports max. frequency between synchronous elements (FFs, RAMs etc) within the device. For calculating max. frequency, trce (timing engine) does not take into account "pads to synchronous elements" or "synchronous elements to pads" delays. Use "OFFSET IN" and "OFFSET OUT" constraints to constraint these paths. For details on timing constraints, refer "Timing Presentation for 3.1i" at http://www.support.xilinx.com/support/techsup/journals/timing/index.htm -Vikram Xilinx Applications Manjunathan wrote: > Hello Everybody !! > > after doing implementaion using XILINX tool,in post layout timing report it showed us maximum frequeny is 191 MZ ,but in pad report it has given a net having delay of 8.711 ns. then how is possible to work under that much frequency. > > and we checked the net delay with fpga editor it showed the same(8.711 ns). i would like to know where is the error?. > > thanks in advnce. > > regards, > ManjunathanArticle: 30141
What kind of an error message is this:
Fitting Status: Did NOT Fit
**************************** Errors and Warnings
*************************
ERROR:nd202 - Design 'confcpld' has no inputs.
A design with no inputs and three outputs does not fit into a XC9536XL
CPLD?
In the near future I want to configure an FPGA from a flash via CPLD.
But until then I need to disable the FLASH outputs to be able to connect
a download cable.
Her is the code :-)
flash_oe <= '1';
flash_we <= '1';
flash_ce <= '1';
Does anyody know how to implement this?
(I do not believe that I am asking a question like this to real experts.
I hate these tools :-(
CU,
Kolja Sulimma
Article: 30142Kolja Sulimma schrieb: > > What kind of an error message is this: > > Fitting Status: Did NOT Fit > **************************** Errors and Warnings > ************************* > ERROR:nd202 - Design 'confcpld' has no inputs. > > A design with no inputs and three outputs does not fit into a XC9536XL > CPLD? > In the near future I want to configure an FPGA from a flash via CPLD. > But until then I need to disable the FLASH outputs to be able to connect > a download cable. When programming the CPLD via JTAG, all outputs are tristated. -- MFG FalkArticle: 30143
Falk Brunner wrote: > Kolja Sulimma schrieb: > > > > What kind of an error message is this: > > > > Fitting Status: Did NOT Fit > > **************************** Errors and Warnings > > ************************* > > ERROR:nd202 - Design 'confcpld' has no inputs. > > > > A design with no inputs and three outputs does not fit into a XC9536XL > > CPLD? > > In the near future I want to configure an FPGA from a flash via CPLD. > > But until then I need to disable the FLASH outputs to be able to connect > > a download cable. > > When programming the CPLD via JTAG, all outputs are tristated. Thats right. But I want to programm the CPLD to output a logic '1' to three of its outputs like in the VHDL code that I posted: flash_oe <= '1'; flash_we <= '1'; flash_ce <= '1'; So that the FLASHROM connected to the CPLD will be tristated and I can programm the FPGA that shares its DIN pin with the FLASHs DQ0 pin.. But the tools fail to implement the code, because a circuit with no inputs allegedly does not fit in the CPLD. KoljaArticle: 30144
Kolja Sulimma schrieb: > > > When programming the CPLD via JTAG, all outputs are tristated. > > Thats right. But I want to programm the CPLD to output a logic '1' to three of > its outputs like in the VHDL code that I posted: > flash_oe <= '1'; > flash_we <= '1'; > flash_ce <= '1'; > So that the FLASHROM connected to the CPLD will be tristated and I can > programm the FPGA that shares its DIN pin with > the FLASHs DQ0 pin.. > But the tools fail to implement the code, because a circuit with no inputs > allegedly does not fit in the CPLD. Because it has a negative size. Just kidding. ;-))) Maybe use pull ups on the pins. -- MFG FalkArticle: 30145
"Rune Baeverrud" <fpga@no.spam.iname.com> wrote in message news:984659934.640452@news2.cybercity.dk... > > have you looked at the documents in > > C:/cygwin/usr/altera/excalibur/nis-sdk/technotes/ > > Could you tell us the IP address of your c-drive, please? > > Rune :) > > https://www.safeweb.com/_s:indexpg2.php3Article: 30146
Kolja Sulimma wrote: > > Falk Brunner wrote: > > > Kolja Sulimma schrieb: > > > > > > What kind of an error message is this: > > > > > > Fitting Status: Did NOT Fit > > > **************************** Errors and Warnings > > > ************************* > > > ERROR:nd202 - Design 'confcpld' has no inputs. > > > > > > A design with no inputs and three outputs does not fit into a XC9536XL > > > CPLD? > > > In the near future I want to configure an FPGA from a flash via CPLD. > > > But until then I need to disable the FLASH outputs to be able to connect > > > a download cable. > > > > When programming the CPLD via JTAG, all outputs are tristated. > > Thats right. But I want to programm the CPLD to output a logic '1' to three of > its outputs like in the VHDL code that I posted: > flash_oe <= '1'; > flash_we <= '1'; > flash_ce <= '1'; > So that the FLASHROM connected to the CPLD will be tristated and I can > programm the FPGA that shares its DIN pin with > the FLASHs DQ0 pin.. > But the tools fail to implement the code, because a circuit with no inputs > allegedly does not fit in the CPLD. Some Sw does this, so you need to give the chip some LOGIC, even if it is very simple and ultimately redundant :-). eg flash_oe = PinXX OR '1'; flash_we = PinXX OR '1'; flash_ce = PinXX OR '1'; This using a CPLD+ROM as a Loader seems to be on the increase. What size is your FLASHROM ( Content and package )? -jgArticle: 30147
Falk Brunner wrote: > > Maybe use pull ups on the pins. > Yes, since the outputs are 3-stated ( with a week pull-up, I assume ), you can generate a High by connecting 10 kilohm pull-ups on the pins in question. Once the chip is active, the driver will easily override these external resistors. Peter Alfke, Xilinx ApplicationsArticle: 30148
> > Kolja Sulimma schrieb: > > > > > > What kind of an error message is this: > > > > > > Fitting Status: Did NOT Fit > > > **************************** Errors and Warnings > > > ************************* > > > ERROR:nd202 - Design 'confcpld' has no inputs. Kolja Sulimma <kolja@bnl.gov> writes: > But the tools fail to implement the code, because a circuit with no inputs > allegedly does not fit in the CPLD. I don't think that the error message means literally that the design won't fit in the device, I think it just means that the 'fit' stage didn't complete. A place-and-route stage might fail with the message "Did not route", and the reason could be one of several. In this case, I think that the Fitting stage did not complete, so the error message is "Did Not Fit", meaning "Fitting isn't finished". Hopt this helps, -KentArticle: 30149
It's not quite appropriate to lump AHDL together with ABEL and CUPL. AHDL isn't VHDL/VERILOG, but it is capable of quite a bit larger tasks than ABEL/CUPL/PALASM unless you don't mind really large files. They do give you somewhat closer control of how resources in the target device are utilized, however. It might not be a bad thing to whip up a translator from a single SPLD in CUPL to a package in VHDL, however, since that might serve some use, some day in the future. Dick On Mon, 26 Feb 2001 07:34:46 +1300, Jim Granville <jim.granville@designtools.co.nz> wrote: >Will wrote: >> >> Got my hands on protel which supports cupl and not vhdl, but now i am >> wondering if its a waste of time to learn cupl. >> As i understand, from another question i posted somewhere, cupl is not as >> wide a standard as vhdl, so will i just end up with knowing a language which >> is not used anywhere? or will it be a sound investment of time? > > Knowing both is not a bad solution. > >The CUPL/ABEL/Altera's AHDL are all what I'd call direct entry >Hardware Description languages, and are less abstract than VHDL/Verilog. > >They allow syntax that like >Reg.ck = ClockTerm; >Reg.D = Shift & Reg1.D > # Load & Pin1.io > # Hold & Reg; > >And they allow you to 'floor plan' onto the SPLD/CPLD better. > > This is simpler, and importantly maps more directly to the PLD >underneath. >VHDL/Verilog are synthesis languages, that amount to a request for >logic, >and you hope that the SW between you and the silicon, can meet your >request >exactly. > It also means they can compile faster. > > On a FPGA, a few extra logic registers might not be a big problem, but >on >the SPLD/CPLD end of the scale, you want to know what your final >resource count >is. > > I know designers that have moved from VHDL to AlteraAHDL because it was >more >productive. > It's a bit like the Compiler Vs Assembler spins that run on uC - a good >designer >should be able to use both. > >-jg > > >-- >======= 80x51 Tools & IP Specialists ========= >= http://www.DesignTools.co.nz
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