Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Call for Participation:
SIGDA Ph.D. Forum at DAC'2001
* Submission deadline: Friday, March 16, 2001 (firm deadline)
http://www.eng.uci.edu/~daforum/
Las Vegas Convention Center
* Reviewers please sign up at
http://www.eng.uci.edu/~daforum/01/reviewer-signup.pl
The Ph.D. Forum at the Design Automation Conference is a poster session
hosted by SIGDA for Ph.D. students to present and discuss their thesis
work with people in the DA community. It is a great chance for the Ph.D.
students to get feedback on their work, and for the industry to preview
academic work-in-progress. Approximately $15,000 in travel grants will
be available to select students.
Eligible students are
* those within 1-2 years from completion of thesis, with
- either a university-approved thesis proposal,
- or at least one published conference paper.
* those who have completed their theses in the 2000-2001 academic year
Submission
* A one-page abstract of the thesis in PDF, not including figures or
references, and not to exceed 750 words. The one-page limit on the
abstract text will be strictly enforced. Any text beyond the first
page will be truncated before sending to the reviewers.
* A university-approved thesis proposal, or a published paper.
this is required of ALL students.
* Names of five reviewers whom the student would like to review the
abstract
* Web-based electronic submission system will open by March 7, 2001
at http://www.eng.uci.edu/~daforum/
Dates
* Submission deadline (firm): Friday, March 16, 2001 5pm U.S. Pacific time
* Notification Date: Monday, April 30, 2001
* Forum Presentation: Tuesday, June 19, 2001, 7-9pm
Organizers:
Pai H. Chou (UC Irvine)
Ibrahim Elfadel (IBM)
Soha Hassoun (Tufts Univ)
Robert Jones (Intel)
Diana Marculescu (CMU)
Article: 29526In article <Q25+o9SaB5l6EwID@databuzz.demon.co.uk>, alan@[127.0.0.1] (Alan Hall) wrote: > from painful experience design security is very > important for this project We've been round this loop a number of times in the ng, without coming to any universal solution. The new Xilinx devices with built-in encryption seem very interesting from this POV, but they still aren't perfect for everybody. > and we don't foresee any requirement for > changes after the design is proven. Well, all I can say is I envy you if that is truly the case! I've heard of projects where everything was clearly and explicitly defined in advance, but I've never worked on one :-) > Unfortunately it looks like Usenet isn't going to be its usual font of > knowledge :-( My gut feeling is that a lot of the people using antifuse technologies are major corporate aerospace and defence types, who are naturally unwilling to share... -- Steve Rencontre http://www.rsn-tech.co.uk //#include <disclaimer.h>Article: 29527
Austin, I don't mean to be rude, but is this circuit intended to be a "fix" to the power up issue? I can just as easily increase the surge capacity of my power converter than to add a secondary circuit to handle the few mS of startup current. The cost of this added startup circuit may be small, but it uses a lot of board space. By the time you account for the power requirement of the I grade, the board space of the chip has doubled. The other issue that I would raise with this circuit is the requirement that the voltage at startup be increased monotonically. If you depend on capacitors to provide current to the load, then the voltage will sag during that time. Perhaps the parts are not affected by a small voltage droop, hence the huge capacitor requirement. But doesn't the data sheet say that the voltage must increase monotonically? I can't find that now. Perhaps I saw it in an app note or the data sheet for the Virtex parts? Or am I mistaken about this? Austin Lesea wrote: > > Rick & Paul, > > Been out on vacation, so I missed this question. > > Spartan II is a Virtex derivative, so it has the same behavior during power up > as the Virtex family. Now this is about 2.5 years old, so it is a pretty well > known behavior. > > The ramp up time has a secondary effect on the amount of current required. > The shortest ramps require more current than the longer ramps, but as they get > close to 50 ms (the spec), the currents may start going back up again. > Current increases as temperature decreases. > > The current is required at about twice the Vt of the transistors (~0.7 to 1.0 > Vdc), and lasts perhaps as long as 200 us in the smaller parts of Spartan. > > We are now building the "kick start" circuit I had previously described. It > uses a 500 mA current limited LDO regulator with an enable pin. > > The enable pin comes from a micro power comparator /voltage reference ( we > abandoned the simple RC -- too unpredictable). > > When the input voltage (3.3 or 5 Vdc) passes a set threshold (set by two > resistors), the LDO is enabled. > > Ahead of the LDO is a ~1,000 uF 6.3 V cap that stores the necessary current to > start up the part. > > For four devices, this same technique can be extended to a larger cap, and a 2 > ampere LDO. > > The idea is quite simple: use the stored charge in the big cap to provide the > necessary kick to get all the parts started. For the I grade, at -40C, you > need 2 amps per part, and again, it is bigger capacitor, and larger regulators > (better is a low voltage switcher enabled by the comparator). > > The added cost is the mico power comparator / reference (less than 1$), two > resistors, and a big cap (<25 cents for a good aluminium electrolytic of large > value). (This assumes you have to provide a 2.5 V power supply regulator > anyway). > > In the meantime, the Spartan designers continue to optimize process / design / > test to improve the startup behavior. > > As soon as we have tested the kick starter with all process corner silicon, I > will publish it as a note. > > Again, I apologize for the delays, > > Austin -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 29528
Check out Atmel's AT17C010A configurator (www.atmel.com) Mark Tom wrote: > > Does someone know a second source for the ALTERA EPC1 configuration PROM ? > > -TomArticle: 29529
Steve Rencontre wrote: > We've been round this loop a number of times in the ng, without coming to > any universal solution. The new Xilinx devices with built-in encryption > seem very interesting from this POV, but they still aren't perfect for > everybody. Perhaps "nothing is ever perfect for everybody", but if you know of a specific issue that we should improve, or a feature we should add, please let me know. Perfection is still our goal... Peter Alfke, Xilinx ApplicationsArticle: 29530
I have some background in micro controller circuit design and now wants to learn how to use FPGA in designing circuits. Can anyone give me some recommendation on how to start? Do you think it is difficult to learn?Article: 29531
Will wrote:
>
> Got my hands on protel which supports cupl and not vhdl, but now i am
> wondering if its a waste of time to learn cupl.
> As i understand, from another question i posted somewhere, cupl is not as
> wide a standard as vhdl, so will i just end up with knowing a language which
> is not used anywhere? or will it be a sound investment of time?
Knowing both is not a bad solution.
The CUPL/ABEL/Altera's AHDL are all what I'd call direct entry
Hardware Description languages, and are less abstract than VHDL/Verilog.
They allow syntax that like
Reg.ck = ClockTerm;
Reg.D = Shift & Reg1.D
# Load & Pin1.io
# Hold & Reg;
And they allow you to 'floor plan' onto the SPLD/CPLD better.
This is simpler, and importantly maps more directly to the PLD
underneath.
VHDL/Verilog are synthesis languages, that amount to a request for
logic,
and you hope that the SW between you and the silicon, can meet your
request
exactly.
It also means they can compile faster.
On a FPGA, a few extra logic registers might not be a big problem, but
on
the SPLD/CPLD end of the scale, you want to know what your final
resource count
is.
I know designers that have moved from VHDL to AlteraAHDL because it was
more
productive.
It's a bit like the Compiler Vs Assembler spins that run on uC - a good
designer
should be able to use both.
-jg
--
======= 80x51 Tools & IP Specialists =========
= http://www.DesignTools.co.nz
Article: 29532On Sun, 25 Feb 2001 16:59:52 GMT, Peter Alfke <palfke@earthlink.net> wrote: > > >Steve Rencontre wrote: > >> We've been round this loop a number of times in the ng, without coming to >> any universal solution. The new Xilinx devices with built-in encryption >> seem very interesting from this POV, but they still aren't perfect for >> everybody. > >Perhaps "nothing is ever perfect for everybody", but if you know of a >specific issue that we should improve, or a feature we should add, please let >me know. >Perfection is still our goal... > >Peter Alfke, Xilinx Applications how about some non-volatile memory to store the key in? Muzaffer FPGA DSP Consulting http://www.dspia.comArticle: 29533
I am selecting a VHDL book. There are many out there. Since I am going to be designing for Xilinx, does this impact my choice of instructional VHDL books ? Sincerely Daniel DeConinck High Res Technologies, Inc.Article: 29534
Muzaffer Kal wrote: > > > how about some non-volatile memory to store the key in? > Excellent idea. We tried very hard, but finally gave up, and settled for the battery-backup. Adding to the process complexity would have increased cost and reduced speed for everybody, so that's not the way to go. We need to keep the process in line with mainstream microprocessors, for early availability, highest speed and lowest cost for everybody. Other tricks just did not work out. So, it was not for lack of trying... And, as we have belabored here ad nauseam, the battery is not such a bad solution, if you are serious about encryption. Peter Alfke, Xilinx ApplicationsArticle: 29535
> > > > The ramp up time has a secondary effect on the amount of current required. > > The shortest ramps require more current than the longer ramps, but as they get > > close to 50 ms (the spec), the currents may start going back up again. > > Current increases as temperature decreases. This is all a little bit strange. What happens if the current supplied by the PS is lower than 500mA?? I have the Spartan II demo board, and the power supply is current limited to about 100 mA. It works fine. I also did a quick (not very scientific ;-) test, limited the current to 20mA and had a look at the 2.5V core voltage (behind the regulator on the board). The voltage goes up to about 1 V, bends down to 0.8V (this takes about 15us) and goes straight to 2.5V (takes about 30us). This is absolutely the same for 60 and 200mA. Hmmm. Again, what happens when the power supply is too weak?? I can imagine that there can be some trouble when using serial master mode, but in slave mode, this should be an issue?? -- MFG FalkArticle: 29536
Falk, you are lucky. What we state in the data sheet, and what Austin is talking about, are worst-case numbers, when the device "wakes up" the wrong way. In your case it doesn't, thats why you have these benign currents. BTW, this has nothing to do with configuration mode choice, which becomes relevant many milliseconds later, when Vcc has already reached its nominal value. Peter Alfke ================================== Falk Brunner wrote: > > > > > > The ramp up time has a secondary effect on the amount of current required. > > > The shortest ramps require more current than the longer ramps, but as they get > > > close to 50 ms (the spec), the currents may start going back up again. > > > Current increases as temperature decreases. > > This is all a little bit strange. What happens if the current supplied > by the PS is lower than 500mA?? > I have the Spartan II demo board, and the power supply is current > limited to about 100 mA. It works fine. I also did a quick (not very > scientific ;-) test, limited the current to 20mA and had a look at the > 2.5V core voltage (behind the regulator on the board). The voltage goes > up to about 1 V, bends down to 0.8V (this takes about 15us) and goes > straight to 2.5V (takes about 30us). This is absolutely the same for 60 > and 200mA. Hmmm. > Again, what happens when the power supply is too weak?? I can imagine > that there can be some trouble when using serial master mode, but in > slave mode, this should be an issue?? > > -- > MFG > FalkArticle: 29537
I have found that using a new soldering iron tip helps tremendously in soldering large PQFP parts. Solder tends to stick onto the tip better, enabling removal of solder stubbornly stuck between pins easier. To get really accurate alignment of the FPGA on the solder pads, I shift the IC by tapping it with the soldering iron tip while pressing it down with my finger. I can make minute adjustment of 0.2 mm like this.Article: 29538
Hi: i generate a fifo with BlockRam by CoreGen in Foundation3.1,but how i do initial? Can anyone give me a example of 511x32 fifo with Verilog Language? thanksArticle: 29539
Dan, > I am selecting a VHDL book. There are many out there. > > Since I am going to be designing for Xilinx, does this impact my choice of > instructional VHDL books ? I suggest first maybe have a look at the free Xilinx Synthesis Technology (XST) User Guide 3.1i: http://support.xilinx.com/support/sw_manuals/3_1i/download/ It's very instructional on how to write your VHDL to take best advantage of the FPGA's resources. My personal preference is to write VHDL code modules / cores / macros in a generic, vendor independent style as much as possible, and then write "wrappers" if I need to instantiate vendor or architecture specific components like GCLKs or DLLs. This makes the VHDL as reusable and portable as possible. There are alot of great VHDL books out there, as you have found. One that I've found useful is "Essential VHDL, RTL Synthesis Done Right" by Sundar Rajan. This one gets my vote :-) > > > Sincerely > Daniel DeConinck > High Res Technologies, Inc. > Best regards Tony Burch www.BurchED.com.au Lowest cost, easiest-to-use FPGA prototyping kits!Article: 29540
I'm afraid I don't know much about DSP's. I implemeted Rijndael on a VirtexE FPGA using the Handel-C language (I think its produced by Celoxica... www.celoxica.com). It took me about a week to get it working, and another 2 or three to optimise. Throughput was close to 3 Gbits/sec. Andrew <satish_me@my-deja.com> wrote: Hi, I seen your response for Rijndel implementation in FPGA. I want to just know the statistical result on FPGA versus DSP of this algorithm. I need to know How many blocks it occupied, whether key storage is on memory cells, how much speed it can execute, memory consumption(cycles used).etc.. I am planning to run the same on TI -DSP If you have a data on these things please share with me Thanks in advance SATISH KUMAR Subject: Re: Rijndael From: ajadu76@hotmail.com (ajadu76@hotmail.com) I did it in a month. What FPGA part are you trying to put it on and what memory do you have available? Andrew <tchoh@my-deja.com> wrote in message news:95m5li$j87$1@nnrp1.deja.com... > > > Hi. > > I wondered if anyone out there had attempted to implement the new AES > in an FPGA. > > If so, being new to the world of crytography, I wonder if you have any > general tips/advice? > > Thanks.Article: 29541
Jim Granville writes: > I know designers that have moved from VHDL to AlteraAHDL because it > was more productive. So do I -- and not to save registers. They switched because Altera AHDL was easier and quicker for them to work with. -- JamieArticle: 29542
Let us assume that the device woke up the wrong way AND the power supply
cannot supply the .5 amp required current. What happens?
And to respond to Austin comment about this being an old problem seen
on the Virtex family.... well I have been using Lucent's parts for the
last three years and have not kept up with Xilinx. Will you please
enlighten me as to the behavior of the device should the current requirement
not be met?
Jerry English
Peter Alfke wrote:
> Falk, you are lucky. What we state in the data sheet, and what Austin is talking
> about, are worst-case numbers, when the device "wakes up" the wrong way.
> In your case it doesn't, thats why you have these benign currents.
> BTW, this has nothing to do with configuration mode choice, which becomes relevant
> many milliseconds later, when Vcc has already reached its nominal value.
>
> Peter Alfke
> ==================================
> Falk Brunner wrote:
>
> > > >
> > > > The ramp up time has a secondary effect on the amount of current required.
> > > > The shortest ramps require more current than the longer ramps, but as they get
> > > > close to 50 ms (the spec), the currents may start going back up again.
> > > > Current increases as temperature decreases.
> >
> > This is all a little bit strange. What happens if the current supplied
> > by the PS is lower than 500mA??
> > I have the Spartan II demo board, and the power supply is current
> > limited to about 100 mA. It works fine. I also did a quick (not very
> > scientific ;-) test, limited the current to 20mA and had a look at the
> > 2.5V core voltage (behind the regulator on the board). The voltage goes
> > up to about 1 V, bends down to 0.8V (this takes about 15us) and goes
> > straight to 2.5V (takes about 30us). This is absolutely the same for 60
> > and 200mA. Hmmm.
> > Again, what happens when the power supply is too weak?? I can imagine
> > that there can be some trouble when using serial master mode, but in
> > slave mode, this should be an issue??
> >
> > --
> > MFG
> > Falk
--
~~~ "It's not a BUG,
/o o\ / it's how I make my living"
( > )
\ ~ / Jerry English
_]*[_ FOE of Script Lords
Article: 29543Hi Dan If you have no idea what is VHDL I would recommend on "VHDL FOR DESIGNERS - Stefan Sjoholm and Lennart Lindth". It goes step by step with lots of examples and it's very easy to read. More advanced book is "The Designer's Guide to VHDL - Peter J. Ashenden", this is a very good one but first you should have some VHDL experience. I use VHDL for Xilinx and Altera devices and basically the VHDL code is "vendor free", the synthesis tool takes care on the vendor. If you use this approach it will be very easy to take your code and re-synthesis it for other FPGA or ASIC devices. Good luck Gil. Dan wrote: > I am selecting a VHDL book. There are many out there. > > Since I am going to be designing for Xilinx, does this impact my choice of > instructional VHDL books ? > > Sincerely > Daniel DeConinck > High Res Technologies, Inc.Article: 29544
I have 4 Ports (each 1 output Clock and 1 bidirectional data signal)
which have to be multiplexed. The selector for the multiplexer is hold
in the signal "Address". The externals on the left/right of the Virtex
manage the access by themselves. The Virtex is only used for routing.
< Clock1 - |--------------------|
<> DataIO1 - | |
| |
< Clock2 - | |
<>DataIO2 - | |- < Clock
| |- <> DataIO
<Clock3 - | Virtex |
<>DataIO3 - | |
| MUX (Address) |
<Clock4 - | |
<>DataIO4 - |--------------------|
Are there any VHDL samples or application notes?.
Thanks,
Michael
Article: 29545Hi Will Don't waste your time with CPUL, AHDL etc. There are two industry standards VHDL and VERILOG. All the synthesis tools on the market can handle VHDL or VERILOG, which means that you can target your design for different devices without changing it! Regards Gil Will wrote: > Got my hands on protel which supports cupl and not vhdl, but now i am > wondering if its a waste of time to learn cupl. > As i understand, from another question i posted somewhere, cupl is not as > wide a standard as vhdl, so will i just end up with knowing a language which > is not used anywhere? or will it be a sound investment of time?Article: 29546
Catalin Baetoniu wrote: > Does anybody know where metastable recovery information for Spartan2, > Virtex and VirtexE FPGAs can be found? I am especially interested in K1 > and K2 for VirtexE-8. I know that Peter Alfke is working on measurements for > metastable > recovery of Virtex2 but what about the parts that everybody else uses > right now? It is true that this is not a real issue for normal designs > but there is a class of applications like clock recovery from high speed > serial data where this information is essential. Don't search. This information is not available. The sad fact is that our (my) measuring technique fell to pieces. I relied on measuring metastable delays that are one half clock period long. Unfortunately (or fortunately?) the flip-flops recover so fast that I could not measure metastable delays with a 100 MHz clock rate ( 5 ns for the half period ). Now, with the Virtex-II DCM there is hope, since I can move the test clock in 50 picosecond increments. Peter Alfke, Xilinx ApplicationsArticle: 29547
Rick, Call it what you will. It is intended to aid those that have less than the 500 mA available. Initially, we thought, "anyone using this IC will probably run it at a clock speed, and with enough IO's that 500 mA will be required for its normal operation." Obviously, there is a smaller contingent of users that do not use the fast clock rates, or the large drive strengths, and need to get by with 200 or so mA. To help those users, we are working on the kick start circuit. As I said before, it is now being built, and we hope to have some results to report by next week. The area we are talking about here is pretty tiny. Surface mount caps are required anyway for good bypassing. The comparator is a tiny three leaded surface mount part (2 X 2 mm?). Resistors are pretty tiny as well. I can't see them anymore (getting old). The LDO will supply the voltage to the Vccint from the big capacitor, and at the output of the LDO, the power will be rising monotonically. The 3.3 Vdc may droop (that is why it is better if available to run the core voltage LDO off 5 Vdc), but the droop is something one engineers (I=C dV/dt) to be small. The monotonicity "rule" is not a hard rule. We care about the voltage rising through the POR trip point, and not falling back down after once passing through the POR trip point. I believe this is stated in a number of tech notes/tech tips. It may also be stated in the configuration section of the data sheet similar to how I have stated it above. This is even to be relaxed at some point in the future Virtex II as we designed it to not care about this point in the power on ramp. This is something we will later test and verify as not being a problem. As well, Virtex II power on is in the tens of mA range, so we do try to improve in every subsequent generation. Austin Rick Collins wrote: > Austin, > > I don't mean to be rude, but is this circuit intended to be a "fix" to > the power up issue? > > I can just as easily increase the surge capacity of my power converter > than to add a secondary circuit to handle the few mS of startup current. > The cost of this added startup circuit may be small, but it uses a lot > of board space. By the time you account for the power requirement of the > I grade, the board space of the chip has doubled. > > The other issue that I would raise with this circuit is the requirement > that the voltage at startup be increased monotonically. If you depend on > capacitors to provide current to the load, then the voltage will sag > during that time. Perhaps the parts are not affected by a small voltage > droop, hence the huge capacitor requirement. But doesn't the data sheet > say that the voltage must increase monotonically? I can't find that now. > Perhaps I saw it in an app note or the data sheet for the Virtex parts? > Or am I mistaken about this? > > Austin Lesea wrote: > > > > Rick & Paul, > > > > Been out on vacation, so I missed this question. > > > > Spartan II is a Virtex derivative, so it has the same behavior during power up > > as the Virtex family. Now this is about 2.5 years old, so it is a pretty well > > known behavior. > > > > The ramp up time has a secondary effect on the amount of current required. > > The shortest ramps require more current than the longer ramps, but as they get > > close to 50 ms (the spec), the currents may start going back up again. > > Current increases as temperature decreases. > > > > The current is required at about twice the Vt of the transistors (~0.7 to 1.0 > > Vdc), and lasts perhaps as long as 200 us in the smaller parts of Spartan. > > > > We are now building the "kick start" circuit I had previously described. It > > uses a 500 mA current limited LDO regulator with an enable pin. > > > > The enable pin comes from a micro power comparator /voltage reference ( we > > abandoned the simple RC -- too unpredictable). > > > > When the input voltage (3.3 or 5 Vdc) passes a set threshold (set by two > > resistors), the LDO is enabled. > > > > Ahead of the LDO is a ~1,000 uF 6.3 V cap that stores the necessary current to > > start up the part. > > > > For four devices, this same technique can be extended to a larger cap, and a 2 > > ampere LDO. > > > > The idea is quite simple: use the stored charge in the big cap to provide the > > necessary kick to get all the parts started. For the I grade, at -40C, you > > need 2 amps per part, and again, it is bigger capacitor, and larger regulators > > (better is a low voltage switcher enabled by the comparator). > > > > The added cost is the mico power comparator / reference (less than 1$), two > > resistors, and a big cap (<25 cents for a good aluminium electrolytic of large > > value). (This assumes you have to provide a 2.5 V power supply regulator > > anyway). > > > > In the meantime, the Spartan designers continue to optimize process / design / > > test to improve the startup behavior. > > > > As soon as we have tested the kick starter with all process corner silicon, I > > will publish it as a note. > > > > Again, I apologize for the delays, > > > > Austin > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAXArticle: 29548
Falk, If the power supply is too weak, the part may get stuck at asome lower voltage, never clean out, and never be ready for configuration. If the temperature exceeds the absolute maximum temperature for too long, the device will fail. This is hard to do with less than 500 mA in just about any package/part (permanent damage due to overheating). This has nothing whatsoever to do the configuration mode. The part doesn't even know what mode it is in yet while it needs this current. Austin Falk Brunner wrote: > > > > > > The ramp up time has a secondary effect on the amount of current required. > > > The shortest ramps require more current than the longer ramps, but as they get > > > close to 50 ms (the spec), the currents may start going back up again. > > > Current increases as temperature decreases. > > This is all a little bit strange. What happens if the current supplied > by the PS is lower than 500mA?? > I have the Spartan II demo board, and the power supply is current > limited to about 100 mA. It works fine. I also did a quick (not very > scientific ;-) test, limited the current to 20mA and had a look at the > 2.5V core voltage (behind the regulator on the board). The voltage goes > up to about 1 V, bends down to 0.8V (this takes about 15us) and goes > straight to 2.5V (takes about 30us). This is absolutely the same for 60 > and 200mA. Hmmm. > Again, what happens when the power supply is too weak?? I can imagine > that there can be some trouble when using serial master mode, but in > slave mode, this should be an issue?? > > -- > MFG > FalkArticle: 29549
Jerry, Sure. It just sits there at some voltage less than the required voltage to get itself going. As I already said, it is unlikely it damages itself, as the current is too small to heat up the device, or cause any EM issues on the tens of thousands (millions) of transistors weakly conducting. Also, this "problem" disappeared in Virtex once we specified the power on behavior. It was a trivial matter to design the power supply to operate properly if the engineer is told BEFORE they started on the board. That is why my first priority here at Xilinx was to specify the power on behavior for all parts (not just Virtex), and establish test programs to insure that the specification was being met. I believe we are the only FPGA company to specify and test every part for power on behavior, and perform extensive characterization in the lab on a regular basis and after every process or design change. We actually have a programmable power supply that we can use to create three independent supplies with control over the power on ramp shape and times, and the offset times between the three supplies, with programmable current limiting on each (and it captures the voltage/current waveforms as html web pages for viewing). Since we have no way of knowing every possible power supply out there, and we wouldn't want to require (like some companies) that you can only use a particular power supply, we had to be able to create a wealth of power on profiles. Austin Jerry English wrote: > Let us assume that the device woke up the wrong way AND the power supply > cannot supply the .5 amp required current. What happens? > > And to respond to Austin comment about this being an old problem seen > on the Virtex family.... well I have been using Lucent's parts for the > last three years and have not kept up with Xilinx. Will you please > enlighten me as to the behavior of the device should the current requirement > not be met? > > Jerry English > > Peter Alfke wrote: > > > Falk, you are lucky. What we state in the data sheet, and what Austin is talking > > about, are worst-case numbers, when the device "wakes up" the wrong way. > > In your case it doesn't, thats why you have these benign currents. > > BTW, this has nothing to do with configuration mode choice, which becomes relevant > > many milliseconds later, when Vcc has already reached its nominal value. > > > > Peter Alfke > > ================================== > > Falk Brunner wrote: > > > > > > > > > > > > The ramp up time has a secondary effect on the amount of current required. > > > > > The shortest ramps require more current than the longer ramps, but as they get > > > > > close to 50 ms (the spec), the currents may start going back up again. > > > > > Current increases as temperature decreases. > > > > > > This is all a little bit strange. What happens if the current supplied > > > by the PS is lower than 500mA?? > > > I have the Spartan II demo board, and the power supply is current > > > limited to about 100 mA. It works fine. I also did a quick (not very > > > scientific ;-) test, limited the current to 20mA and had a look at the > > > 2.5V core voltage (behind the regulator on the board). The voltage goes > > > up to about 1 V, bends down to 0.8V (this takes about 15us) and goes > > > straight to 2.5V (takes about 30us). This is absolutely the same for 60 > > > and 200mA. Hmmm. > > > Again, what happens when the power supply is too weak?? I can imagine > > > that there can be some trouble when using serial master mode, but in > > > slave mode, this should be an issue?? > > > > > > -- > > > MFG > > > Falk > > -- > > ~~~ "It's not a BUG, > /o o\ / it's how I make my living" > ( > ) > \ ~ / Jerry English > _]*[_ FOE of Script Lords
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z