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Seb C schrieb: > > hi, > > i obtained this error message : > > ERROR:baste:314 - NCD was not produced. All logic was removed from design. > This > is usually due to having no input or output PAD connections in the design > and > no nets or symbols marked as 'SAVE'. You can either add PADs or 'SAVE' > attributes to the design, or run 'map -u' to disable logic trimming in > the > mapper. > > what means, NCD, PAD connections, because i used hierarchy connectors for > inputs and outputs and finally i don't understand this message, it's my > single error !! > > If somebody can help me, don't hesitate !! As you wish ;-)) So, simply read the Error message again. All logic has been removed, because some internal signal are unused. So the generators (logic or FlipFlops) that generate these signals will be removed too (because they are useless). Now some other signals (that were inputs to the now removed logic/flipFlops) are unused too and so on . .. . THE GATE-EATER CAUGTH YOU!!!!!! ;-)) -- MFG FalkArticle: 29501
In article <DfIqylAd0kl6Ew5t@databuzz.demon.co.uk>, alan@[127.0.0.1] (Alan Hall) wrote: > I will shortly be starting a new design with the intention of using the > Quicklogic combined FPGA and PCI interface devices. There seems to have > been little or no discussion of these parts on this group, and I'm not > sure if this is a good sign or not. Does anyone have anything good or > bad to say about these devices, the development tools, technical > support etc? In fact has anyone actually used them? I suspect that most of us here find OTP technologies a bit of a pain. You don't get much discussion of Actel devices either, which I used quite a lot in the past. Not to say that antifuse FPGAs don't have their place, but having switched to SRAM and flash technologies, it would take a lot to make me go back. -- Steve Rencontre http://www.rsn-tech.co.uk //#include <disclaimer.h>Article: 29502
The coef change every 5 seconds, the sample rate is 100MHz, the filter outputs the result every clock cycle. There are 2 channels and 4 such filters per channel. To fit into 1 FPGA chip, the speed and area is hard for me to achieve. Thank you very much.Article: 29503
My Vim colours the UCF file without any additional syntax description. Vim seems to use the sh-shell syntax colouring, which is not bad. I think this is because of our header, the file starts with: #----------------------------------- # # UCF file for Project XYZ # # Author: Your Name # # Company: Don't know # #------------------------------------ Best Regards, -- ChrisArticle: 29504
Nicolas Matringe <nicolas.matringe@IPricot.com> writes: > Hi > I was wondering if someone had a 'UCF' (Xilinx constraint format, for > those who wouldn't know) mode for Emacs before I try and make one > myself. You can use the sh-mode in Emacs, which seems to fit somehow. It is not the correct mode, and it not very colourfull, but it is not bad either. -- ChrisArticle: 29505
Hi I try to use GSR then I include --LIBRARY ieee; library IEEE; library UNISIM; use IEEE.STD_LOGIC_1164.all; use IEEE.std_logic_unsigned.all; use UNISIM.all; I use Xilinx Foundation and try to check syntax, however it says "library logic name UNISIM cannot be mapped to a host directory" How to solve it ? Thanks al ot!Article: 29506
Try DigiKey for Xilinx parts.
www.digikey.com
and
http://info.digikey.com/T011/V4/SectB.pdf
on page 178
Philip Freidin
On Sun, 18 Feb 2001 13:42:33 -0300, "Márcio Longaray" <longaray@vortex.ufrgs.br>
wrote:
>Hi there
>
>Where on Earth can I order small quantities (ten or even less) of either
>Altera's or Xilinx' or whatever from?
>
>I contacted Altera's Distributor but their minimal order is of US$500, a
>nonsense for me.
>
>Thanks in advance for the kind directions.
>
>
>Yours,
>
>Márcio, Brazil
>
Philip Freidin
Fliptronics
Article: 29507Philip Freidin <philip@fliptronics.com> writes: > Try DigiKey for Xilinx parts. > www.digikey.com > and > http://info.digikey.com/T011/V4/SectB.pdf > on page 178 Sure would be nice if they had Spartan II parts. (It would be nice if *anyone* had Spartan II parts.)Article: 29508
Hello everyone: I am using the Xilinx Foundation Series 2.1 Student Edition to study/play with Verilog coding onto a Xilnix FPGA. I am wondering if there is a way to view the netlist produced by the synthesis tool in some schematic viewpoint? Basically, I want to learn how it synthesizes various bits of Verilog coding so I can learn how to code efficiently. Thanks PrasanthArticle: 29509
In article <memo.20010223184550.1848C@steve.rsn-tech.co.uk>, steve@?.? writes >I suspect that most of us here find OTP technologies a bit of a pain. You >don't get much discussion of Actel devices either, which I used quite a >lot in the past. Not to say that antifuse FPGAs don't have their place, >but having switched to SRAM and flash technologies, it would take a lot to >make me go back. I too am nervous about the OTP aspect (having previously used Xilinx 4K, not for PCI), but from painful experience design security is very important for this project, and we don't foresee any requirement for changes after the design is proven. It also seems a very cost-effective solution, Design-wise, having a "hard" PCI core also seems attractive, as I have the impression that there is a fair degree of fine tuning required to get the "soft" core solutions working correctly, and I cheerfully confess to being a novice in this area. Of course if there are any defects in the hard core we are stuffed, this is one area where others' experiences would have been welcome. Finally, I have the impression that Quicklogic technical support is a bit thin on the ground, certainly in the UK, and would like to know how anyone has found them in practice. Unfortunately it looks like Usenet isn't going to be its usual font of knowledge :-( Regards, -- Alan Hall, Ipswich, UKArticle: 29510
Hi, For Altera parts you can go with Arrow Electronics. Last time I checked Arrow had a $20/line item minimum order. Brian Goudy "Márcio Longaray" wrote: > Hi there > > Where on Earth can I order small quantities (ten or even less) of either > Altera's or Xilinx' or whatever from? > > I contacted Altera's Distributor but their minimal order is of US$500, a > nonsense for me. > > Thanks in advance for the kind directions. > > Yours, > > Márcio, BrazilArticle: 29511
Got my hands on protel which supports cupl and not vhdl, but now i am wondering if its a waste of time to learn cupl. As i understand, from another question i posted somewhere, cupl is not as wide a standard as vhdl, so will i just end up with knowing a language which is not used anywhere? or will it be a sound investment of time?Article: 29512
CPLD's and FPGA's are both a curse and a blessing for prototyping - gone are those happy days spent wire-wrapping zillions of TTL gates, but come are the problems soldering PQFP packages - eg a PQFP 208 has the pins at a pitch of 0.5mm. For those forced by circumstances to hand solder these objects, a couple of hints which may come in useful one day ... Soldering 0) Check which way round the package goes ... 1) Use solder paste, a very fine tip soldering iron and a microscope of some sort (stereo, 15x is good) 2) Put down a couple of blobs of solder paste for the opposite corners of the device - do not bother with paste on the rest of the connections, as you will only push it around as you seek the correct position ! 3) Normally solder paste is applied using a silk screen, or with a very expensive device that squeezes out just the wrong amount. However, I have discovered that the plastic syringes that it comes in are flexible, and it turns out that you can easily apply the correct amount by squeezing the body of the syringe and dabbing the nozzle ! 4) Start by tacking down two opposite corners of the beast only. This allows you to fine tune the position. 5) When the position is correct, Check which way round the package goes ... 6) Now solder the rest of the connections. Do this by squeezing a blob of solder paste between each pair of leads. As you heat each lead, it is fun to watch the solder paste melting and running into position. Let the soldering iron dwell on each joint for an additional second or two to make sure that the solder has run into position. 7) Clean off the flux and solder paste remains 8) Now check which way round the package is once more ... Do not be suprised if you find it has rotated 90 degrees, which leads onto the second topic ... Unsoldering a PQFP208 You should never find yourself in this position, but if you do ... 1) Use fine solder wick to remove as much solder as possible from the joints. In my experience this leaves the lead still attached to the pad. 2) Now use a very sharp scalpel blade to slide between the pad and lead - it is suprisingly easy to break the remaining solder joint without bending the lead much - and after 208 of them you will get quite good at it ! 3) The chip will now lift off, so you can clean up and resolder. Note that there is a fairly good chance that you will lift the odd pad or two which has no connections, but this usually doesn't matter. Which brings me to one of those rants - why do the people who design packages insist on making them symmetrical - perhaps they think that they are immune from Murphy's Law ? regards to all, dave - "Don't worry - I've read all about this sort of thing in books !" Dave Garnett Metapurple LimitedArticle: 29513
david garnett wrote: > Unsoldering a PQFP208 > > 2) Now use a very sharp scalpel blade to slide between the pad and lead - it > is suprisingly easy to break the remaining solder joint without bending the > lead much - and after 208 of them you will get quite good at it ! > There is another way to use the scalpel: Get a *new* blade and run it repeatedly with not too heavy pressure along the top of the leads where they join the plastic. Eventually you will cut through them. When you have cut through all 4 sides lift the armless chip off. Its easy to remove the legs & then - very important - use solder wick to clean the pads. Turn the iron's temp setting down as far as possible for this to make sure you dont lose any pads. Of course this crude method assumes you have a spare chip lying around but you did buy one or 2 didn't you ? Best to try & get hold of the more expensive versions whose pin 1 marker is fixed. > Which brings me to one of those rants - why do the people who design > packages insist on making them symmetrical - perhaps they think that they > are immune from Murphy's Law ? Even the rectangular packages have at least one way of getting it wrong - usually enough.Article: 29514
Will wrote: > > Got my hands on protel which supports cupl and not vhdl, but now i am > wondering if its a waste of time to learn cupl. > As i understand, from another question i posted somewhere, cupl is not as > wide a standard as vhdl, so will i just end up with knowing a language which > is not used anywhere? or will it be a sound investment of time? You can download free software from both Xilinx and Altera to design FPGAs in VHDL or Verilog. So why both learning CUPL? You don't need to be limimted by your software. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 29515
Falk Brunner wrote: > > Seb C schrieb: > > > > hi, > > > > i obtained this error message : > > > > ERROR:baste:314 - NCD was not produced. All logic was removed from design. > > This > > is usually due to having no input or output PAD connections in the design > > and > > no nets or symbols marked as 'SAVE'. You can either add PADs or 'SAVE' > > attributes to the design, or run 'map -u' to disable logic trimming in > > the > > mapper. > > > > what means, NCD, PAD connections, because i used hierarchy connectors for > > inputs and outputs and finally i don't understand this message, it's my > > single error !! > > > > If somebody can help me, don't hesitate !! > > As you wish ;-)) > > So, simply read the Error message again. All logic has been removed, > because some internal signal are unused. So the generators (logic or > FlipFlops) that generate these signals will be removed too (because they > are useless). Now some other signals (that were inputs to the now > removed logic/flipFlops) are unused too and so on . .. . > > THE GATE-EATER CAUGTH YOU!!!!!! > ;-)) > > -- > MFG > Falk The warning message tells you to check to see if you have no IO pins attached to your design. Did you do that? Your posting does not indicate either way. Even if you have IO pins, you have to have a complete path between an input and an output to prevent the logic from disappearing. For example, you can have a counter driving outputs, but if you did not connect a clock, then all of the counter logic will be removed by the optimizer. Turning off the optimizer will not solve your problem, but it might help you find the net that is not driven/used. Is all of this clear? I know I had a little trouble with it the first time I encountered it. But it is not a bad thing in most cases to trim unused logic. It can show you quite clearly some flaws in your design. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 29516
> You can download free software from both Xilinx and Altera to design > FPGAs in VHDL or Verilog. So why both learning CUPL? You don't need to > be limimted by your software. CUPL is bad comparad to vhdl?Article: 29517
On Fri, 23 Feb 2001 18:45 +0000 (GMT Standard Time), steve (Steve Rencontre) wrote: >In article <DfIqylAd0kl6Ew5t@databuzz.demon.co.uk>, alan@[127.0.0.1] (Alan >Hall) wrote: > >> I will shortly be starting a new design with the intention of using the >> Quicklogic combined FPGA and PCI interface devices. There seems to have >> been little or no discussion of these parts on this group, and I'm not >> sure if this is a good sign or not. Does anyone have anything good or >> bad to say about these devices, the development tools, technical >> support etc? In fact has anyone actually used them? > >I suspect that most of us here find OTP technologies a bit of a pain. You >don't get much discussion of Actel devices either, which I used quite a >lot in the past. Not to say that antifuse FPGAs don't have their place, >but having switched to SRAM and flash technologies, it would take a lot to >make me go back. Steve, on one prototype, our production people desoldered/replaced one Actel chip nine times, and lost only one pad. We gave them a bonus, and fired the engineer. We use Xilinx now. JohnArticle: 29518
On Sat, 24 Feb 2001 12:54:16 -0000, "david garnett" <dave.garnett@metapurple.co.uk> wrote: >CPLD's and FPGA's are both a curse and a blessing for prototyping - gone are >those happy days spent wire-wrapping zillions of TTL gates, but come are the >problems soldering PQFP packages - eg a PQFP 208 has the pins at a pitch of >0.5mm. For those forced by circumstances to hand solder these objects, a >couple of hints which may come in useful one day ... > >Soldering > >0) Check which way round the package goes ... > >1) Use solder paste, a very fine tip soldering iron and a microscope of some >sort (stereo, 15x is good) > >2) Put down a couple of blobs of solder paste for the opposite corners of >the device - do not bother with paste on the rest of the connections, as you >will only push it around as you seek the correct position ! > >3) Normally solder paste is applied using a silk screen, or with a very >expensive device that squeezes out just the wrong amount. However, I have >discovered that the plastic syringes that it comes in are flexible, and it >turns out that you can easily apply the correct amount by squeezing the body >of the syringe and dabbing the nozzle ! > >4) Start by tacking down two opposite corners of the beast only. This allows >you to fine tune the position. > >5) When the position is correct, Check which way round the package goes ... > >6) Now solder the rest of the connections. Do this by squeezing a blob of >solder paste between each pair of leads. As you heat each lead, it is fun to >watch the solder paste melting and running into position. Let the soldering >iron dwell on each joint for an additional second or two to make sure that >the solder has run into position. > >7) Clean off the flux and solder paste remains > >8) Now check which way round the package is once more ... Do not be suprised >if you find it has rotated 90 degrees, which leads onto the second topic ... > >Unsoldering a PQFP208 > >You should never find yourself in this position, but if you do ... > >1) Use fine solder wick to remove as much solder as possible from the >joints. In my experience this leaves the lead still attached to the pad. > >2) Now use a very sharp scalpel blade to slide between the pad and lead - it >is suprisingly easy to break the remaining solder joint without bending the >lead much - and after 208 of them you will get quite good at it ! > >3) The chip will now lift off, so you can clean up and resolder. Note that >there is a fairly good chance that you will lift the odd pad or two which >has no connections, but this usually doesn't matter. > >Which brings me to one of those rants - why do the people who design >packages insist on making them symmetrical - perhaps they think that they >are immune from Murphy's Law ? > >regards to all, > >dave >- >"Don't worry - I've read all about this sort of thing in books !" >Dave Garnett Metapurple Limited > > Dave, my production people tack down two corner pins, put liquid flux on the rest, and feed the solder from the iron tip onto the pins. They have a special tip that has a small solder-reservoir groove... they fill the groove and run the tip down a whole row of pins, and each pin seems to slurp its fair share. They prefer to *hand solder* the fine-pitch parts, even though we solder paste, pick-n-place, and reflow everything else. They use some sort of infrared thingie to desolder all the pins at once. Checking the orientation does seem like a good idea. JohnArticle: 29519
Falk Brunner wrote: > > Austin Lesea schrieb: > > > > For those interested: > > > > http://www.xilinx.com/products/virtex/techtopic/vtt013.pdf > > ;-))) This is getting funny. > > > Comments are appreciated, > > Hmm, what should we expect?? That Altera says the Xilinx parts are > better?? > And Xilinx says the Altera parts are better?? > Both "experiments" have their points, but they both have the smell of > marketing and influenced by company policy. > Its like the Pepsi and Coca fight . . . > After all, both devices must prove their qualities in real world > appllication, its alwas possible to bring a good device down on the > knees with a heavy test (and vica versa ;-)) > > -- > MFG > Falk Yes, and this also ignores the many other issues involved in picking an FPGA vendor. I am working with a company that does not commit to a single vendor. They do their FPGA designs in HDL and do not use heavily the proprietary features unless necessary. They then pick the chip for the board at the final stage before building the prototype. This maximizes their leverage and gets them the best price for their boards. Of course there are times that they have to pick one or the other based on technical features. A new design with 10 Gbps fiber interface was just not doable in a Xilinx part because of the high speed (622 MHz) data path. The Altera part does this with a single clock. The Xilinx solution was to use a clock for every two data pins. They would have then needed fifos to resync the data to a common clock. The designers felt this was not workable. I personally am more impressed with the Xilinx parts. I recently found that the low cost ACEX parts from Altera (based on the 10K arch) does not let you use the LUTs as RAM. I see this as a major drawback when you need many small fifos. But again a non-technical issue of supply may force me to use the ACEX instead of the Spartan II parts. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 29520
"Alan Hall" <alan@[127.0.0.1]> wrote in message
news:DfIqylAd0kl6Ew5t@databuzz.demon.co.uk...
> I will shortly be starting a new design with the intention of using the
> Quicklogic combined FPGA and PCI interface devices. There seems to have
> been little or no discussion of these parts on this group, and I'm not
> sure if this is a good sign or not. Does anyone have anything good or
> bad to say about these devices, the development tools, technical support
> etc? In fact has anyone actually used them?
> --
> Alan Hall, Ipswich, UK
Alan,
In the days of old, when the earth was being bombarded with nasty
neutrinos and I used Actel, I remember the Actel FAE, Actel manufacturer's
rep and disty telling me that they would supply me with as many Actel chips
as I needed for prototyping. This, of course, was to entice me to use
Actel.
Strangely, when I came to needing the chips, the Actel FAE,
manufacturer's rep and disty had a fight as to who was going to provide me
with the chips. It seems that each was assuming that the other guy was
"promising" to supply the chips. When you need chips, you need chips;
however, while these guys are fighting in the background. precious time is
being wasted.
The moral of the story: program either the FPGAs or the reps correctly
first time around when using OTPs.
Simon Ramirez, Consultant
Synchronous Design, Inc.
Article: 29521Rick & Paul, Been out on vacation, so I missed this question. Spartan II is a Virtex derivative, so it has the same behavior during power up as the Virtex family. Now this is about 2.5 years old, so it is a pretty well known behavior. The ramp up time has a secondary effect on the amount of current required. The shortest ramps require more current than the longer ramps, but as they get close to 50 ms (the spec), the currents may start going back up again. Current increases as temperature decreases. The current is required at about twice the Vt of the transistors (~0.7 to 1.0 Vdc), and lasts perhaps as long as 200 us in the smaller parts of Spartan. We are now building the "kick start" circuit I had previously described. It uses a 500 mA current limited LDO regulator with an enable pin. The enable pin comes from a micro power comparator /voltage reference ( we abandoned the simple RC -- too unpredictable). When the input voltage (3.3 or 5 Vdc) passes a set threshold (set by two resistors), the LDO is enabled. Ahead of the LDO is a ~1,000 uF 6.3 V cap that stores the necessary current to start up the part. For four devices, this same technique can be extended to a larger cap, and a 2 ampere LDO. The idea is quite simple: use the stored charge in the big cap to provide the necessary kick to get all the parts started. For the I grade, at -40C, you need 2 amps per part, and again, it is bigger capacitor, and larger regulators (better is a low voltage switcher enabled by the comparator). The added cost is the mico power comparator / reference (less than 1$), two resistors, and a big cap (<25 cents for a good aluminium electrolytic of large value). (This assumes you have to provide a 2.5 V power supply regulator anyway). In the meantime, the Spartan designers continue to optimize process / design / test to improve the startup behavior. As soon as we have tested the kick starter with all process corner silicon, I will publish it as a note. Again, I apologize for the delays, Austin Rick Collins wrote: > Paul Smith wrote: > > > > How are people handling the large (500 mA) startup current for a Spartan > > II device? > > The data sheet implies this can be reduced by ramping the power supply > > up over 50 mS, but doesn't say what the startup current will be reduced > > to. Is anyone doing this? > > > > Also, maybe I'm not looking in the right place, but I can't find > > anything about how to estimate the power needed for a running device. > > There must be some algorithm that lets one estimate this based on clock > > frequency and percentage of device switching? > > > > Paul Smith > > Indiana University Physics > > This is a question that has appeared here several times already. The > Xilinx people can give you a lot of data, which they may have done > offline as they did with me. But none of it helps me to get around the > 500 mA requirement. The new board I am building will have 5 FPGAs on a > very small board. To have to supply 2.5 Amps, even for a brief moment at > startup, is a very hard thing to do on this board since it makes it's > own 2.5 volts. > > I never got the info on what the Spartan II would do if you could only > supply 400 mA, for example. They will tell you that different Vdd ramp > speeds require different supply currents. But they do not have any hard > data to tell you that a specific ramp rate will only require X mA of > supply current. > > But then I keep hearing how you can't get them anyway, so how does it > matter what current they draw? > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design > > Arius > 4 King Ave > Frederick, MD 21701-3110 > 301-682-7772 Voice > 301-682-7666 FAX > URL http://www.arius.comArticle: 29522
Hi, CUPL can be usefull for very simple designs for PAL devices, other than that I would recomend learning VHDL or Verilog. Brian Goudy Will wrote: > Got my hands on protel which supports cupl and not vhdl, but now i am > wondering if its a waste of time to learn cupl. > As i understand, from another question i posted somewhere, cupl is not as > wide a standard as vhdl, so will i just end up with knowing a language which > is not used anywhere? or will it be a sound investment of time?Article: 29523
Hi David , my 2 pennys. david garnett wrote: > CPLD's and FPGA's are both a curse and a blessing for prototyping ... > Soldering > 0) Check which way round the package goes ... > 1) Use solder paste, a very fine tip soldering iron and a microscope of some > sort (stereo, 15x is good) If your not use to solder paste, then your not going to like the results. You will always make solder balls and you "Must" vent away the fumes of solder paste. You can use a hot air tool, but you can always use a ESD safe soldering iron. > 2) Put down a couple of blobs of solder paste for the opposite corners of > the device If you hand soldering, I've found a safer way. Put liquid rosin flux on pads. Put the FPGA into place, Wait 20, 30 sec. Thr rosin flux will be getting sticky. Get all the pins aligned, use a zoom scope. Touch a pad for a sec. the rosin will get gummy. This sticky rosin will hold the pin in place, Go around the whole IC. When your sure the PQFP is aligned, then use 0.010 solder. ... snip ... > 6) Now solder the rest of the connections. Do this by squeezing a blob of > solder paste between each pair of leads. As you heat each lead, it is fun to > watch the solder paste melting and running into position. Let the soldering > iron dwell on each joint for an additional second or two to make sure that > the solder has run into position. > > 7) Clean off the flux and solder paste remains I like useing either iso-propyl or ethyl alcohol. ... snip ... > Unsoldering a PQFP208 > You should never find yourself in this position, but if you do ... Use a hot air tool if possible. If not then alot of rosin flux and the smallest solder wick , look at Chemtronics for the free Solder wick chart. The small wick will not take away all of the heat from the soldering iron, also causing as less thermal damage to the tiny pads. A Weller WTCP w/ a #7 tip works all the time. > 1) Use fine solder wick to remove as much solder as possible from the > joints. In my experience this leaves the lead still attached to the pad. > 2) Now use a very sharp scalpel blade to slide between the pad and lead ... snip ...Article: 29524
Does anybody know where metastable recovery information for Spartan2, Virtex and VirtexE FPGAs can be found? I am especially interested in K1 and K2 for VirtexE-8. In the VirtexE Data Sheet the word "metastability" is not even mentioned and the only AppNote that adresses the issue (XAPP094) is 4 years old and for obsolete FPGAs that except for legacy designs nobody uses anymore. I know that Peter Alfke is working on measurements for metastable recovery of Virtex2 but what about the parts that everybody else uses right now? It is true that this is not a real issue for normal designs but there is a class of applications like clock recovery from high speed serial data where this information is essential. Catalin Baetoniu Starnet Engineering Inc.
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