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"Jay" <kayrock66@yahoo.com> skrev i meddelandet news:d049f91b.0204030946.26f0ea69@posting.google.com... > Check the parallel port settings for your PC in the BIOS. This will > control the drive of the port pins used to control that TTL part. > Some settings just have a slow pull up on the plus side, others > actually drive the pin high. > > And as a matter of fact, the old original Byteblaster used the LS part > and was 5V only, the newer Byteblaster MV had to have used an HC part > to support both 5V and 3.3V chips. > > Regards I think the problem was that I forgot to add a decoupling capacitor for the 244 which Russel so nicely pointed out in his last message. After adding the capacitor everything works perfectly. I pointed this out in my last message but maybe it didn't show on the newsserver. Thanks for the help. ArbitraryArticle: 41626
Uzytkownik "crob" <crob714@yahoo.com> napisal w wiadomosci news:cb769f6b.0204030943.2d745fd@posting.google.com... > It's simple. If you want an ARM core, use Altera's Excalibur family. > This is a cost-effective method if you want an ARM microprocessor Cos effective? Altera's dealer told me that prices are starting from $1000 (in Poland) to $5000. I wanted to buy ARM kit two weeks ago. When he told me that kit costs $10k, and chips are starting from $1k - I stopped ;) > connected directly to a PLD. > > As for the slogan, "Half the size and twice the speed of NIOS", leave > this were it belongs, with the Marketing weenies. I have used the > MicroBlaze microprocessor, and couldn't get close to the numbers > claimed, go figure. I also noticed a SIGNIFICANT decrease in > performance when I ran my code from external memory. Interesting. Don't you know how it looks like in Nios? - my Nios is waiing for... taxes (those taxes which are applied to stuff when crossing national border - I don't know their name in English ;) jerryArticle: 41627
jerry1111 wrote: > > Uzytkownik "crob" <crob714@yahoo.com> napisal w wiadomosci > news:cb769f6b.0204030943.2d745fd@posting.google.com... > > It's simple. If you want an ARM core, use Altera's Excalibur family. > > This is a cost-effective method if you want an ARM microprocessor > Cos effective? > Altera's dealer told me that prices are starting from $1000 (in Poland) > to $5000. I wanted to buy ARM kit two weeks ago. When he told > me that kit costs $10k, and chips are starting from $1k - I stopped ;) You have to need the speed, and tight coupling :-) At the other end of the scale, the lowest price spotted so far, for a ARM microcontroller (Off chip memory) is $4.95/10K from OKI See http://www.okisemi.com/html/docs/Intro-7830.html That's under x188 / x186 / eZ80 ... -jgArticle: 41628
C-ROB, Obviously, when one does a performance test, one does not go off chip to memory. It is much faster to execute out of BRAM, and show what the part is capable of doing. It would be like testing a Pentium IV with SDR 133 MHz RAM..... As for the difference when on-chip, I can only guess that you were doing something different from what was done for the benchmark. Did you open a hotline case at the time, and ask why? Austin crob wrote: > It's simple. If you want an ARM core, use Altera's Excalibur family. > This is a cost-effective method if you want an ARM microprocessor > connected directly to a PLD. > > As for the slogan, "Half the size and twice the speed of NIOS", leave > this were it belongs, with the Marketing weenies. I have used the > MicroBlaze microprocessor, and couldn't get close to the numbers > claimed, go figure. I also noticed a SIGNIFICANT decrease in > performance when I ran my code from external memory. > > C-ROB > > Austin Lesea <austin.lesea@xilinx.com> wrote in message news:<3CAA3906.C7F98F3@xilinx.com>... > > Ron, > > > > You can put any soft processor core you want in the Virtex II, or II Pro, as long as > > they are small enough to fit in the FPGA. > > > > Of course, there are royalty issues when using the ARM core. > > > > The PowerPC(tm IBM) license allows unlimited use of the PowerPC core in Virtex II > > Pro. And the license is free. MicroBlaze is also free. > > > > Austin > > > > Ron Huizen wrote: > > > > > Peter, > > > > > > Are you saying that putting an ARM core into a Virtex II is not doable, > > > or just not practical? Or are you only talking about the V2 Pro? > > > > > > --------- > > > Ron Huizen > > > BittWare > > > > > > Peter Alfke wrote: > > > > > > > > "Cyrille de Brébisson" wrote: > > > > > > > > > In our design we are using an ARM CPU. My question is: > > > > > Can we put an ARM in the virtex 2 pro? > > > > > Were can I find/buy an ARM cpu core source (or precompiled) file to program > > > > > in my FPGA? > > > > > > > > > > > > > Cyrille, > > > > the answer to both your questions is: No. > > > > The PowerPC in Virtex-II Pro is a "hard" implementation, packing the > > > > microprocessor with its caches and MMU into the smallest possible silicon > > > > area, <4 square millimeters. > > > > What you seem to be looking for is a "soft" implementation, using the > > > > programmable logic "fabric". > > > > That solution is impractical for something as complex as PowerPC or even ARM. > > > > It would take up an unreasonable portion of a large chip, and achieve mediocre > > > > performance at best. > > > > Xilinx offers a soft microprocessor, called MicroBlaze, especially tuned for > > > > efficient implementation in the Virtex architecture. It is not as fast and > > > > capable as PowerPC, but uses only ~900 slices. > > > > "Half the size and twice the speed of NIOS" is the Xilinx slogan. Please, no > > > > flames... > > > > > > > > Peter Alfke, Xilinx ApplicationsArticle: 41629
Depends on your design. If you want the max toggle frequency, I believe that
is in the data sheet (I don't know it for the ACEX off hand), however, most
real designs will not be able to be clocked any where near that rate and if
they are they probably need a hefty heatsink on the FPGA.
"S³awomir Balon" wrote:
> Hi!
> I'm planning to use ACEX devices in my designs. Can anyone tell me what is
> maximum clock frequency for -2 and -3 devices?
> I mean external clock input (without clock-lock option).
> thanx
> Slawek
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 41630crob wrote: > I also noticed a SIGNIFICANT decrease in > performance when I ran my code from external memory. No surprise, and an excellent argument for on-chip microprocessors running out of on-chip caches and BlockRAM, and having good connectivity to the FPGA fabric. Let me stop here, before I get into my Virtex-II Pro with PowerPC pitch... :-) Peter AlfkeArticle: 41631
"Peter Alfke" <peter.alfke@xilinx.com> wrote: > crob wrote: > > I also noticed a SIGNIFICANT decrease in > > performance when I ran my code from external memory. > > No surprise, and an excellent argument for on-chip microprocessors running out of on-chip caches > and BlockRAM, and having good connectivity to the FPGA fabric. If you're going to stay on chip, you might as well assume a 16-bit address space. Once you've done that, a <200 LUT 16-bit RISC MCU will often suffice. :-) If you're going to choose a 32-bit CPU because you want to use some of those great sprawling OSs and RTOSs and TCP/IP stacks and so forth, then it is likely that your application will not fit in on-chip RAM, and you should choose a microprocessor that provides at least an I-buffer, or I-cache, or branch target cache, lest your processor stall every instruction or branch. (Even if you have adequate bandwidth to off-chip instruction memory, the branch latency (nonsequential instruction fetch latency) will kill you.) A 20-50 MHz RISC CPU can get by with flow-through external SRAM. But at 125 MHz and up, plan to use an I-cache. The good news it is fairly simple to add an I-cache to an FPGA CPU core, assuming it already has an "instruction not ready signal". Of course, caches are also important to reduce core external bandwidth requirements. Using caches, you may be able to share a common memory interface with other cores, or may be able to use a 16-bit external memory data path instead of a 32-bit one. Jan Gray, Gray Research LLCArticle: 41632
In <3CAB7A34.F16B1AC4@xilinx.com>, Peter Alfke wrote: > crob wrote: > >> I also noticed a SIGNIFICANT decrease in >> performance when I ran my code from external memory. > > No surprise, and an excellent argument for on-chip microprocessors > running out of on-chip caches and BlockRAM, and having good connectivity > to the FPGA fabric. Let me stop here, before I get into my Virtex-II Pro > with PowerPC pitch... :-) > > Peter Alfke Xilinx has made some curious choices with the VirtexII Pro line and I was wondering if Peter would comment on some of them. First off let me say that the PPC was the right choice. Over the last few years the embedded processor of choice at all of the places that I have consulted to has been the 405. I also think that combining a 405 with an FPGA makes a lot of sense, it goes a long way towards being able to build a single chip customized embedded system without having to do an ASIC. Now for the things that I think were a little curious, 1) How come there isn't a dedicated DDR interface on the chip. I've never seen a PPC application that didn't require DRAM, a dedicated interface would be cheaper and higher performing than using valuable CLBs to build a soft interface. (If I'm mistaken about the lack of a dedicated DDR interface please let me know, I didn't see any mention of one when I read the spec). 2) I don't see the need for putting four processors on a die. In almost all cases a single 405 should be adequate, in a few case you could make good use of two but I don't think that you would ever need four. There should have been a wider choice of parts with a single 405 core. 3) There should also be a wider range of parts that have Rocket IO but no PPC. This is really a 2003 time frame issue when 3GIO starts to roll out, at that point Rocket IO will become very important. 4) On chip Flash RAM would be useful. An embedded PPC is going to require some Flash. Also it would be nice if the serial Flash RAM were on chip, I bet every one is sick of the extra part that most Xilinx designs require. 5) The IBM 405 chips include on board ethernet MACs, a PCI interface and an SDRAM interface, a version of that chip that also incorporates an FPGA and FLASH would be a good idea. In theory you could handle almost any embedded application with just that one chip plus an SDRAM or two. 6) This is a Virtex II issue, not just a Virtex II Pro issue. How about offering versions of the Virtex II without the on board multipliers. The multipliers make sense for DSP applications but they are a waste of money and power for everything else. In my 12 years doing Xilinx designs I have never needed a multiplier. I've frequently needed a CAM so I wouldn't mind a few CAMs on board, but I'd rather have a cheaper part without the multiplers.Article: 41633
I'll put in my 2 cents worth on a few items below regarding the aspects I've come to appreciate... "B. Joshua Rosen" wrote: > 1) How come there isn't a dedicated DDR interface on the chip. I've never > seen a PPC application that didn't require DRAM, a dedicated interface > would be cheaper and higher performing than using valuable CLBs to build > a soft interface. (If I'm mistaken about the lack of a dedicated DDR > interface please let me know, I didn't see any mention of one when I read > the spec). > > 2) I don't see the need for putting four processors on a die. In almost > all cases a single 405 should be adequate, in a few case you could make > good use of two but I don't think that you would ever need four. There > should have been a wider choice of parts with a single 405 core. For both 1) and 2), the intent isn't exclusively to replace the processor in an embedded system, but to distribute the tasks. If you're dealing with an IP block that needs some intelligence, a single PPC could be used to take care of the somewhat complex - though limited - functionality needed. Why do almost all systems require a DRAM interface? Because there's just sooo much functionality pushed into a single general purpose machine. If you can distribute the processing and keep the code requirements small for some functional blocks, a main CPU could take care of the big tasks outside of the FPGA when performance wouldn't allow the little Virtex-II PPC to keep up with all the system demands. > 4) On chip Flash RAM would be useful. An embedded PPC is going to require > some Flash. Also it would be nice if the serial Flash RAM were on chip, > I bet every one is sick of the extra part that most Xilinx designs > require. I've been finding more ways to deal with external flash memory. I'd prefer to keep the FPGA cost constrained and get cheap generic flash rather than spending more for a process that isn't optimum for either the logic or the memory. > 6) This is a Virtex II issue, not just a Virtex II Pro issue. How about > offering versions of the Virtex II without the on board multipliers. The > multipliers make sense for DSP applications but they are a waste of money > and power for everything else. In my 12 years doing Xilinx designs I have > never needed a multiplier. I've frequently needed a CAM so I wouldn't > mind a few CAMs on board, but I'd rather have a cheaper part without the > multiplers. Do you find yourself designing shifters? Both barrel shifters and straight shifters are nicely implemented in the multiplier blocks. Whether to align a SONET bit stream to the byte oriented frame or to insert/extract variable bit-width items into/from serial streams, shifters have been an important part of many of my designs.Article: 41634
On Wed, 03 Apr 2002 07:11:58 -0800, John_H <johnhandwork@mail.com> wrote: >Is the 0.8V p-p only on the positive logic level of an LVTTL signal? > The ripple I saw is in on the positive logic level, but i can't say that is "only" on the positive level, because the duration of low level of the signal with the ripple is shorter than the frequency of ripple, so i can't see the 0.8 V PP on the low level. I think that the ignal is not an LVTTL because the Spartan I use do not use that levels. On the signal without pollution the high logic level is about 4.1-4.3 Volts. Frank.Article: 41635
Can someone explain the following OPS: din_zx din_zxp split split_y in the file "microcode.csv" on the Free6502 page Or better yet, if you know of a document that describes all the ops, please tell me. Thank you WillArticle: 41636
>It depends on what you're trying to do with your clock, need to supply >more detail... ok, i'm planning to use it for aquiring datas from two 8 bit flash adc (AD9057) clocked at 80MHz both but clocks are shifted by 180deg in phase (effectivelly 160MHz) will APEX -3 be fast enough to work with, or should i use a -2 device (this data will be stored in fast 16 bit SRAM). regards SlawekArticle: 41637
I will like to know if there is anyone who can explain to me how Bitgen's (Xilinx tool's bit stream generation program) /Gclkdel option works. This is an option Xilinx uses for 66MHz PCI in Virtex/Virtex-E/Spartan-II/Spartan-IIE, but it seems like a guarded secret. () If someone can explain to me how this feature works, drop me off an E-mail at RemoveThis_kevinbraceusenet@hotmail.com. (Obviously, remove "RemoveThis_" from the E-mail address.) Thanks, Kevin BraceArticle: 41638
> If I add a 10kohm resistor between the pin and GND the ripple is off, > but the high voltage is only 3.6 Volt. What is the output impedance of the device which is generating your signal? Sounds like a mismatch problem. adrianArticle: 41639
I see what you mean! - my first hit was the following ......
On 3 Apr 2002 03:01:42 -0800, Bill Sloman <bill.sloman@ieee.org> wrote:
> Sylvan Butler <Znospam+noZs_0204@hpb13799Z.Zboi.hpZ.com.invalid> wrote in message news:<slrnaakknf.m1j.Znospam+noZs_0204@hpb13799Z.Zboi.hpZ.com.invalid>...
>> On 30 Mar 2002 11:10:55 -0800, Bill Sloman <bill.sloman@ieee.org> wrote:
>> > But you do support the NRA, which implies some level of neural damage.
>>
>> Coming from you that is quite a compliment, so thank you. :)
>
> On the basis that if I think it is stupid to support the NRA, it must
> actually be clever to support the NRA. This is a sounder argument that
> most that come from the NRA, if fatally flawed by being wrong - it is
> stupid to support the NRA because they misuse and misinterpret the
> statistical evidence available in a way that any non-stupid
> well-informed adult ought to be able to detect and reject. On this
> subject I'm just a well-informed adult, rather than a dangerous lefty.
No, you are either mis-informed or an idiot. Probably the former.
sdb
--
| Sylvan Butler | Not speaking for Hewlett-Packard | sbutler-boi.hp.com
|
| Watch out for my e-mail address. Thank UCE. #### change ^ to @ ####
|
They that can give up essential liberty to obtain a little temporary
safety deserve neither liberty nor safety. --Benjamin Franklin, 1759
Fight terrorism, arm the population!
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Posted via Mailgate.ORG Server - http://www.Mailgate.ORG
Article: 41640www.hunteng.co.uk www.xilinx.com , you can find all the third party development board. "Tom Loftus" <hdlman@hotmail.com> wrote in message news:5e68a941.0203290720.4fe62f2c@posting.google.com... > antipattern@hotmail.com (Unit Manager) wrote in message news:<e1f38cc5.0203290119.6aeecfb2@posting.google.com>... > > Do you aware of any Virtex II pro development board on market? > > > You might want to contact your local NuHorizons rep and > see if their Engineering Solutions Platform is what you > are looking for. I haven't used it myself but just > happened to hear about it a few days ago. Not clear > that it supports the "Pro" part yet, but I don't see > why it wouldn't. > > http://www.nuhorizons.com/EngineeringServices/esp/ESPBoard.html > > TomArticle: 41641
Just keep hearing about this hand placement thing, don't know how it is done in reality. Does someone actually use their hands to do the placement as opposed to CAD based P&R. Any hints? -- ----------------------------------------------------- Click here for Free Video!! http://www.gohip.com/freevideo/Article: 41642
Greetigns All, I have always found it more natural to work with schematics than an HDL (although learnign vhdl is proving very usefull in some areas...) I have used the Aldec schematic capture program from Xilinx Foundation 3/4 and ECS from Webpack. Thus far, I am somewhat underwhelmed by these tools - I have always felt that a good tool (eg text editor, ide etc.) should allow you to work about as fast as you can enter data, and this is just not the case with the schematic capture tools I have used. So my question is: Does anyone know of a powerfull, flexible schematic editor with decent (preferably configurable) key bindings, rock like stability, a nice user interface, highly intuitive, that is fast and a pleasure to use etc? One that uses an HDL description of each schematic behind the scenes ECS style is probably a plus. Or should I just be gratefull I'm not directly entering netlists... ;-) Cheers, Chris SaunterArticle: 41643
I would like to program Lattice ispLsi 2192 devices. I would like to have a source code like ispcode7 from Lattice. But it should work on Win NT. Does anybody know something?Article: 41644
I'm rather frustrated with a new SpartanII design I have assembled as I can't get it to talk JTAG. I've got a homemade programming cable based on the parallel III schematic. Spartan Vccos are within 5% of 3.3v and Vccints 2.5v. There are close decoupling caps though admittedly not on every supply pin. The cable is supplied from 5v but of course has one diode drop to the HC125 Vccs. Having no luck with Impact I've also run some trusted code (based on JFlash for SA1100 but tweaked to use parallel III hardware), watched TDI+TCK+TMS do their thing to try to extract the device ID but TDO stays high (maybe assisted by the 5k1 pullup in the cable). I've ordered a real parallel IV cable but think there must be something else wrong. I've checked everything so many times now. It may seem like a funny question but what am I most likely to have done wrong ? Thank you in advance, JonArticle: 41645
Joshua, Maybe I can comment, as I was on the VII Pro team, and the VII team. See below, Austin ---------------------snip---------------- > > > 1) How come there isn't a dedicated DDR interface on the chip. I've never > seen a PPC application that didn't require DRAM, a dedicated interface > would be cheaper and higher performing than using valuable CLBs to build > a soft interface. (If I'm mistaken about the lack of a dedicated DDR > interface please let me know, I didn't see any mention of one when I read > the spec). DDR is built out of the DDR FF in the IOB's and logic in the FPGA. DDR isn't the only standard, and customers have many other applications. DDR is neat, but too specific. > > > 2) I don't see the need for putting four processors on a die. In almost > all cases a single 405 should be adequate, in a few case you could make > good use of two but I don't think that you would ever need four. There > should have been a wider choice of parts with a single 405 core. We just don't know how customers will use all of this power. If 405ppc's are 'free', you can use one executing out of internal cache to handle the "error 404", and another running off internal cache to monitor QOS, etc. When electric motors were very expensive, a machine shop had one, and leather belts to every tool station. When fractional horsepower motors became inexpensive and ubiquitous, they were used everywhere, with no thought. If 405ppc are everywhere, you may dedicate them to tasks that seem horribly inefficient if you continue to think in terms of the one big expensive monster processor. > > > 3) There should also be a wider range of parts that have Rocket IO but no > PPC. This is really a 2003 time frame issue when 3GIO starts to roll out, > at that point Rocket IO will become very important. Stay tuned. > > > 4) On chip Flash RAM would be useful. An embedded PPC is going to require > some Flash. Also it would be nice if the serial Flash RAM were on chip, > I bet every one is sick of the extra part that most Xilinx designs > require. Flash requires a process that is usually two years behind the leading process. To do a flash capable FPGA would be to be obsolete on day 1 of the introduction. Not very exciting. > > 5) The IBM 405 chips include on board ethernet MACs, a PCI interface and > an SDRAM interface, a version of that chip that also incorporates an FPGA > and FLASH would be a good idea. In theory you could handle almost any > embedded application with just that one chip plus an SDRAM or two. MACs are soft cores to us. > > 6) This is a Virtex II issue, not just a Virtex II Pro issue. How about > offering versions of the Virtex II without the on board multipliers. The > multipliers make sense for DSP applications but they are a waste of money > and power for everything else. In my 12 years doing Xilinx designs I have > never needed a multiplier. I've frequently needed a CAM so I wouldn't > mind a few CAMs on board, but I'd rather have a cheaper part without the > multiplers. Well, they take up a tiny amount of area, so the cost savings is washed out completely by having to make two parts, with lower volumes in each.Article: 41646
Hand placement means you direct where the logic goes instead of allowing
the automatic placement to do it. Floorplanning the design can make
significant gains in performance, density and power consumption. We
have typically seen 50+% improvement in max clock rates as a result of
floorplanning (hand placing) a design. To do this, work hierarchically
and place what you can in the source so that you don't have to manually
place every instance in the floorplanner.
Jimmy Zhang wrote:
> Just keep hearing about this hand placement thing, don't know how it
> is done in reality. Does someone actually use their hands to do the
> placement as opposed to CAD based P&R. Any hints?
>
> --
> -----------------------------------------------------
> Click here for Free Video!!
> http://www.gohip.com/freevideo/
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 41647
Viewlogic used to be that. I haven't used anything newer than workview 7.5.
It is now innoveda, and I can't vouch for ease of use etc. In any event, the
workview was far superior to the foundation/aldec schematic package in every
respect.
Christopher Saunter wrote:
> Greetigns All,
>
> I have always found it more natural to work with schematics than an HDL
> (although learnign vhdl is proving very usefull in some areas...)
>
> I have used the Aldec schematic capture program from Xilinx Foundation 3/4
> and ECS from Webpack.
>
> Thus far, I am somewhat underwhelmed by these tools - I have always felt
> that a good tool (eg text editor, ide etc.) should allow you to work about
> as fast as you can enter data, and this is just not the case with the
> schematic capture tools I have used.
>
> So my question is: Does anyone know of a powerfull, flexible schematic
> editor with decent (preferably configurable) key bindings, rock like
> stability, a nice user interface, highly intuitive, that is fast and a
> pleasure to use etc?
>
> One that uses an HDL description of each schematic behind the scenes ECS
> style is probably a plus.
>
> Or should I just be gratefull I'm not directly entering netlists... ;-)
>
> Cheers,
> Chris Saunter
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 41648I am new come in the FPGA business. I guess that to implement a monostable multivibrator using a Xilinx FPGA should be pretty common. Maybe somebody provide me with a hint or an example? ThanksArticle: 41649
Kevin Brace wrote: > > I have gotten some personal attacks from a few die-hard Altera fans > because I made some negative comments about Altera's products. (About > the free tools available from Altera). Kevin, that's rubbish (unless you were getting private emails we don't know about). A few people, myself included, queried your assesment of Altera's free tools compared with Xilinx tools. Disagreeing and argueing a point isn't the same as a personal attack. I don't even know you. > Not everyone is professional in this newsgroup. Not everyone's got a very thick skin :-). I for one recognise your contribution to the newsgroup, especially with respect to PCI core implementations, I just didn't agree with what I considered to an unbalanced opinion. Nial.
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