Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
antipattern@hotmail.com (Unit Manager) wrote in message news:<e1f38cc5.0203290119.6aeecfb2@posting.google.com>... > Do you aware of any Virtex II pro development board on market? > You might want to contact your local NuHorizons rep and see if their Engineering Solutions Platform is what you are looking for. I haven't used it myself but just happened to hear about it a few days ago. Not clear that it supports the "Pro" part yet, but I don't see why it wouldn't. http://www.nuhorizons.com/EngineeringServices/esp/ESPBoard.html TomArticle: 41476
You can get some MAX7000 devices through RS components. Swedish distributor is (or at least was) RS componenst at Vallingby, Box 15, 15211 Vallingby, +46 8 445 8900. Here at Finland Arrows is a distributor. You should check Arrows at Sweden. -- Tuomo AuerArticle: 41477
I too got the same error when I was trying to simulate one of my design. I think you get this error when you are trying to simualte the design in a trial version of Modelsim. -praveenArticle: 41478
Given this is an fpga design, not abstract concepts, how do you want the data communicated? Do you want a serial list with an end-of-list flag that you can clock out one position at a time or do you need a parallel list all available at one clock with an attached item count? Are you running at 10MHz or 200MHz? A very easy method would be to shift the bits out one at a time and indicate that the address was or wasn't a one over the 32 locations. Only knowing what you need for an output can we (I) understand what you want to accomplish. If it's just homework then you have huge liberties in how to approach the task! xcvjb wrote: > There is a 32bit data in a register.how do i know the bit "1"'s position? > for example: > 01010000110011001101010001100010 > > the bit "1"'s position is : > 1/5/6/10/12/14/15/18/19/22/23/28/30. > how do implemention it with verilog code?Article: 41479
>Also I think >that the cable is dumb. A poor craftsman blames his toolsArticle: 41480
You might need a better ground to the parallel cable. There are two ground pins on the DLC-5 one for jtag and one for serial download. Try hooking the serial download gnd to your board also. SteveArticle: 41481
Kevin, The output enable register most likely got routed through the peripheral bus, hence the large delay. To avoid this, you will need to turn on single-pin output enable routing for this register. Regards, "Kevin Brace" <ihatespam99kevinbraceusenet@ihatespam99hotmail.com> a écrit dans le message de news: a81213$m3l$1@newsreader.mailgate.org... > Okay, here is a continuation of "Unrecognized LUTs Inserted in A > FLEX10KE/ACEX1K Design" posting I made. > I just did another P&R in Quartus II 2.0 Web Edition targeting > FLEX10K100E-1, and got very strange results for one of the pin's Tco. > The pin in question is Pin W9, and PCI's FRAME# signal is connected to > this pin. > > > > 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_L18; REG Node > = 'FRAME_n_OE_n~reg0' > > 2: + IC(6.700 ns) + CELL(3.500 ns) = 10.200 ns; Loc. = Pin_W9; PIN Node > = 'FRAME_n' > > > 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC8_L18; REG Node > = 'FRAME_n_Port~reg0' > > > 2: + IC(0.200 ns) + CELL(4.900 ns) = 5.100 ns; Loc. = Pin_W9; PIN Node = > 'FRAME_n' > > > > This FRAME_n pin is a bidirectional pin, so there is a tri-state > buffer before the pin. > Both FRAME_n_OE_n~reg0 (An Output Enable FF) and FRAME_n_Port~reg0 (An > output FF) are located in LAB L18 which is located right above pin W9. > Even though they are from the same LAB, the routing delay for > FRAME_n_Port~reg0 is 0.2ns, which is very good, but for some reason > FRAME_n_OE_n~reg0's routing delay is staggering 6.700 ns, which I don't > understand why can it be that bad considering the physical location of > the FF. > Did FLEX10KE somehow ran out of routing channels, and the routing for > FRAME_n_OE_n~reg0 got diverted? > Or is the automatic P&R tool that bad in QII? > I didn't use an IOE FF for FRAME_n_Port~reg0 because of FLEX10KE's IOE > doesn't seem to support asynchronous preset. > For synthesis, I used QII's native Verilog synthesis (Altera in-house > synthesis tool) instead of LeonardoSpectrum-Altera because I didn't feel > like using LS-Altera for this experiment. (I will try to use it later.) > > > > Thanks, > > > > Kevin Brace (In general, don't respond to me directly, and respond > within the newsgroup.)Article: 41482
Xilinx gurus, I tried all over the place, but can't find this myself. Where can I find information on performing design with both Verilog and VHDL modules? We are doing a design with VHDL, but have to utilize several existing Verilog modules. Can you please send me the links to the the appropriate documents. I'm using 4.1i software. Top level is VHDL, with different modules in Verilog. Thanks! Yen (yen@my-nemesis.com)Article: 41483
I'd tell you in private but your not willing to put out a real email address. Not only was that a snotty reply but you missed the point entirely. My guess is courtesy is proportional to intelligence. Steve <m0> wrote in message news:ee75e1c.5@WebX.sUN8CHnE... > >Also I think > >that the cable is dumb. > > A poor craftsman blames his toolsArticle: 41484
Hello all,
I'm trying to design a block to perform correlation
on two vectors: A and B. (A and B each have two elements:
A=(a1, a2) and B=(b1, b2)
The correlation between A and B shoul be calculated like
this:
corr = [(a1 * b1) + (a2 * b2)] / [sqrt(a1^2 + a2 ^2) * sqrt(b1^2 + b2^2)]
all a1,a2,b1,b2 are 16 bit wide and the result width needs to be 8 bits.
in the first look one can say it needs:
16 x 16 bit miltiplier x6
32 x 32 bit multiplier x1
32 bit square root block x2
32/32 bit divider x1
32 bit adder x3
I built a block like that with 16x16 bit multipliers from
Xilinx CoreGenerator but by far it exceeds the logic resources
that I have available for this block. ( because I need so many
of these blocks so the size of each block needs to be around
1000 - 1500 LUTs !)
So, any idea or trick for an efficient implementation?
I could not find a correlation Core in Xilinx's CoreGen IPs.
The latency is not important but it needs to produce 1 sample/clk.
Thanks,
-Max Edmand
Article: 41485looks like question got answered before my message made it on... c_oflynn@yahoo.com (Colin O'Flynn) wrote in message news:<a163b853.0203290655.70f396c9@posting.google.com>... > Hi, > > Also check that the computer's parallel port is okay! It could be > misconfigured, try the cable on a different computer. Also I think > that the cable is dumb. It doesn't have a micrcontroller on it, so the > software has no way of checking if the cable is working without being > connected to the target. > > -Colin > > "Tuomo Auer" <tuomo.auer@removethis.hut.fi> wrote in message news:<a81k8m$pnr$1@tron.sci.fi>... > > Power your home-build ByteBlaster using 5V or 3V3 power supply (not > > connected to computer or FPGA). Then feed to inputs (both computer side and > > FPGA side) GND and VCC and check with multimeter that the other side of > > 74HC244 responds properly. > > > > If possible, test also with genuine ByteBlasterMV that settings of your > > software are correct and test that you don't have a dead FPGA (they are > > static sensitive devices. Have separate ground wire connected between > > computer and FPGA-ground when using ByteBlaster).Article: 41486
Hello, Actually, I have a related question. In our design we are using an ARM CPU. My question is: Can we put an ARM in the virtex 2 pro? Were can I find/buy an ARM cpu core source (or precompiled) file to program in my FPGA? Regards, Cyrille "Muthu" <muthu_nano@yahoo.co.in> wrote in message news:28c66cd3.0203120612.6792156a@posting.google.com... > Hi, > > The virtex2pro having 2 inbuild powerpc 405. Is it mean that, for any > logic design the powerpc will be used to give the logic functionality? > or If we need POwerpc we can use it? > > What is the special about having inbuild powerpc? > > Thanks and Regards, > MuthuArticle: 41487
Minor help: A little algebra can help with the size: make the denominator sqrt( (a1^2+a2^2)*(b1^2+b2^2) ), reducing the resource count by one 32 bit square root block. If you only need 8 bits output, you can provide an answer with slightly greater error (1.5 LSbits instead of 0.51 LSbits) by limiting the size of the intermediate results in a structured error analysis. Perhaps someone has a squaring method that takes up fewer resources than a generic multiplier? Is the clock rate 200MHz or 20MHz? Are you using Virtex-II which has (did you know?) built-in multipliers available? Engineers calculate a value to 9 digits, use a micrometer measure, mark with chalk, and cut with an axe. Max Edmand wrote: > Hello all, > > I'm trying to design a block to perform correlation > on two vectors: A and B. (A and B each have two elements: > A=(a1, a2) and B=(b1, b2) > The correlation between A and B shoul be calculated like > this: > > corr = [(a1 * b1) + (a2 * b2)] / [sqrt(a1^2 + a2 ^2) * sqrt(b1^2 + b2^2)] > > all a1,a2,b1,b2 are 16 bit wide and the result width needs to be 8 bits. > in the first look one can say it needs: > 16 x 16 bit miltiplier x6 > 32 x 32 bit multiplier x1 > 32 bit square root block x2 > 32/32 bit divider x1 > 32 bit adder x3 > > I built a block like that with 16x16 bit multipliers from > Xilinx CoreGenerator but by far it exceeds the logic resources > that I have available for this block. ( because I need so many > of these blocks so the size of each block needs to be around > 1000 - 1500 LUTs !) > > So, any idea or trick for an efficient implementation? > I could not find a correlation Core in Xilinx's CoreGen IPs. > > The latency is not important but it needs to produce 1 sample/clk. > > Thanks, > -Max EdmandArticle: 41488
Sim or synth? Sim is in the manual for whichever sim you use. Mixed-language is usually an extra-cost option. Synth means - compile the Verilog modules to a set of EDIFs - instantiate the Verilog modules in the VHDL as 'black boxes' - compile the VHDL Then the Xilinx tools (ngdbuild) hook all the EDIF modules together. Just make sure the references in the top-level EDIF match the module names in the lower-level EDIF; for safety this should include case matching. Good luck. Romans @mindspring.com wrote in message > Xilinx gurus, > > I tried all over the place, but can't find this myself. Where can I find > information on performing design with both Verilog and VHDL modules? We are > doing a design with VHDL, but have to utilize several existing Verilog > modules. Can you please send me the links to the the appropriate documents. > > I'm using 4.1i software. Top level is VHDL, with different modules in > Verilog.Article: 41489
Thank you!i am glad to see your response.but i will tell you the whole thinking. when i find one bit "1" position,the position will be notified other module.In fact it is one port number.they will send a lot of data according the port.after finished,i will continue to look for next one bit "1" position. can you help me?Article: 41490
Hello,
I am a newbie to this field and I had a question regarding the term "PCI
Compliance" for FPGAs..
Suppose I were to have a PC104+ which has a PCI bus on it and I wanted to
connect an FPGA to the PCI bus. IF the FPGA documentation says that the FPGA
is PCI Compliant (~XC4028) then does it mean that-
- I can directly connect the FPGA I/O to the PCI bus without any additional
programming or synthesis or
- do I still have to implement a PCI Core in the FPGA in order to make it
talk to the PC104+ ??
Thanks
Anup
--
**************************************************************
ANUP B. KATAKE Office:
Graduate Student, 609-D, HRBB
Aerospace Engineering 3141-TAMU,
Texas A & M University. College Station, TX 77840
Tel: (979) 845-0720 (O) email: anup@tamu.edu
(979) 845-3288 (Visnav)
**************************************************************
I am! I can!! I will!!!
**************************************************************
Article: 41491"Cyrille de Brébisson" wrote: > In our design we are using an ARM CPU. My question is: > Can we put an ARM in the virtex 2 pro? > Were can I find/buy an ARM cpu core source (or precompiled) file to program > in my FPGA? > Cyrille, the answer to both your questions is: No. The PowerPC in Virtex-II Pro is a "hard" implementation, packing the microprocessor with its caches and MMU into the smallest possible silicon area, <4 square millimeters. What you seem to be looking for is a "soft" implementation, using the programmable logic "fabric". That solution is impractical for something as complex as PowerPC or even ARM. It would take up an unreasonable portion of a large chip, and achieve mediocre performance at best. Xilinx offers a soft microprocessor, called MicroBlaze, especially tuned for efficient implementation in the Virtex architecture. It is not as fast and capable as PowerPC, but uses only ~900 slices. "Half the size and twice the speed of NIOS" is the Xilinx slogan. Please, no flames... Peter Alfke, Xilinx ApplicationsArticle: 41492
Quicklogic has a new family called Eclipse that is antifuse and goes up to "500K" gates. They claim 600MHz internal clock frequency is possible. That sounds competitive at a glance anyway. Is anyone familiar with Eclipse? -- Pete Dudley Arroyo Grande Systems "Kevin Brace" <ihatespam99kevinbraceusenet@ihatespam99hotmail.com> wrote in message news:a814nl$mhd$1@newsreader.mailgate.org... > Peter Alfke wrote: > > > > > > We have looked at this several times. Here is my -somewhat personal- opinion: > > > > The standard CMOS process without any exotic additions ( like EEPROM or > > antifuse) is always better ( smaller, faster, higher-yielding, and earlier > > available) than a mixed process. We prefer the most aggressive > > microprocessor-oriented process. > > > > > Although, I don't know much about it, but it seemed like > anti-fuse FPGAs used to be more competitive in the '90s compared to > SRAM-based FPGAs, but now they seem to have gotten quite behind in terms > of performance or density. > Were the anti-fuse camp more competitive in terms of process technology > in the early to mid '90s? > Will MRAM or some other non-volatile storage technology replace > SRAM at some point because of soft error concern at some process > technology? (I do realize that MRAM is nowhere near being a high volume > commercial product like flash.) > > > > > The benefit of a EEPROM-based FPGA are really limited to very small designs, > > (where single-chip is seen as an advantage) and to certain high-security > > applications, which we already cover with triple-DES encrypted bitstreams. > > > > The market niche is small, and we prefer our present, very successful approach. > > > > Peter Alfke > > > Then how come CPLDs remain almost all EEPROM? > Also, why doesn't CPLD's density almost never seem to go above 512 or > 1,024 macrocells? (Except Cypress' Delta 39K which is SRAM-based.) > > > > > Kevin Brace (In general, don't respond to me directly, and respond > within the newsgroup.)Article: 41493
"tamu.edu" wrote: > Hello, > I am a newbie to this field and I had a question regarding the term "PCI > Compliance" for FPGAs.. > > Suppose I were to have a PC104+ which has a PCI bus on it and I wanted to > connect an FPGA to the PCI bus. IF the FPGA documentation says that the FPGA > is PCI Compliant (~XC4028) then does it mean that- > - I can directly connect the FPGA I/O to the PCI bus without any additional > programming or synthesis or No > > - do I still have to implement a PCI Core in the FPGA in order to make it > talk to the PC104+ ?? > Yes. PCI compliance only refers to the electrical parameters of the I/O (output drive, diode or not diode to Vcc, input capacitance, etc). You still have to implement the logic, or get the right core design, inside the chip. The PCI core is "soft", i.e. it uses the CLBs and interconnects of the FPGA. Note also that there is a substantial difference between 5V- and 3.3V PCI. The general rule is: try to keep the voltage as low as you can. 5V has less, if any, future... Peter Alfke, Xilinx ApplicationsArticle: 41494
Spam Hater wrote: > I see two problems here: > > "i am experienced HDL designer anyway" > > No, you're not. Sorry, but an experienced HDL designer has fought his > way through many pre-post synthesis mismatches. > > "I still don't know what problem the design was intended to solve" > > This is also a serious problem. If you don't know what it is to do, > how can you tell if it's doing it? > > And as to your last question: "how can I detect fatal bugs in my code" > the answer is: Knowledge, and experience. > and to gain K & E you need - in no particular order: - sweat - hours - coffee by regular tanker delivery - someone to bring in a regular supply of pizza - patience & determination - complete understanding of how your tool chain works *and* its limitations/bugs. - a full acceptance of just how dumb the errors you make can be - a gun to shoot yourself with when those errors become just too much to bear - never make assumptions, that's where most of the bite marks on my ass come from. finally Never be surprised when the idea that you can just "push the big green GO button" fails dismally.Article: 41495
The man speaks from experience. "All true knowledge comes from direct experience" - Mao On Sat, 30 Mar 2002 09:48:02 +0000, Rick Filipkiewicz <rick@algor.co.uk> wrote: > > >Spam Hater wrote: > >> I see two problems here: >> >> "i am experienced HDL designer anyway" >> >> No, you're not. Sorry, but an experienced HDL designer has fought his >> way through many pre-post synthesis mismatches. >> >> "I still don't know what problem the design was intended to solve" >> >> This is also a serious problem. If you don't know what it is to do, >> how can you tell if it's doing it? >> >> And as to your last question: "how can I detect fatal bugs in my code" >> the answer is: Knowledge, and experience. >> > >and to gain K & E you need - in no particular order: > >- sweat >- hours >- coffee by regular tanker delivery >- someone to bring in a regular supply of pizza >- patience & determination >- complete understanding of how your tool chain works *and* its >limitations/bugs. >- a full acceptance of just how dumb the errors you make can be >- a gun to shoot yourself with when those errors become just too much to bear >- never make assumptions, that's where most of the bite marks on my ass come >from. > >finally > >Never be surprised when the idea that you can just "push the big green GO >button" fails dismally. > > >Article: 41496
In article <a82m6n$lvj$1@web1.cup.hp.com>, cyrille_de-brebisson@hp.com says... > Hello, > > Actually, I have a related question. > In our design we are using an ARM CPU. My question is: > Can we put an ARM in the virtex 2 pro? > Were can I find/buy an ARM cpu core source (or precompiled) file to program > in my FPGA? In the interest of full disclosure... Xilinx doesn't do ARM, but Altera has an ARM hard core in their Excalibur series. I don't know anything more than what is on their web site though. Xilinx chose the right processor. ;-) ---- Keith IBM PowerPC Development (but nothing to do with Xilinx/IBM alliance)Article: 41497
Again, like what Peter said, "PCI Compliant" only means that the FPGA is
electrically compatible with PCI (I don't know much about analog stuff,
but things like current drive capability, pin capacitance, etc.).
Most FPGAs sold are basically empty boxes, except for a few like
Quicklogic's QuickPCI FPGA which already contains a PCI interface in it.
Quicklogic's QuickPCI is an anti-fuse FPGA, so you can only burn the
chip once, but I guess in a university environment, that's not
desirable.
So, to connect your custom logic to PCI bus, you will have to 1)
license a PCI IP core from someone like Xilinx, Altera, or another third
party IP core vendor, 2) use a PCI to local bus bridges from PLX or
AMCC, 3) download a free PCI IP core from Opencore.org
(http://www.opencores.org/projects/pci/), or 4) develop your own PCI IP
core.
If you are going with 1), you might be able license a PCI IP core from
Xilinx or Altera at a university discount rate, but typically, free
tools (Xilinx ISE WebPACK 4.1 or Quartus II 2.0 Web Edition) don't
support IP cores from the device vendors, so you may have to shell out a
some more money to obtain design tools.
If you are going with 2), you can attach an FPGA to the backend of the
PCI bridge chip, and you won't have to worry about PCI bus protocol or
PCI's unforgiving setup time (Tsu < 7ns for 33MHz PCI).
If you are going with 3), the PCI IP core is free, and the authors seem
to have gotten Tsu < 7ns, but the code seems to be pretty hard to
comprehend (That's my biased opinion because it is always hard to
understand someone else's code.), so if the PCI IP core is buggy, likely
the original authors will be the only ones who can help you.
In my case, I went with 4), and if you have the time, and willing to
learn HDL, PCI bus protocol, and the internal architecture of an FPGA,
it is possible to develop your own PCI IP core.
I used free Xilinx ISE WebPACK for the development, simulated with
ModelSim XE-Starter (Comes with ISE WebPACK, and it is also free.), and
did some primary testing with Insight Electronics Spartan-II PCI
Development Kit
(http://208.129.228.206/solutions/kits/xilinx/spartan-iipci.html).
If you are only going to buy the hardware (not licensing Xilinx LogiCORE
PCI), the PCI card alone costs only $145, and even with two more option
boards, a parallel port JTAG cable, and ground shipping, the whole thing
cost me only $370, but someone said recently that Insight Electronics
discontinued the kit, but I haven't verified that.
I know the Insight Electronics Spartan-II PCI card is a regular PCI
card, and not PC104+, but I guess you can debug your design with the
regular PCI card, and then find a PC104+ that has Spartan-II or develop
your own PCB.
I don't know if PC104+ is has 5V PCI or 3.3V PCI, but if it is
5V PCI, you should use a fairly new FPGA like Virtex/Spartan-II rather
than older ones (XC4000 series) for Xilinx, or APEX20K/FLEX10KE/ACEX1K
for Altera.
However, those are the last FPGAs that support 5V PCI, so if you want to
use newer FPGAs, you will have to use 3.3V PCI which is not too popular
(Almost all desktop computers have only 5V PCI slots.), but that might
not be an issue in an embedded environment like what you are in.
In general, I will say that Xilinx FPGAs are more PCI friendly than
Altera FPGAs, but to some extent that's a biased opinion because I have
more experience dealing with a Xilinx FPGA (Spartan-II) than an Altera
FPGA (FLEX10KE).
I am saying it is not impossible to do PCI in Altera FPGAs, but it will
probably be harder than Xilinx FPGAs.
Kevin Brace (In general, don't respond to me directly, and respond
within the newsgroup.)
"tamu.edu" wrote:
>
> Hello,
> I am a newbie to this field and I had a question regarding the term "PCI
> Compliance" for FPGAs..
>
> Suppose I were to have a PC104+ which has a PCI bus on it and I wanted to
> connect an FPGA to the PCI bus. IF the FPGA documentation says that the FPGA
> is PCI Compliant (~XC4028) then does it mean that-
> - I can directly connect the FPGA I/O to the PCI bus without any additional
> programming or synthesis or
> - do I still have to implement a PCI Core in the FPGA in order to make it
> talk to the PC104+ ??
>
> Thanks
> Anup
>
> --
> **************************************************************
> ANUP B. KATAKE Office:
> Graduate Student, 609-D, HRBB
> Aerospace Engineering 3141-TAMU,
> Texas A & M University. College Station, TX 77840
>
> Tel: (979) 845-0720 (O) email: anup@tamu.edu
> (979) 845-3288 (Visnav)
> **************************************************************
> I am! I can!! I will!!!
> **************************************************************
Article: 41498I read an article a few months ago about a startup developing yet another ARM clone (PicoTurbo exited the ARM clone business.). http://www.eetimes.com/story/OEG20020124S0111 What is the purpose of putting an ARM or its clone core into a Virtex-II Pro? Is it for an ASIC prototype? Kevin Brace (In general, don't respond to me directly, and respond within the newsgroup.) "Cyrille de Brébisson" wrote: > > Hello, > > Actually, I have a related question. > In our design we are using an ARM CPU. My question is: > Can we put an ARM in the virtex 2 pro? > Were can I find/buy an ARM cpu core source (or precompiled) file to program > in my FPGA? > > Regards, Cyrille >Article: 41499
Yves Petinot wrote:
> does any of you know where to find a C-library handling the compilation from
> VHDL to the bitstream format ? Any target FPGA will do ...
That will be quite a C library.
Synthesis, Place and Route, and bitstream conversion.
Might as well throw in simulation as well:)
-- Mike Treseler
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z