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Martin, Do you mean SpartanII(E) vs Virtex-E? There is really no such part as a VirtexII(E). If so I think they are exactly the same die. The SpartanII(E) is just marketed to be cheap as possible. I think they accomplish that through the types of packages offered. -- Pete Dudley Arroyo Grande Systems "Martin Sauer" <msauer@gmx.net> wrote in message news:3C904A7E.5010304@gmx.net... > Hi, > > can you tell me the difference between the Xilinix Virtex-II and the > Virtex-E Series? > Thanks for your answer. > > bye > > martin > >Article: 40901
I would think about doing the star routing with a source termination resistor for each leg of the star, may 20 Ohms each. Make all the legs the same length and make sure there are no breaks in the ground return under these legs. -- Pete Dudley Arroyo Grande Systems "rickman" <spamgoeshere4@yahoo.com> wrote in message news:3C923297.57531263@yahoo.com... > I need to plan a high speed bus that will connect 5 devices. They will > all be very closely spaced so that the lengths of the routes can be kept > pretty short. The clock line is the one I am most concerned about. It > is 100 MHz ECLKOUT from a TI C6711 DSP. The five devices are an SBSRAM, > two SDRAMs (16 bits each for 32 bit memory) and an XC2S200E. > > The longest as-the-crow-flys run is 1.4" with 1 inch x and 1 inch y if > you keep it square (as layout guys like to do). The other signals are > within the box these two points inscribe. > > Another approach would be to daisy chain them which would make the total > run about 3 inches. What type of termination could I expect to work > well with this type of run? > > With such short runs, I was thinking about using no termination with a > star topology. I am not even sure I need to worry about keeping the net > delays equal since the variation will be less than +- 1 inch or about > 100 pS of clock skew. > > Anyone have much experience with running high speed clocks on such short > runs? Can I expect this to work well? > > I know Austin will tell me to simulate it, which I plan to do. I am > just trying to get a "gut" feeling as Bob Pease would want to do. You > know how easy it is to get the WRONG, right answer from a computer. > GIGO. > > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAX >Article: 40902
"Pete Dudley" wrote: > Do you mean SpartanII(E) vs Virtex-E? There is really no such part as a > VirtexII(E). > > If so I think they are exactly the same die. The SpartanII(E) is just > marketed to be cheap as possible. I think they accomplish that through the > types of packages offered. Any '2SxE is most assuredly a different die from its brethren 'VxE, since the '2SxE lamentably provides only half the block RAM. Jan Gray, Gray Research LLCArticle: 40903
> > Pete, where are you getting all these rules (and "thought"s ;-) from? I, > > obviously, don't have the same updated resources you do on writing style, > > and I'd like to update my resources...so if you wouldn't mind revealing > > yours, I'd appreciate it. > > > Frank Vorstenbosch already mentioned: > > --My "Webster's Standard American Style Manual" has this to say: > > --In typewritten material, two spaces follow a period that ends a > --sentence. If the period is followed by a closing bracket, closing > --parenthesis, or quotation marks, the two spaces follow the second > --mark. In typeset material, only one space follows this period. > > I just checked with a technical writer friend who agrees, and > says that both the Microsoft Style Manual and AP Style Manual > concur. Unfortunately, I couldn't find either on line, so I can't > quote the text. Hi Pete, I believe we're kind of talking about two different things. The Internet, specifically news groups and mail programs, are not the same as publications. With a publication, you can specify the font the publication is being published in, and because it's printed...well, the font is what the publication will be viewed in. For text only based news, and email, I specify the font I want to view it in, as you or anyone else does. Since no one knows whether the font the viewer uses is going to be fixed or proportional...which "rule" applies? I know for me, news group posts are MUCH clearer to read with two spaces after the period, but it certainly isn't really that important. But...the posts are CERTAINLY easier to read when people use capital letters to start off sentences, and capitalize "I". If the purpose of this medium IS communication, wouldn't clarity and ease of communication be of paramount importance? Of course people who don't communicate in English "well" don't have to get it perfect...I am referring to people who do have a command of the English language, and one would assume the "correct" use of writing it too. Two or one space is nitpicking in my book, but I don't believe capitalization is. I think "proper" capitalization is common courtesy. Austin P.S. BTW, I wanted to know YOUR source ;-)Article: 40904
Jan Gray wrote: > > "Pete Dudley" wrote: > > Do you mean SpartanII(E) vs Virtex-E? There is really no such part as a > > VirtexII(E). > > > > If so I think they are exactly the same die. The SpartanII(E) is just > > marketed to be cheap as possible. I think they accomplish that through the > > types of packages offered. > > Any '2SxE is most assuredly a different die from its brethren 'VxE, since > the '2SxE lamentably provides only half the block RAM. > > Jan Gray, Gray Research LLC And the S2E has extra IOs as well. I would have loved it if they had made the V2E and the S2E pin compatible. Then I could offer a low cost version of our boards as well as a high performance version. But that was not to be since they even moved the power and ground pins :( -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 40905
Hi, Gurus:
I want to know what's the problem with this module? I want to make use of
the ROC inside an Spartan-II
FPGA chip.
The error was Analyzing top module <roc>.
ERROR:Xst:899 - "roc.v", line 21: The logic for <count> does not match a
known FF or Latch template.
module example(clk, rst, count, clk_2xo);
input clk;
input rst;
output [3:0] count;
output clk_2xo;
wire rst;
wire clk_buf;
reg [3:0] count;
wire rst_i;
BUFG GBUF_FOR_MUX_CLOCK( .O(clk_buf), .I(clk));
// BUFG GBUF_RST( .O(rst_i), .I(rst));
ROCBUF rocbuf( .I( rst ), .O( rst_i ) );
always @ (posedge clk_buf or posedge rst_i)
begin
if (rst == 1'b1)
count <= 4'h0;
else
count <= count + 4'h1;
end
// IBUFG CLK_ibufg( .I( clk ), .O( clk_ibufg ) );
BUFG CLK_bufg( .I( clk_2xi ), .O( clk_2xo ) );
CLKDLL CLK_2X_O( .CLKIN( clk ),
.CLKFB( clk_2xo ),
.RST( rst_i ),
.CLK2X( clk_2xi ),
.CLK0( ), .CLK90( ), .CLK180( ), .CLK270( ),
.CLKDIV( ),
.LOCKED( )
);
endmodule
module ROCBUF( I, O );
input I;
output O;
endmodule
Article: 40906Hi, I m using a Virtex II 1M gate device. My questions are: 1. What is the best way to generate the reset signal for internal logic? Presently I m ORing the external reset signal with the LOCKED signals of the 5 DCMs. But this approach gives problem in POST ROUTE simulation, although it works fine in real hardware. 2. Can I use the BUFGMUX for this internal RESET signal, so that it will use the GLOBAL ROUTING? Note: The internal RESET Signal is synchronous RESET, so it should not violate the setup timings of the sequential logic.Article: 40907
Hi Kelvin, first tell me which is this "other chip", is it an FPGA? if so then u can delay your reset signal there itself for 64 Cycles and then take that delayed signal to the current chip, then it will use the BUFGMUX. try and see if this works.. Regards -AmarArticle: 40908
Hello, can you tell me which FPGA is better Xilinx Virtex II or Altera Apex 20KC? I want to use an FPGA in a fastprototyping enviroment with an LVDS interface. Can I use both FPGAs or there is one better? Thank you for your answer. bye martin sauerArticle: 40909
OR <br> If this is not possible, then u can run a counter in this FPGA itself. that will use 7 registers. and this counter will be triggered on the reset from the parent chip. and the MSB of the counter (i.e. 7th bit, rst_cntr[6] if its a rst_cntr[6:0] counter) can be fed to the input of BUFGMUX instantiation and port map the output of this instantiation to the Internal reset(Which is 64 Cycles delayed) of your FPGA. This will definitely work. <br><br> -AmarArticle: 40910
And remember,<br> you will have run a seperate 7 bit counter to deassert this delayed RESET signal... :-)<br> If you need further clarification, feel free to contact me. <br>Note: The BUFGMUX specified in the previous discussion is nothing but the BUFG with two inputs, you can also instantiate BUFG for the same<br><br> -AmarArticle: 40911
I am trying to simulate two designs and compare the waveforms.
Is there a way to do such a thing?
So far, I tried running two instances of ModelSim XE-Starter 5.5b, but
it won't let me run more than one instance of the program.
Actually, comparing the current waveform result with an already
simulated one saved to a file is adequate, but I have not been
successful doing that.
Thanks,
Kevin Brace (In general, don't respond to me directly, and respond
within the newsgroup.)
Article: 40912On 17 Mar 2002 20:33:53 GMT, vhdlcohen@aol.com (VhdlCohen) wrote: >Have you read Cooley's article? >http://www.eedesign.com/columns/industry_gadfly/OEG20020311S0058 > >For Synplicity's complete response see: >www.synplicity.com/synplicity_responds.html > >Would be interested in hearing your comments. I am not a very experienced ASIC designer but I am pretty sure clock tree synthesis, signal integrity, electromigration are not features one expects from a synthesis tool. These are usually handled at the back-end. Last I looked no one had a working RTL to GDS2 tool yet even though that's the holy grail of EDA. One very nice thing about synplify asic is that it gets good results extremely quickly. Muzaffer Kal http://www.dspia.com ASIC/FPGA design/verification consulting specializing in DSP algorithm implementationsArticle: 40913
On Mon, 18 Mar 2002 14:49:27 +0800, "Kelvin Hsu" <qijun@okigrp.com.sg> wrote: >The error was Analyzing top module <roc>. >ERROR:Xst:899 - "roc.v", line 21: The logic for <count> does not match a >known FF or Latch template. ... > >always @ (posedge clk_buf or posedge rst_i) >begin >if (rst == 1'b1) ... If this is exactly what you tried, the problem is with "posedge rst_i" and "if rst == 1'b1". The identifier after posedge doesn't match the reset condition in the first if. Muzaffer Kal http://www.dspia.com ASIC/FPGA design/verification consulting specializing in DSP algorithm implementationsArticle: 40914
On Mon, 18 Mar 2002 01:47:13 -0600, Kevin Brace <ihatespam99kevinbraceusenet@ihatespam99hotmail.com> wrote: > I am trying to simulate two designs and compare the waveforms. >Is there a way to do such a thing? >So far, I tried running two instances of ModelSim XE-Starter 5.5b, but >it won't let me run more than one instance of the program. You don't need to run two instances. Just instantiate both designs in a test bench and xor the outputs. Muzaffer Kal http://www.dspia.com ASIC/FPGA design/verification consulting specializing in DSP algorithm implementationsArticle: 40915
1)Is there a very clear example how to functionally simulate a Core with Ise 4.1 and ModelSIm (xilinx edition) with VHDL? 2)Is not clear to me which are the files involved and the flow to follow. Moreover: 3)Do I need to generate a testbench file? do I need to modify it? The answer 11742 and 9329 were not very helpful, in particular they do not match with files from the core generator GiuseppeArticle: 40916
My 2c worth... If anyone here uses LaTeX, you would know that it does not even allow you to type two spaces after a period. Since LaTeX is the generally accepted document format for scientific journals (IEEE, I don't know, but certainly the Astrophysical Journals and Astronomy Journals), I would think this pretty much sums up this argument. adrian VhdlCohen <vhdlcohen@aol.com> wrote in message news:20020317164614.15262.00001512@mb-mh.aol.com... > >--My "Webster's Standard American Style Manual" has this to say: > > > >--In typewritten material, two spaces follow a period that ends a > >--sentence. If the period is followed by a closing bracket, closing > >--parenthesis, or quotation marks, the two spaces follow the second > >--mark. In typeset material, only one space follows this period. > > > >I just checked with a technical writer friend who agrees, and > >says that both the Microsoft Style Manual and AP Style Manual > >concur. Unfortunately, I couldn't find either on line, so I can't > >quote the text. > > > > When looking at the VHDL LRM, it looks like there are two spaces after a > period. > Whether there are 2 characters spaces in the original text is hard to tell, but > visually, on printed text, it looks like 2 spaces. The IEEE reviews all specs > before publications. > Ben > --------------------------------------------------------------------------Article: 40917
> Maybe I am not up to date with elementary school methods, but isn't > "creative spelling" simply a stepping stone to "proper" spelling? > I believe that it parallel to allowing an infant to speak baby talk rather > than correcting them and making them speak the "King's" grammer from the > cradle. As long as it is straighten out by the time they need to > communicate in writing where is the harm? That would be grammar, not grammer. The term would also be Queen's english. As for proper spelling and grammar... :) adrian > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAXArticle: 40918
> > Out of curiosity, and not meaning to sound crass (me, no) but don't they > > teach the use of capital letters, two spaces after a period, and a line > > break between paragraphs in school these days? > > Only in US schools, I believe. Here, it is one space and no line > break. And just about everywhere else. Again, the use of LaTeX enforces an indentation for paragraphs. adrianArticle: 40919
William Meyer <wmhmeyer@earthlink.net> writes: > In article <3C94E4F4.6102DBD7@ieee.org>, cshappee@ieee.org says... > > I was taught in typing class that two spaces after a period was required. > > Many years ago, when we first gained access to proportional spacing, and > when software manuals still taught usage, rather than being only > reference manuals, I learned that only one space should be used. Some > page layout programs enforce this rule, preventing the entry of multiple > spaces from the keyboard. FrameMaker (optional, though) Anyway, two spaces after a period seems to be a US pecularity. So, please, can we accept both in these INTERNATIONAL fora? Homann -- Magnus Homann, M.Sc. CS & E d0asta@dtek.chalmers.seArticle: 40920
Got two questions from a beginner here 1. What is the binary format of the bit stream one downloads to the FPGA that controls the place and route? 2. How much effort is needed for me to bypass FPGA vendor's software and write my own FSM machine into the binary format as in the previous question? ThanksArticle: 40921
Muzaffer Kal wrote: > On Mon, 18 Mar 2002 01:47:13 -0600, Kevin Brace > <ihatespam99kevinbraceusenet@ihatespam99hotmail.com> wrote: > > > I am trying to simulate two designs and compare the waveforms. > >Is there a way to do such a thing? > >So far, I tried running two instances of ModelSim XE-Starter 5.5b, but > >it won't let me run more than one instance of the program. > > You don't need to run two instances. Just instantiate both designs in > a test bench and xor the outputs. Or just call the testbench twice in a much higher block "dummy": module dummy (); testbench tb_a (); testbench tb_b (); endmodule But simulation will be twice slower, so why not running each of them separately and then post-processing testvectors later on? UtkuArticle: 40922
Muzaffer Kal wrote: > On 17 Mar 2002 20:33:53 GMT, vhdlcohen@aol.com (VhdlCohen) wrote: > > >Have you read Cooley's article? > >http://www.eedesign.com/columns/industry_gadfly/OEG20020311S0058 > > > >For Synplicity's complete response see: > >www.synplicity.com/synplicity_responds.html > > > >Would be interested in hearing your comments. > > I am not a very experienced ASIC designer but I am pretty sure clock > tree synthesis, signal integrity, electromigration are not features > one expects from a synthesis tool. These are usually handled at the > back-end. Last I looked no one had a working RTL to GDS2 tool yet even > though that's the holy grail of EDA. One very nice thing about > synplify asic is that it gets good results extremely quickly. > > Muzaffer Kal > > http://www.dspia.com > ASIC/FPGA design/verification consulting specializing in DSP algorithm implementations Maybe the fear is that if Synplify-ASIC works as advertised, or close to it, then the rationale for the whole "Kremlin watching" ESNUG industry disappears down the Swanee, along with a lot of people's raisons d'etre - aka their jobs. Imagine how cool life would get if `It's not a bug its a feature' were reversed.Article: 40923
Jimmy Zhang wrote: > Got two questions from a beginner here > > 1. What is the binary format of the bit stream one downloads to the FPGA > that > controls the place and route? > Its usually proprietary. Xilinx's certainly is although there is a tool that can be used to modify it directly. > > 2. How much effort is needed for me to bypass FPGA vendor's software and > write my own FSM machine into the binary format as in the previous question? > > Thanks Several million $s of VC funding. But you would be onto a winner if you could figure it. Xilinx bought NeoCAD, the last company to try it. Unfortunately since those XC3/4K days the devices have become much more complex.Article: 40924
Jimmy Zhang wrote: > Got two questions from a beginner here > > 1. What is the binary format of the bit stream one downloads to the FPGA > that > controls the place and route? > > 2. How much effort is needed for me to bypass FPGA vendor's software and > write my own FSM machine into the binary format as in the previous > question? Do you want to do your own statemachine synthesis (i.e. bypassing VHDL/Verilog synthesis) or do you want to really implement your statemachine (bypassing backend place & route tools, e.g. Xilinx PAR) In the case that you want to bypass VHDL/Verilog synthesis, you can write an application that directly writes EDIF or XNF files. In the case that you want complete control over placement and routing and if you are using Xilinx Virtex or Spartan-2 devices, you can get a set of Java classes called JBits that allows direct manipulation of bitstreams. Mail to jbits@xilinx.com . The exact format of the bitstream is only partially known to public and seems to be a good keeped secred of Xilinx. However, the format for the configuration bits that control LUTs, BlockRAMs and IOBs is available as application note from Xilinx, XAPP 151. Regards, Chris
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