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if anyone would tell me how to set in Outlook ExpressArticle: 40726
Hi, can you tell me the difference between the Xilinix Virtex-II and the Virtex-E Series? Thanks for your answer. bye martinArticle: 40727
I see from your description, that you use phase shifts to sample the differences between the different toggling signals. I hadn't considered the "combination" of these elements. Thank you very much for sharing your ideas! John_H wrote: > ______ ______ ______ > clk10x _/ \______/ \______/ > __ _____________ _____________ _____ > toggle __X_____________X_____________X_____ > _ _ _ _ _ _ _ _ _ > clk35x_shift _/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_ > ______ _______________ ___________ __ > togp ______X_______________X___________X__ > ________ ___________ _______________ > togn ________X___________X_______________X > _ _ _ > tog_diff ______/ \___________/ \___________/ \ > ___ > samplep ______________________/ \__________ > ___ > samplen ________/ \_______________________/ > _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ > ddr_data X6X0X1X2X3X4X5X6X0X1X2X3X4X5X6X0X1X2X > > You're right about the toggle period. > Though it's tough to show prop delays (the combinatorial tog_diff doesn't show a delay in > the diagram) it seems that the pulse that covers timeslot 3 and 4 in this phase shift > version of clk35x is independent of which clk35x transition you use to sample the > difference. You can apply the same timing diagram to the clk10x90deg signal with an > unshifted clk35x and get similar results but the timing analysis is up to you. Fun stuff! > > Mark wrote: > > > I think that with the toggling signals, they have a period of twice the clock period. > > It seems when using clk35x_p and clk35x_n, toggle35x_p and toggle35x_n can only resolve > > down to one clk35x resolution. The 90 degree phase shift sounds like one way to find a > > difference. I believe that I once saw an appnote that described using 90 deg phases to > > lock(?) onto an input signal. > > > > Now that you mention it, I do remember reading messages about clock skew and jitter in > > FPGAs. Also, several weeks ago, I looked into the Virtex-II skew/jitter when > > multiplying up the clock by 7x to the rate of 420 MHz.Article: 40728
Hello all, I use a BUFGDLL in a Virtex-E FPGA to succeed a proper distribution of a clock (155MHz). I instantiate BUFGDLL in my code and I did the port map. In this way I have not access to the RST pin of the DLL (I want to set it '0' as xilinx suggests). I checked that DLL's CLKIN,CLKFB and CLK0 pins are OK but I cant check if the RST pin is '0' by default. How can I check if the RST pin is grounded or not? Best Regards, HarrisArticle: 40729
Hi all, on the Xilinx documentation I do find, that the bitstream format has a minimum of 8 '1' at the very beginning of the serial bitstream. Is it possible to extend the minimum 8 of '1' to any higher number before the start-pattern is being applied? markusArticle: 40730
Is the difference between the buffers LVDCI_DV2_18 and LVCMOS18 only in the internal pair 2R resistors ? HaimArticle: 40731
Hi. I want to use virtex2 DCM as a delay line on a clock signal. This means that I want to disable any loop to prevent any added jitter to the clock. I need only specified delay in the 50 ps steps. How can it be done ? ThankX , Nahum.Article: 40732
Hello, one question: Is it possible to connect a 5V IO Device direct to the Xilinx Virtex FPGA series? Thanks for your answer. bye martin sauerArticle: 40733
Thanks for your answer in advance!Article: 40734
RSM wrote: > Thanks for your answer in advance! www.fpgacpu.org (excellent starting point!) www.gaisler.com (LEON CPU) www.opencores.org regards, chrisArticle: 40735
hmmmmmmmm, quite strange! It can explain why I could not find any useful benchmark on the web for the recent verstions of these tools.... But the question remains, and it's that if there is no benchmark comparision, how would one choose one tool over another one? Just looking at the feature list and vendor claims does not look like the best way... A year ago, I used one of my big DSP designs as benchmark for these tools and at that time Synplify outperformed both Leonardo and FPGA compiler for a Flex10K target. But today? Who knows how these tools compete against each other? Should I try to downlaod the trial version of the tools, and run all of them on my latest designs to choose one? For each new design? :) I don't think so... Regards Arash "S. Ramirez" <sramirez@cfl.rr.com> wrote in message news:H3Rj8.118337$Dl4.13204394@typhoon.tampabay.rr.com... > "Arash Salarian" <arash.salarian@epfl.ch> wrote in message > news:3c8f4cb7$1@epflnews.epfl.ch... > > Hello, > > > > Do you know of any recent review/benchmark comparision of major synthesis > > tools for the FPGA? I'm interested in such a comparision between Synplify, > > LeonardoSpectrum and FPGA compiler. And is there any major perfromance > > difference between these tools when targetting different FPGAs from Xilinx > > and Altera? > > > > Best Regards > > Arash > > You will be hard pressed to find these comparisons, since the license > agreements of these vendors say something close to "Licensee shall not .. > disclose the results of any benchmarking of the SOFTWARE, or use such > results for its own competing software development activities, without the > prior written permission of Blah Blah." > Don't blame me, I'm just the messenger! > Simon Ramirez, Consultant > Synchronous Design, Inc. > Oviedo, FL USA > >Article: 40736
S. Ramirez wrote > You will be hard pressed to find these comparisons, since the license > agreements of these vendors say something close to "Licensee shall not .. > disclose the results of any benchmarking of the SOFTWARE, or use such > results for its own competing software development activities, without the > prior written permission of Blah Blah." You could fall back on the legal principle that "common abuse is not actionable". From what we hear about some of the tools, common abuse would be a fair summary :-)Article: 40737
Hi all,
For a class (calmer down.. I'm not looking for answers to my homework)
I've designed an 8-bit CPU. Fifteen instructions, pre-fetching, branch
predicting, load-store, etc. etc. So far, it cruises along at ~50MHz on an
XC4010XL-3. This is better than what's necessary for the class, but I'd
like to push it further.
Now that I have a ballpark speed, what's the best way to get started
specifying constraints in a .ucf? How do I get the (old, old, old)
Foundation 3.1 software in the labs to tell me what the worst paths are, so
that I can start picking out false paths, etc.
Incidentally, the post-layout timing report gives a figure of ~20MHz fo
the maximum clock speed, but on the board, I'm well over 45.. is this
typical? How can I get more accurate numbers out of the reports?
Thanks for your attention
JoshP
Article: 40738Timmestein wrote: [snip] > Kelvin Hsu wrote: > [snip] or maybe you didn't bother setting permissions properly on your files and a simple cp/scp worked just fine. get a book on *nix operating systems, and then one about posting to relevant groups in usenet. edicArticle: 40739
Arash Salarian wrote:
> Should I try to downlaod the trial version of the tools, and run all of them
> on my latest designs to choose one?
That would answer the question for you.
I'm not sure the difference between the
two products is worth spending much time over.
Consider other factors like existing licenses,
local experts etc.
-- Mike Treseler
Article: 40740Hello, We are trying to decide on boards for use in a course in the Electrical Engg. department at our university. The requirements we have come up with so far are as follows: 1. Easy to get started and working with it. 2. Relatively inexpensive 3. Can be used to implement reasonably large designs, especially DSP filters, FFTs etc. Here we would like to implement the designs without having to go to too much low- level optimization (bit-serial implementations etc.) unless absolutely necessary, as this would change the focus from learning about FPGA implementation to low-level design. 4. Can be used with existing tools (we have Synopsys DC and FPGA compiler II, so we would prefer not to have to purchase Foundation etc. unless necessary) It seems that the Xilinx Spartan chips can be used with the Webpack which is free, and they also have very large capacities (100k-200k for XC2S200). Two boards I have found so far with these are 1. XESS XSA-100 (100k gate, $279) from xess.com 2. Digilab XLA 2 (XC2S200 Spartan II - 200k gates, $99) from digilentinc.com The digilent board seems to have better features at a lower price, but XESS appears more popular overall. Are there any other compelling reasons for using one or the other? Alternately, are there any other boards that are especially suited to classroom use? Apart from basic use in a classroom setting, we are also interested in boards that can be used for rapid reconfiguration etc., for use in research into reconfigurable computing techniques. Any replies much appreciated. Thank you, NitinArticle: 40741
Martin, Sure. As a member of the design, and the verification team for Virtex II (and II-Pro), I think I can answer pretty fairly. Virtex E was a shrink to 0.18u of the classic Virtex architecture and circuitry. Virtex E added LVDS input buffers to the original Virtex design, but little else was changed. Virtex II was a complete redesign in 0.15u at 1.5V for the core, that extended the reach of the interconnect, and buffered virtually all paths to reduce loading effects. The CLB had more features added (more LUT RAM modes, SRL modes), as well as the horizontal carry (useful for p-terms). The block RAMS got bigger, and there are more of them (4K vs 18K), as well as having three read/write modes instead of one in addition to a 18X18 multiplier in each BRAM block. The global clock skew was reduced from ~ 300 ps in Virtex E to less than 120 ps in Virtex II (largest parts). The DLL got two new friends, a digital phase shifter (1/256 resolution of a period) for variable or fixed phase shifting, and a digital frequency synthesizer for M/D frequency sythesis. The IOBs got current sink/source differential LVDS outputs, and they have digital controlled impedance for precise 50 ohm (or 25 to 100 ohm) t-line matching. The IOBs also got a full set of hardware to support double data rate (DDR) clock forwarded interfacing. Oh, and I almsot forgot, there is key storage for 6 keys, and it supports Triple DES for encrypted bitstreams to protect your IP. All of these features support the myriad of RAM interfaces, and other wide and fast parallel IO. The software got twice as fast, and many more powerful features were added to make designs easier. The new power and speed of Virtex II allows for many ASIC like cores and functions that just can't run on anything less powerful, or slower. The bottom line for Virtex II is that we see it in all cell base station designs, in data communications systems, routers, switches, enterprise storage systems, video processing .... and many many more. The family is extended by the introduction last week of the Virtex II Pro family members, which included IBM Power PC uP's (yes, that is plural as in more than one on the larger family members), and Rocket IO(tm) gigabit serial transceivers (up to 3.125 Gbs each). The smallest family member is the 2V40, with 40K "fpga" gates (e.g. 512 LUT's), that is about 30X more powerful than a clock distribution chip, and is actually less expensive, too. From there, you have the 2v80, 2v250, 2v500, 2v1000, .... up to the 2v6000, and later this year, the 2v8000. Check out the documentation: http://www.xilinx.com/products/platform/ Austin Martin Sauer wrote: > Hi, > > can you tell me the difference between the Xilinix Virtex-II and the > Virtex-E Series? > Thanks for your answer. > > bye > > martinArticle: 40742
Nahum, Contact your FAE, and request information on how to use the "Freeze_DLL" feature. This is a signal that is part of the test primitive that we do not support, aminly because there was too much to do to get all the supported features, and some of the new ones introduced. Like most designs, there are a lot of hidden features that we placed in there for test, but may be useful for some applications. The freeze stops all tap updates, so once locked, and the delay is set, freezing suspends all further corrections for temperature and voltage changes in the system. Austin Nahum Barnea wrote: > Hi. > I want to use virtex2 DCM as a delay line on a clock signal. > This means that I want to disable any loop to prevent any > added jitter to the clock. I need only specified delay > in the 50 ps steps. > > How can it be done ? > > ThankX , > Nahum.Article: 40743
On Wed, 13 Mar 2002 17:04:37 -0600, Kevin Brace <ihatespam99kevinbraceusenet@ihatespam99hotmail.com> wrote: > I am currently experiencing a problem with XST's Pack I/O >Registers into IOBs option. >I don't appreciate XST overriding the design trade off I made in the >design, and do I have a way to prevent XST from duplicating the OE FF? >I am using ISE WebPACK 4.1WP3.0's XST (XST E.33), and Spartan-II XC2S150 >is the target device. >I feel like this OE FF duplication thing should not happen, and hope >that the future version of XST will give its users an option to disable >OE FF duplication if the user doesn't want it. > I had the opposite problem for a long time, until I realised the OE signal _into_ the ENBFFs has to be active low (mine was active high). Maybe changing the polarity of your OE signal would prevent this "optimisation"? Or, check if your tool chain supports "dont_touch" or "preserve_signal" attributes on specific signals? - BrianArticle: 40744
The old 4000 series stuff seemed to be pretty conservatively timed. It was not unusual to be able to clock something at 50% faster than the timing report stated in the lab under ideal conditions, however I would not put such an overclocked design into production unless you like spending your career fixing production problems. The numbers reported by the timing analysis are worst case over voltage, temperature and process. Chances are in the lab you will not hit the worst case on any of the three much less all of the three. For the timing, run the static timing analyzer and set it to report paths failing timing. Those are sorted so that the worst paths show up first. From that report, you'll be able to see what CLBs the worst paths go through, so you'll have an idea where to look. Josh Pfrimmer wrote: > Hi all, > For a class (calmer down.. I'm not looking for answers to my homework) > I've designed an 8-bit CPU. Fifteen instructions, pre-fetching, branch > predicting, load-store, etc. etc. So far, it cruises along at ~50MHz on an > XC4010XL-3. This is better than what's necessary for the class, but I'd > like to push it further. > > Now that I have a ballpark speed, what's the best way to get started > specifying constraints in a .ucf? How do I get the (old, old, old) > Foundation 3.1 software in the labs to tell me what the worst paths are, so > that I can start picking out false paths, etc. > > Incidentally, the post-layout timing report gives a figure of ~20MHz fo > the maximum clock speed, but on the board, I'm well over 45.. is this > typical? How can I get more accurate numbers out of the reports? > > Thanks for your attention > JoshPArticle: 40745
Nitin Chandrachoodan (nitin@eng.umd.edu) wrote: : It seems that the Xilinx Spartan chips can be used with the : Webpack which is free, and they also have very large : capacities (100k-200k for XC2S200). Two boards I have found : so far with these are : 1. XESS XSA-100 (100k gate, $279) from xess.com : 2. Digilab XLA 2 (XC2S200 Spartan II - 200k gates, $99) from : digilentinc.com There is another, similar $99 board out there, new with a spartan 2E, otherwise not to different. http://www.nuhorizons.com/EngineeringServices/SpartanIIEBoard.html : The digilent board seems to have better features at a lower : price, but XESS appears more popular overall. Are there any : other compelling reasons for using one or the other? The external SDRAM on the XESS board could be nice. There is a core availible on their website to interface this to FPGA designs. If you are demonstrating DSP stuff, this could be usefully, as you can store a large ammount of data to be processed on the board in advance, then the people using the boards can have the satisfaction of seeing just how fast they can do neat things.... Combine that with the primitive onboard VGA (theres some good examples out there on generating VGA timings in FPGAs with VHDL / Schematic) and you might be surprised at what comes out of the labs... On the other hand, there is more embeded 'BlockRAM' on the larger SpartanIIE chip on the Digilent board, so I guess the answer depends on the size of the data chunks you want to process vs. the number of chunks. The XESS XSV Boards are probably very good for DSP/FPGA classes, having audio in and out, composite video in and VGA out functionality - XESS links to some examples of their usage from the website. There a bit pricey though. --- cdsArticle: 40746
"Tim" <tim@rockylogic.com.nooospam.com> wrote in message news:1016124118.3610.0.nnrp-12.9e9832fa@news.demon.co.uk... > S. Ramirez wrote > > > You will be hard pressed to find these comparisons, since the license > > agreements of these vendors say something close to "Licensee shall not .. > > disclose the results of any benchmarking of the SOFTWARE, or use such > > results for its own competing software development activities, without the > > prior written permission of Blah Blah." > > You could fall back on the legal principle that "common abuse is not > actionable". From what we hear about some of the tools, common abuse > would be a fair summary :-) I could, but I don't have an attorney right now and would rather not get one anyhow to experiment legally. If you can spare an extra $100K-200K, please send it along and let's try it! :) Simon Ramirez, Consultant Synchronous Design, Inc. Oviedo, FL USAArticle: 40747
Hi, Haven't really looked at the DigiLab XLA 2 with the spartan II on, but we got the Digilab XLA some time ago, with Spartan XL on, and I didn't like it that much. I found that too many peripherals such as LED's and different BNC ports took up valuable I/O pin connections. On top of that, they had engineered there own programming dongle on to the board which didn't like the Xilinx Foundation programmers (Hardware Debugger and JTAG) at all. Instead, had to use some little utility I found on there website to program. I would recomend having a look at the Burch Ed. board (www.burched.com). I think the price is about $200 (AUS), has a Spartan II 200k gates (XC2S200) and easy access to all the pins. There is a picture of the board on their webpage. I have been using it for the past 9 months and it has worked perfectly as a prototyping board. I am a university student and learnt to work with it by myself. Adrian > Hello, > > We are trying to decide on boards for use in a course in the > Electrical Engg. department at our university. The > requirements we have come up with so far are as follows: > > 1. Easy to get started and working with it. > 2. Relatively inexpensive > 3. Can be used to implement reasonably large designs, > especially DSP filters, FFTs etc. Here we would like to > implement the designs without having to go to too much low- > level optimization (bit-serial implementations etc.) unless > absolutely necessary, as this would change the focus from > learning about FPGA implementation to low-level design. > 4. Can be used with existing tools (we have Synopsys DC and > FPGA compiler II, so we would prefer not to have to purchase > Foundation etc. unless necessary) > > It seems that the Xilinx Spartan chips can be used with the > Webpack which is free, and they also have very large > capacities (100k-200k for XC2S200). Two boards I have found > so far with these are > > 1. XESS XSA-100 (100k gate, $279) from xess.com > 2. Digilab XLA 2 (XC2S200 Spartan II - 200k gates, $99) from > digilentinc.com > > The digilent board seems to have better features at a lower > price, but XESS appears more popular overall. Are there any > other compelling reasons for using one or the other? > > Alternately, are there any other boards that are especially > suited to classroom use? Apart from basic use in a classroom > setting, we are also interested in boards that can be used > for rapid reconfiguration etc., for use in research into > reconfigurable computing techniques. > > Any replies much appreciated. > > Thank you, > > Nitin > >Article: 40748
Hi All, Apologies if this is too OT. I need a few parts for a project Easy enough to source, but thought someone might have excess they'd like to be rid of. Req. 6 or so, any of the following: xcr3128xl-12-TQ144 xcr3256xl-12-TQ144 xcr3384xl-12-TQ144 Sockets would be nice too. BTW: anyone care to recommend a fav source for small orders like this ? Many thx, Tom Private replies to: Buyer@REMOVEsomeisp.net Pls remove REMOVE.Article: 40749
"Austin Lesea" <austin.lesea@xilinx.com> schrieb im Newsbeitrag news:3C90C799.E64C72C2@xilinx.com... > The software got twice as fast, and many more powerful features were > added to make designs easier. The new power and speed of Virtex II Please, dont speakt with this marketing attitude. The first release of ISE 4.1 was buggy like HELL, and many bugs very much looked like software guy "wasting" no time with testing. . . . . -- MfG Falk
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Compare FPGA features and resources
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