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On Sun, 28 Apr 2002 23:44:29 GMT, Ray Andraka <ray@andraka.com> wrote: >Reminds me of Poly-Paks. For those of you who weren't around back then, >Poly-Paks was a company in the 70's that sold cut rate electronics of dubious >origin to hobbyists. For some, the availability of dirt cheap, albeit not 100% >parts can make the difference between playing with this stuff or just reading >about it. When I started playing with electronics, about all a newspaper route >would support was the Poly-Paks specials. Of course in those days, one could >get away with dead-bug construction and still get something working. > Wow, that brings back memories. As a college student, I used to order parts from their Lynne, MA mail-order address. And on a couple of occasions I went to their walk-in outlet in Wakefield, MA, where dozens of high-school girls ran around a huge warehouse filling orders. Mostly I bought specific parts, but occasionally got one of their grab-bags, replete with everything from transistors in rusted-out metal cans to TV tuner knobs. It was all wonderful. Historical note: Most of what Poly Paks sold was of iffy quality, but they made a special point of warning you about certain stuff, such as the grab-bags, by stating in their ad copy, "No time to test 'em!" This slogan has now been appropriated by the software industry. Bob Perlman ----- Cambrian Design Works http://www.cambriandesign.comArticle: 42601
<http://www.globetrotter.com/> HTH On Sun, 28 Apr 2002 23:32:56 GMT, "S. Ramirez" <sramirez@cfl.rr.com> wrote: >I would like to know who invented FlexLM. <SNIP>Article: 42602
"S. Ramirez" <sramirez@cfl.rr.com> wrote in message news:IE%y8.118703$nc.17199086@typhoon.tampabay.rr.com... > I would like to know who invented FlexLM. This product has been in use for > a while with some major EDA vendors, and apparently it is providing a very > good job of protecting the integrity and use of the products that use it. I > am surprised that in this world of breaking codes, someone hasn't broken the > FlexLM code. Don't get me wrong. I am very much in favor of protecting the > intellectual property rights of companies or people who develop and market > products, and I am glad that it hasn't been broken. > > I did hear about 3-5 years ago that someone in Hong Kong had broken the code > on FlexLM, but I then heard that this was incorrect. I salute a product > that has protected EDA products for years and has managed to stay unbroken > for so long. A Google search for "FlexLM crack" gives the following: http://linux20368.dn.net/crackz/Tutorials/Flexpilg.htm http://sfcheng.myetang.com/crack/crk.htm Leo Havmøller.Article: 42603
> Life is too precious to be wasted on such silly misunderstandings.
What do you mean?
Are you saying that I should have known that Virtex IOB tri-state
buffers are active low?
I think what I said previously should have been included in Spartan-II
datasheet.
Kevin Brace (In general, don't respond to me directly, and respond
within the newsgroup.)
Peter Alfke wrote:
>
> It's the old confusion between output enable and tristate, which obviously are the
> opposite of each other. But we should, therefore, make it redundantly absolutely
> and perfectly clear that active High OE is identical with active Low 3-state ( and
> vice versa).
> Life is too precious to be wasted on such silly misunderstandings.
>
> Peter Alfke, Xilinx Applications
> =============================================
Article: 42604Hi, Can anyone confirm that the Synplicity/Xilinx special promotion of $3995 for Synplify and $1000.00 for HDL Analyst is a "one-year time based license" i.e it will only be useable for one year?? Thanks AnthonyArticle: 42605
Hi, I must configure some pins on this device with 24mA output drive.Where can I find this option (in the UCF file, in the Project Manager, ..)? Thanks, Frank.Article: 42606
I know I am asking a really basic question, but which website lets me do an IP lookup? Kevin Brace (In general, don't respond to me directly, and respond within the newsgroup.) Brian Drummond wrote: > > > Priceless... > > Turn the headers on. See a line that says > NNTP-Posting-Host: 66.35.226.228 > > Try a lookup... > > IP address: 66.35.226.228 > Official name: ip66-35-226-228.altera.com > > oops! > > - BrianArticle: 42607
Yes, but isn´t there anyone who knows this information? I´m going to get this information out, without signing a NDA, but it would save a lot of my time, if somebody already has this information ;-) greetings michaelArticle: 42608
Is it possible to use the dedicated SelectMap data pins D0..D7 as ordinary IO-pins when configuration is finsihed and at the same time support partial reconfiguration? Readback does not need to be supported. I would like D0..D7 to be used as part of a 16 bit wide microprocessor data bus, when the FPGA is not in configuration mode or partial reconfiguration mode. Thanks in advance Stein KjølstadArticle: 42609
I am interested in using the PLI-based SMI (Software Model Interface)
for testing Iverilog designs. The link
given on the Iverilog website is no longer valid. Does anyone have the
updated link?
Bad link from Iverilog site.
http://members.home.net/lewisas/smi.html
Article: 42610> I know that I could do this, but what shall I do with an information I can > tell to nobody? > And why lies this information under NDA? I think it is basically to protect proprietary information not crreping through to competition. > I´ve bought an board, got the (not very cheap) software license and now the > time is over and I can´t use it anywhere. Isn´t it unfair? If you take one year subscribtion to a magazine, and do not renew, is it unfair that they do not continue send you magazines? Most of the money for the AT40K/94K dev kits goes to third party vendors. You can buy an unlimited time licences, but Mentor wants 2.5-3k$ for that. -- Best Regards Ulf at atmel dot com These comments are intended to be my own opinion and they may, or may not be shared by my employer, Atmel Sweden.Article: 42611
Surely this is Xilinx posting in disguise - to stimulate debate and give a chance to spout on. Although it is a stunning device. -- Posted via Mailgate.ORG Server - http://www.Mailgate.ORGArticle: 42612
I attended the Boston show, lucky I was late and sat at back. After an hour I was utterly bored hearing the IBM & Xilinx fellows repeating the same blurb over & over, I thought we were already basically sold. Good job you had some interesting partners there like Nallatech, Celoxica, Mathworks etc, got to hang with them instead, much more interesting.If you do another marketing BS show again, bring these partner guys back.Thanks for the sandwiches.I am curious about how the Celoxica guys went down with other attendees, great HW demo of Venus de Milo. But C HW design remains a tough sell (esp at $35K) no matter how it's dressed since HandelC hasn't been standardised & most of the other C guys going south.Article: 42613
Hello! Can anyone advise where can I find the documentation about a complete list of ptf sections and assignments? According to Altera's manual it should be at http://www.altera.com/nios but no sign of it. I'd like the ptf specs for Nios 2.0 because I already have it for 1.1 (is there any difference or new feature?). Regards, Matjaz FincArticle: 42614
Hello again! I would like to make a Nios peripheral that receives some data (as slave peripheral) from Nios cpu and after some processing pass it directly (as master) to shared RAM and let Avalon do the arbitration. How do I implement the master fuctionality and how can I address RAM directly through Avalon in the ptf file or SOPC builder? Please advise. Regards, Matjaz FincArticle: 42615
I am designing a PCB with Spartan2 200K, package PQ208. For further upgrade, it may be interesting to use a bigger FPGA. so here are a few questions: 1-(for xilinx marketing) Is Spartan2 family doomed or can I hope to get a XC2S300 or 400 in the mid-term? 2- If I decide to use FG256 or even FG456 package instead, can I "plug and play" on the same board a Virtex 2.5V XCV300, I mean: Are the power pins, clk pins and configuration pins exactly the same? Thanks, StephaneArticle: 42616
Hello, As far as I remember from it's documents, FlexLM was not originally intended to "protect" softwares, but to force the "customers" to follow the licensing contracts they have made with the vendor. In this way it's internal structure is very simple to follow and to "crack" and almost every software using this licensing system has been cracked. In fact, as the target in all those cracks has been the same thing, i.e. the FlexLM, it has resulted to creation of some "generic" ways to crack it. For the time being, with a little search on the net and small time studying numerous tutorials about cracking FlexLM, one can virtually crack any software using it in just a few hours (well, yes, after some practice you may bring that to less than 10 minutes...) Anyway, I don't think it's a good protection system, though it was not designed to be such anyway. On the other hand, EDA tools are not office softwares or games, and are published in a very limited market as the users are very professional and hence, limited. This way it may be not a major problem with FlexLM in the eyes of the OEMs as they may feel it's advantages are enough to compensate for it's loose protection... Best Regards Arash "S. Ramirez" <sramirez@cfl.rr.com> wrote in message news:IE%y8.118703$nc.17199086@typhoon.tampabay.rr.com... > I would like to know who invented FlexLM. This product has been in use for > a while with some major EDA vendors, and apparently it is providing a very > good job of protecting the integrity and use of the products that use it. I > am surprised that in this world of breaking codes, someone hasn't broken the > FlexLM code. Don't get me wrong. I am very much in favor of protecting the > intellectual property rights of companies or people who develop and market > products, and I am glad that it hasn't been broken. > > I did hear about 3-5 years ago that someone in Hong Kong had broken the code > on FlexLM, but I then heard that this was incorrect. I salute a product > that has protected EDA products for years and has managed to stay unbroken > for so long. > > Simon Ramirez, Consultant > Synchronous Design, Inc. > Oviedo, FL USA > >Article: 42617
Does anyone know, how to route the inputs and ouputs to I/O-Pins in MGL? Is there any document else then techref.pdf? michaelArticle: 42618
There is some good stuff at http://www.webdevelopersjournal.com/lookup_tools.html Roy. Kevin Brace wrote: > I know I am asking a really basic question, but which website lets me do > an IP lookup? > > Kevin Brace (In general, don't respond to me directly, and respond > within the newsgroup.) > > Brian Drummond wrote: > > > > > > Priceless... > > > > Turn the headers on. See a line that says > > NNTP-Posting-Host: 66.35.226.228 > > > > Try a lookup... > > > > IP address: 66.35.226.228 > > Official name: ip66-35-226-228.altera.com > > > > oops! > > > > - BrianArticle: 42619
hi, does anyone have experience these? CLK pad input to FF show up as unconstraint path during timing analysis. and reduce coverage of timing constraint (90.5%). These un-constraint paths are the clock delay from the clk pad to the clk pin of the FFS Clk Pad input goes through a DCM and generate a internal clk to most of the ffs in the design. there is currently a period constraint on the clk pad input and during translate, there is message that show that the period constraint have been push through the DCM and new period constraint had been generated for the internal clock. The internal clock period constraint is working fine. Why are all paths from Clk pad input to all ffs clk pin show up as an unconstraint path? pyngArticle: 42620
Hello Benjamin, This is an area of continuing irritation to me! I've done several searches for a 'stand-alone' ABEL compiler/simulator without success. Even if you find it you still don't have a fitter. I have successfully used Lattice Semi's ABEL (which is more-or-less-free) to create a design in ABEL. I then used XILINXs' ABEL toVerilog utility to convert the design to Verilog. Which worked when targeting a Lattice device! I did this as a tool to aid me in learning Verilog but it <might> work for Altera. Roy. Benjamin Heart wrote: > Does anyone know of an ABEL compiler that is available, free or > otherwise, for use with Altera products; the MAX 7000 in particular. > Xilinx and Lattice each have their ABEL tools, but Altera does not > seem to support ABEL. Is there some third party option? If so where > can I get it? > > Thanks in advance, > BenArticle: 42621
Send an order to the rep. instead of the disti. he may be able to expedite. I've done this and it sometimes works. You also may get access to to the product manager in this way. Roy. rickman wrote: > I have been trying to get my hands on some pieces of XC2S150E-6FG456I > for over a month. I am told that they will not be shipping until June > and I need to get about four pieces for prototypes in a month. I can > buy the commercial temp versions, but we need the industrial temp > versions for this version of the board. > > I have tried working with distis and they keep saying that Xilinx won't > give them parts until June no matter how much they beg. I have > contacted the rep and they keep talking about placing an order so that > it can be expedited. But what is the point of placing an order if I > can't get delivery when I need it? > > Anyone know how to get your hands on a small number of ES chips prior to > the official release? > > I was able to get some chips from the Coolrunner product manager under > these same conditions awhile back. But I don't have a way to contact > the SpartanIIE product manager. > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAXArticle: 42622
bharathbhushan wrote:
> we got a problem in using a function repeatedly calling through a variable.
Consider posting your code to the appropriate comp.lang. group.
-- Mike Treseler
Article: 42623Phil, you have read too many conspiracy stories. Peter Alfke Phil Connor wrote: > Surely this is Xilinx posting in disguise - to stimulate debate > and give a chance to spout on. Although it is a stunning device. > >Article: 42624
Hristo Stevic wrote:
> any input here??
>
Consider writing a simulation testbench
to answer the funtional question and
run static timing to check margins.
-- Mike Treseler
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