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Messages from 56975

Article: 56975
Subject: FPGA device + CPU
From: SP <nowhere@nowhere.com>
Date: Fri, 20 Jun 2003 04:37:10 +0000 (UTC)
Links: << >>  << T >>  << A >>
I am looking for an FPGA kit that has a CPU like ARM that can run Linux. 
Basically I want to play with idea of accelerating some functions in the 
FPGA and expose them as device drivers to Linux.

Am still green in FPGAs.

Thanks a lot!!
-Sumeet

Article: 56976
Subject: Re: FPGA device + CPU
From: Mario Trams <Mario.Trams@informatik.tu-chemnitz.de>
Date: Fri, 20 Jun 2003 08:01:21 +0200
Links: << >>  << T >>  << A >>
SP wrote:

> I am looking for an FPGA kit that has a CPU like ARM that can run Linux.
> Basically I want to play with idea of accelerating some functions in the
> FPGA and expose them as device drivers to Linux.

Xilinx has some with PowerPC (VirtexII-Pro) and Altera has some with 
Arm (I think). Just check their web sites.

Regards,
Mario 


Article: 56977
Subject: Re: Investment in FPGA
From: Mario Trams <Mario.Trams@informatik.tu-chemnitz.de>
Date: Fri, 20 Jun 2003 08:07:49 +0200
Links: << >>  << T >>  << A >>
Fei wrote:

> hi, guys,
> 
> I am interested in developing high speed wireless modem
> (modulation/demodulation, channel coding/decoding and equalization)
> using FPGA.  But I am new to FPGA.
> 
> Anyone can evaluate if it worthy?
> 
> 1. How long does it take to get into FPGA design?

:-)
I think this depends heavily on the one who is trying to do so ;-)
If you have good experience in (general) digital hardware design
then it's not a big deal.

> 2. How much money is needed for a FPGA development kit?

200-300 USD should be a good starting point in order to get a 
non-trivial evaluation board. The development software for 
smaller FPGAs is usually free. Just go and check 
the web sites of major FPGA companies.

Regards,
Mario


Article: 56978
Subject: Re: Port Mode
From: Mario Trams <Mario.Trams@informatik.tu-chemnitz.de>
Date: Fri, 20 Jun 2003 08:37:45 +0200
Links: << >>  << T >>  << A >>
Thomas wrote:

> 
> see my post about the bidirectional bus, I have the same problem;
> 
> in theory:
> 
> IOPort : inout
> Input: in
> Output : out
> 
> 
> process(IOPort, Output) is
> begin
> Input <= IOPort
> if(ReadingFromTheOutside = '1') then
> IOPort <= Output;
> else
> IOPort <= (others => 'Z');
> end if;
> end process;

Thomas, this piece of VHDL-Code cannot work, actually. 
You are evaluating Output that is "out" which is not 
possible. Additionally you write into Input. 
No VHDL compiler will (should) accept this.

My guess is that you exchanged Input and Output and you
actually wanted to write:

process(IOPort, Input) is
begin
        Output <= IOPort;
        if(ReadingFromTheOutside = '1') then
                IOPort <= Input;
        else
                IOPort <= (others => 'Z');
        end if;
end process;

(Or alternatively you wanted to say that Input is "out" and 
Output is "in"). 

Anyways, I also do not yet have an idea why this does not work.
Can you try whether this changes something:

signal intermediate ....

process(IOPort, Input) is
begin
        Output <= IOPort;
        if(ReadingFromTheOutside = '1') then
                intermediate <= Input;
        else
                intermediate <= (others => 'Z');
        end if;
end process;

IOPort <= intermediate;

What is actually attached at the other end(s) of your 
bidirectional bus (i.e. IOPort). Might it be that there
is some problem?
Just for testing, you should not connect anything else 
to it and see whether IOPort contains reasonable values 
when  ReadingFromTheOutside = '1'. Then add connections 
one by one and check it each time. 
That's a general rule of thumb for debugging.

Regards,
Mario

Article: 56979
Subject: Re: Port Mode
From: Mario Trams <Mario.Trams@informatik.tu-chemnitz.de>
Date: Fri, 20 Jun 2003 08:40:27 +0200
Links: << >>  << T >>  << A >>
Isaac wrote:

> Hi ,
> How can you drive the inout port from inside the logic?
> Meaning if I have defined a variable and I want to assign this
> variable to inout port( bidirectional), then it didn't work.
> Eg. If have a shared variable A and I want to assign this value to the
> bidirectional bus B (inout). But in simulation I can't see anything
> happening.

Isaac, can you post a stripped-down version of your VHDL code here
that shows your problem?
Then we might be able to help.

Regards,
Mario

Article: 56980
Subject: Re: FPGA device + CPU
From: giachella.g@laben.it (g. giachella)
Date: 20 Jun 2003 02:28:26 -0700
Links: << >>  << T >>  << A >>
SP <nowhere@nowhere.com> wrote in message news:<Xns939FF043C4511nowherenowherecom@216.109.160.14>...
> I am looking for an FPGA kit that has a CPU like ARM that can run Linux. 
> Basically I want to play with idea of accelerating some functions in the 
> FPGA and expose them as device drivers to Linux.
> 
> Am still green in FPGAs.
> 
> Thanks a lot!!
> -Sumeet

The Altera's Excalibur family is similar to an Apex 20KE device + ARM
922T embedded processor connected to an AMBA bus, which interfaces the
processor to the remaining blocks of the fpga.

Regards,

Giuseppe Giachella

Article: 56981
Subject: Output signal problem.
From: frank_zampa@yahoo.it (Frank Zampa)
Date: 20 Jun 2003 02:58:27 -0700
Links: << >>  << T >>  << A >>
Dear Sirs, i have a problem with the outputs of my FPGA (a Spartan
XL).

I have eight bank of 16x1 dual port RAM. When i read the data (DPO)
from the bidirectional bus(eight lines INOUT) the electrical signals
are good, except when all the bits are at "1".


For example, when i measure with the oscilloscope one line when i'm
reading the signal is perfect
   ____
__|    \___

when all the bits are at "1" the same signal is bad
     __
__WWW  \____

If i turn off one of the others lines the signal return good.

Whe i read data from other sources different from  RAM i don't have
this problem.

Can anybody help me?

Thanks

Frank Zampa

Article: 56982
Subject: Xilinx --> WARNING:DesignRules:372
From: "Basuki Endah Priyanto" <EBEPriyanto@ntu.edu.sg>
Date: Fri, 20 Jun 2003 18:06:56 +0800
Links: << >>  << T >>  << A >>
Hi,

Anybody can give me more detailed explaination on the following message
:

WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net
   iuser_ap_my_trans_i3_i6__n0049 is sourced by a combinatorial pin.
This is not
   good design practice. Use the CE pin to control the loading of data
into the
   flip-flop.

What is the implication if I just ignore the warning message ?

Thanks.

BR,
Buzz


Article: 56983
Subject: Perl Testbench generator
From: "Nial Stewart" <nial@spamno.nialstewart.co.uk>
Date: Fri, 20 Jun 2003 11:08:09 +0100
Links: << >>  << T >>  << A >>
The code editor I use when writing VHDL doesn't have any sort of
automatic test bench generation facility (I don't want to know
about emacs thanks).

I've written a Perl testbench generator which generates a testbench
round a given source file. I normally write a testbench for all but
the the most trivial VHDL modules and so this can save some time/typos.

The script is fairly simple and is a good example of how easy file
manipulation is with Perl. It works with my source files, if you find
any problems with your own please let me know and I'll update it
(maybe).

It can be found on the 'Downloads' page of my web site below.


Nial Stewart.

--

Nial Stewart Developments Ltd
FPGA and High Speed Digital Design
www.nialstewartdevelopments.co.uk



Article: 56984
Subject: Re: Controlling FPGA speed with VCCINT
From: Andras Tantos <andras_tantos@yahoo.com>
Date: Fri, 20 Jun 2003 03:35:46 -0700
Links: << >>  << T >>  << A >>
Hi!

> If you have a feedback mechanism to adjust the delay, you could build a
> delay line
> out of  LUTs and tap (or bypass parts of it) the delay line with a mux
> type
> arrangement.  That should work out well with your desired 2.3ns
> resolution.  It would be much cleaner than diddling the VCC, and would
> keep it all digital. You'll probably have to hand-route the delay line to
> make sure the routing doesn't
> spoil your queue.  For finer resolution you can use the carry chains as
> the delay
> line.  Feedback to dynamically adjust the delay line is desirable to keep
> variations due to process, voltage and temperature in check.

That's almost exactly what I'm planning to do. I would use a different
thechnique to process the delay-lines' output, not a mux, but that's not
relevant.

Andras Tantos

Article: 56985
Subject: Multiple clock generation and maybe FIFO
From: "Moises Cambra" <mcambra@jotmail.com>
Date: Fri, 20 Jun 2003 13:18:24 +0200
Links: << >>  << T >>  << A >>
We would like to generate multiple and different clock frequencies from a
single clock source. For example, from 8MHz obtain eight clock outputs of
arbitrary frequencies like 192KHz, 38400Hz, 9600Hz, etc. Basically, it could
be done with one counter/comparator for each output, with output toggle and
reset of the counter when it equals the value of the comparator. The values
of the comparison have to be loaded externally from a microcontroller to
change the frequencies from time to time.

Apart from this, it would be nice if the same device could include a FIFO of
1 or 2 Kbytes deep.

Since it will be the first time we use programmable logic and we don't have
yet any development tool, my question is: what family/product would you
recommend for this application? Power consumption is important. If the FIFO
means to jump to a too big thing, we could stuck with the discrete FIFO...

Thanks,
Moises



Article: 56986
Subject: Is this is possible???
From: vhdl_uk@yahoo.co.uk (MACEI'S)
Date: 20 Jun 2003 04:48:05 -0700
Links: << >>  << T >>  << A >>
Hi fellow,
If I have input port which is bidirectional and I have used this bus
to write into device and thi bus still has signal on it's pins. Now at
this moment if I want to read from same bus then it is possible to do
it or not. What would happen to the signal which is already on the bus
as a result of write operation.
DO I need to tristate the bus just after write and then perform read
operation?

Rgds 
Macei's

Article: 56987
Subject: Re: XST verilog problem
From: nospam <nospam@nospam.invalid>
Date: Fri, 20 Jun 2003 13:43:45 +0100
Links: << >>  << T >>  << A >>
muthu_nano@yahoo.co.in (Muthu) wrote:

>> 
>> That isn't quite the same, crrst is a synchronous clear in the original. I
>> had seen a Xilinx suggestion of moving logic expressions outside the always
>> block to work around the problem.
>
>What Xilinx Suggests? Can you give the modified piece of code?

Search their knowledgebase for "known FF".  You will find acknowledgement
of the problem with a couple of sample workarounds neither of which quite
matched the code I posted. 


Article: 56988
Subject: Re: FPGA device + CPU
From: Michael Dales <michael@dcs.gla.ac.uk>
Date: 20 Jun 2003 13:58:22 +0100
Links: << >>  << T >>  << A >>
There's been quite a bit of research in accelerating processors by
using programmable function units. You might also want to look through
the proceedings of conferences like FPL, FCCM, etc., and even ISCA.

SP <nowhere@nowhere.com> writes:

> I am looking for an FPGA kit that has a CPU like ARM that can run Linux. 
> Basically I want to play with idea of accelerating some functions in the 
> FPGA and expose them as device drivers to Linux.
> 
> Am still green in FPGAs.
> 
> Thanks a lot!!
> -Sumeet

-- 
Michael Dales --- email: michael@dcs.gla.ac.uk --- tel: +44 141 330 6297
Department of Computing Science, University of Glasgow, Glasgow, G12 8QQ

Article: 56989
Subject: Re: Multiple clock generation and maybe FIFO
From: "Falk Brunner" <Falk.Brunner@gmx.de>
Date: Fri, 20 Jun 2003 15:31:05 +0200
Links: << >>  << T >>  << A >>

"Moises Cambra" <mcambra@jotmail.com> schrieb im Newsbeitrag
news:bcuqi5$sia$1@nsnmrro2-gest.nuria.telefonica-data.net...

> We would like to generate multiple and different clock frequencies from a
> single clock source. For example, from 8MHz obtain eight clock outputs of
> arbitrary frequencies like 192KHz, 38400Hz, 9600Hz, etc. Basically, it
could
> be done with one counter/comparator for each output, with output toggle
and
> reset of the counter when it equals the value of the comparator. The
values
> of the comparison have to be loaded externally from a microcontroller to
> change the frequencies from time to time.
>
> Apart from this, it would be nice if the same device could include a FIFO
of
> 1 or 2 Kbytes deep.

So what you want to do? Sounds like a UART appliaction. This can be made
very easy, a small Spartan-IIE is part go. (Yes, there are also Altera part
that work well here ;-)

> Since it will be the first time we use programmable logic and we don't
have
> yet any development tool, my question is: what family/product would you
> recommend for this application? Power consumption is important. If the
FIFO
> means to jump to a too big thing, we could stuck with the discrete FIFO...

No, FIFOs are plug-and-play black boxes, especially in PLDs.

--
Regards
Falk




Article: 56990
Subject: Re: Please help with clock signal
From: "Falk Brunner" <Falk.Brunner@gmx.de>
Date: Fri, 20 Jun 2003 15:34:03 +0200
Links: << >>  << T >>  << A >>

"Ed Stevens" <ed@stevens8436.fslife.co.uk> schrieb im Newsbeitrag
news:bcv1hu$3qd$1@newsg4.svr.pol.co.uk...
> Hi,
>
> Im getting the following error in the XILINX Project Navigator:
>
>
> ERROR:MapLib:93 - Illegal LOC on symbol "w_clk" (pad signal=w_clk) or
BUFGP
> symbol "w_clk_BUFGP" (output signal=w_clk_BUFGP), IPAD-IBUFG should only
be
> LOCed to GCLKIOB site.
>
>
> How can I assign w_clk to a general purpose I/O pin, rather than one of
the
> clock inputs?

You must prevent the HDL compiler from automatically inserting a IBUFG. You
can do this for XST (the Xilinx compiler) by use of the VHDL attribute
CLOCK_BUFFER. Have a look at the constraints guide, it explains the use
quite well.

--
Regards
Falk




Article: 56991
Subject: PALs, GALs and ABEL
From: Paul Urbanus <urbpublic@hotmail.com>
Date: 20 Jun 2003 14:06:01 GMT
Links: << >>  << T >>  << A >>
I have two old designs - from 1987 - that I wrote in ABEL (by Data I/O) 
that fit into a PAL20L8 and a PAL20L10. I want to program some new parts 
with these designs, but only have GAL20V8 and GAL22V10 parts available.

According to a Lattice Semi data sheet, there parts are supposed to be 
fuse compatible with all of the parts they replace. So, in theory I 
should be able (pardon the pun) to use the PAL20L10 JEDEC file to 
program the GAL22V10 and the PAL20L8 JEDEC file to program the GAL20L8.

Anyone have any experience in this matter who can say, "Yes, it will 
work, or, no way in Hades this will work?"

On a related note, does anyone know if the old DOS version of ABEL is in 
the public domain? And if so, where I can download a new version.

Of course, I could always recode the PALS in VHDL using the Cypress Warp 
software, which used to support the 22V10, at least.

Thanx


______________________________________________________________________
Posted Via Uncensored-News.Com - Still Only $9.95 - http://www.uncensored-news.com
      <><><><><><><>   The Worlds Uncensored News Source   <><><><><><><><>
  

Article: 56992
Subject: Virtex II Pro FF896 socket
From: antti@case2000.com (Antti Lukats)
Date: 20 Jun 2003 07:09:22 -0700
Links: << >>  << T >>  << A >>
Hi

does anybody have experience with 1mm BGA sockets?

mpi.tycolectronics.com 

there are I think suitable sockets but I havent yet got the price quote
sometimes the BGA sockets costs over 4000 USD - I do hope the MPI
sockets are a bit cheaper but if there are other low cost alternatives
please let me know!

tnx
antti lukats

Article: 56993
Subject: Virtex-E boards
From: "danyxp" <danyxp@terra.es>
Date: Fri, 20 Jun 2003 16:33:12 +0200
Links: << >>  << T >>  << A >>
Does anyone have a Virtex-E fpga based board design for free use? I remember
I had seen here a Virtex-E 2000 based board with several peripherals but I
cant find the link.
Thanks.
Dany X.P.



Article: 56994
Subject: Re: Virtex II Pro FF896 socket
From: Keith Williams <krw@attglobal.net>
Date: Fri, 20 Jun 2003 10:35:58 -0400
Links: << >>  << T >>  << A >>
In article <80a3aea5.0306200609.72f7be70@posting.google.com>, 
antti@case2000.com says...
> Hi
> 
> does anybody have experience with 1mm BGA sockets?
> 
> mpi.tycolectronics.com 
> 
> there are I think suitable sockets but I havent yet got the price quote
> sometimes the BGA sockets costs over 4000 USD - I do hope the MPI
> sockets are a bit cheaper but if there are other low cost alternatives
> please let me know!

We've used AQL (http://www.aqlmfg.com) BGA sockets with success.  I 
don't think they're going to save you much money (we paid about $3000US 
each), but they're an alternative.  

-- 
  Keith

Article: 56995
Subject: User Core OPB Problem (EDK3.2)
From: Matthias Dyer <dyer@tik.ee.ethz.ch>
Date: Fri, 20 Jun 2003 16:36:11 +0200
Links: << >>  << T >>  << A >>
Hello,

We are trying to implement an OPB slave user core as described in the "User
Core Template Reference Guide" (Jan 2003). We are using the template 
"opb_core_ssp0_v1_00_a". We have connected the user core to the OPB Bus of a
Microblaze system (generated with Xilinx EDK3.2 SP1 tools). Now, having
this core as the only opb slave on the bus causes no problems. But when we
connect other pre-build peripherials such as the "uart-lite", our core
interfers somehow with the other cores. In particular the uart output is
croped after 16 chars if our user core is present. This is a weird behavior
since our core should have a well defined opb addres space and does only
read from the opb and does not write to it.

This effect even occurs when we take an empty user core template! 

Have anyone had the same experience or can anyone help?

Thanks a lot and best regards,

Matthias 



Article: 56996
Subject: Re: PALs, GALs and ABEL
From: mikeandmax@aol.com (Mikeandmax)
Date: 20 Jun 2003 15:30:22 GMT
Links: << >>  << T >>  << A >>
>
>I have two old designs - from 1987 - that I wrote in ABEL (by Data I/O) 
>that fit into a PAL20L8 and a PAL20L10. I want to program some new parts 
>with these designs, but only have GAL20V8 and GAL22V10 parts available.
>
>According to a Lattice Semi data sheet, there parts are supposed to be 
>fuse compatible with all of the parts they replace. So, in theory I 
>should be able (pardon the pun) to use the PAL20L10 JEDEC file to 
>program the GAL22V10 and the PAL20L8 JEDEC file to program the GAL20L8.

Well, almost.  There is a utility on the lattice website, PALTOGAL.EXE, which
will convert the old JED into a GAL-appropriate JED file, and supports most, if
not all, older SPLD types.  it is a DOS executable, so run in a DOS window. 
run paltogal, it will give you an options/help screen, to walk you thru the
syntax required.  
Hope this helps,

Michael Thomas
LSC SFAE
New York/New Jersey
631-874-4968 fax 631-874-4977
michael.thomas@latticesemi.com
for the latest info on Lattice products - http://www.latticesemi.com
LATTICE - BRINGING THE BEST TOGETHER


Article: 56997
Subject: Re: PC-104 dev Boards
From: rickman <spamgoeshere4@yahoo.com>
Date: Fri, 20 Jun 2003 11:59:47 -0400
Links: << >>  << T >>  << A >>
"H. Peter Anvin" wrote:
> 
> Followup to:  <3EF1C96A.448B85D6@yahoo.com>
> By author:    rickman <spamgoeshere4@yahoo.com>
> In newsgroup: comp.arch.fpga
> >
> > Even so.  How can you handle 88 signals with two 32 bit parts?  There
> > are
> > 16 Data
> > 27 Addr
> > 11 IRQ
> > 14 DMA
> >  8 Cntl
> > 12 MISC
> > --------
> > 88 Total
> >
> > Slave mode
> > 16 IO (Data)
> > 42 In
> > 30 Out
> >
> 
> This is the ISA side.  We're using the PCI side.

Then we are talking about two different animals.  I belive PCI muxes
addr and data on the same 32 pins, so that saves a lot.  But that would
be PC/104+, not PC/104.  


-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 56998
Subject: Re: Spartan3 in WebPack
From: Steve Lass <lass@xilinx.com>
Date: Fri, 20 Jun 2003 10:14:37 -0600
Links: << >>  << T >>  << A >>
Lukasz Salwinski wrote:

> uh.. i guess i've got to wait till 7.1 then (or find a third-party
> iMPACT substitute).

Just to be clear, you will have to wait until 7.1 for the Linux version 
of WebPACK.  iMPACT and the cable
drivers will work under Linux in 6.2 and be available in other 
configurations (BaseX, Alliance and Foundation).

Steve


Article: 56999
Subject: Quartus bug or wrong VHDL?
From: "Martin Schoeberl" <martin.schoeberl@chello.at>
Date: Fri, 20 Jun 2003 16:32:02 GMT
Links: << >>  << T >>  << A >>
Since Leonardo is not longer available from Altera I'm trying to use Quartus
for synthesis. But I get a different output with Quartus. I tracked the
problem down and now my qustion is: Is it a bug or sloopy written VHDL?

The problem is setting output to tristate. See following VHDL code: I asumed
that it is ok when the databus (d) is set to 'Z' in state 'idl' and this
will not change when changing state to 'rd1'. This was ok with Leonardo. But
with Quartus I have to set d to 'Z' again in every state. What is the
correct VHDL code?

Martin

process(clk, reset, din, mem_wr_addr, mem_rd, mem_wr)
begin
    if (reset='1') then
        state <= idl;
        a <= "ZZZZZZZZZZZZZZZZZZZ";
        d <= "ZZZZZZZZ";
        ....
    elsif rising_edge(clk) then
        case state is
            when idl =>
                a <= "ZZZZZZZZZZZZZZZZZZZ";
                d <= "ZZZZZZZZ";

                if (mem_rd='1') then
                    a <= din(16 downto 0) & "00";
                    nram_cs <= '0';
                    ram_access <= '1';
                    i := ram_cnt;
                    nrd <= '0';
                    state <= rd1;
                elsif (mem_wr='1') then
                    ...
            when rd1 =>
                d <= "ZZZZZZZZ"; -- this line is necessary in Quartus but
NOT in Leonardo
                i := i-1;
                if (i=0) then
                    state <= rd2;
                    mem_din(7 downto 0) <= d;
                    a(1 downto 0) <= "01";
                    i := ram_cnt;
                end if;

            when rd2 =>
                d <= "ZZZZZZZZ"; -- same as in rd1
                i := i-1;
                if (i=0) then
                    ...

--------------------------------------------------------
JOP - a Java Processor core for FPGAs now
on Cyclone: http://www.jopdesign.com/cyclone/





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2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarAprMayJunJulAugSepOctNovDec2017
2018JanFebMarAprMayJunJulAugSepOctNovDec2018
2019JanFebMarAprMayJunJulAugSepOctNovDec2019
2020JanFebMarAprMay2020

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

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