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Ralph Mason wrote:
> I am not much of a VHDL person, you wouln't by chance know how to set the
> values if the register is declared in a record that in instantiated using
> the above syntax?
>
> type v_reg_type is record
> -- registers
> IOLatch : std_logic_vector(4 downto 0);
> IOLatch2 : std_logic_vector(4 downto 0);
> end record;
>
> signal r, rin : v_reg_type;
It's just a signal assignment, but
the right hand side value must match the type, for example:
constant v_reg_init : v_reg_type :=
(IOLatch => ( others => '0'),
IOLatch2 => ( others => '0')
);
-- Mike Treseler
Article: 57401William LenihanIii wrote: > > ---------------------------------------------------------------------------- > ------ > HOW DOES SPARTAN-3 DIFFER FROM VIRTEX-II? > > Spartan-3 is supposed to be = Virtex-II minus "some features". > Unfortunately, > Xilinx does not appear to provide a comprehensive list of those differences. > The following is my attempt at making such a list based on a first-cut > review > of each families' literature. > > Anyone have any comments, corrections, additions, or questions about this > list? > Then post them here and please 'cc' me via email. > > Thank you. > > Bill Lenihan lenihan3we@earthlink.net > ---------------------------------------------------------------------------- > ------ > > Vccint = 1.2v ..... instead of V-II's 1.5v > Are there any off-the-shelf, 1-chip linear regulators (not switching > regulators) that can supply 1.2v? Yes, the 1.2 volts is not hard, the question is from what voltage? Using an input voltage lower than 2.0 or 2.5 is not so easy. But there are a few around, Micrel, Maxim and some others. Micrel has a linear controller that if coupled with one of the really small MOSFETs is a smaller total footprint than a one piece solution and has better power numbers. > Vccaux = 2.5v ..... instead of V-II's 3.3v > > half the slices are NOT full-featured: missing RAM & shift-register > capability This has been discussed with mixed opinions. I think most designers won't care since using more than half the chip as SRs is unlikely (other than Ray Andraka). > up to 4 DCMs ..... instead of V-II's 12 Yeah, I would really like to have 5 in my design, but I will settle for 4. > DCM works on input clocks up to 325 Mhz ..... V-II up to 450 Mhz > > 8 global clocks ..... instead of V-II's 16 > > data sheet mentions BUFGMUX global clock buffer, but not BUFGCE ..... V-II > has both > > greater # of I/O, due to staggered pad scheme at chip periphery I don't think this is correct. The number of IOs for a given number of slices or gates is about the same. I spot checked about four parts and did not see a significant difference. > LVPECL I/O not available > > LVDS only w/ Vcco = 2.5v ..... V-II can run LVDS from Vcco = 2.5v or 3.3v > > Is there any capability for Spartan-3's +3.3v LVTTL inputs & outputs to > interact with other devices that use +5v TTL? ..... V-II (and Virtex-E) > +3.3v LVTTL inputs could be driven by +5v TTL outputs if an appropriately > sized current-limiting resistor were in series, while V-II (and Virtex-E) > +3.3v LVTTL outputs could safely connect directly to +5v TTL input devices > with no intervening resistor networks. > > configuration pins are LVCMOS25 @ 12mA ..... V-II's are LVTTL @ 12mA > > data sheet mentions a Master/Slave "Parallel" configuration mode that LOOKS > the same as V-II's "SelectMap" mode. Are they completely identical? If so, > then why do they have different names? (I know, marketing droids -- who > specialize in renaming that which already has a name -- rule the universe.) > > Flip-Chip packages not available > > 90 nm process ..... V-II uses 120/150 nm [not that the OEM designing with > FPGAs really cares] -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 57402
"Steven Elzinga" <steven.elzinga@xilinx.com> wrote in message news:3EFC59CE.8090103@xilinx.com... > Ralph, > > Another method (aside from passing an INIT) is to initialize the signal > that will be registered: > > library ieee; > ues ieee.std_logic_1164.all; > > entity ff is > port (d, c : in std_logic; > q : out std_logic); > end entity; > > architecture ff_arch of ff is > signal q_temp : std_logic := '0'; -- XST will pass the proper INIT > value based off of the signal initialization > -- This INIT value is the state to > which the register will power up > -- q_temp is the signal that will be > registered > begin > : > : > > > Steve > Hi Steve, With webpack 5.1 this doesn't seem to work at all. Doing this and then looking at the report file there is no change in the init states of the registers do not change at all. Taking the inferred net names from the synthesis report and using a constraints file worked fine though. Any ideas why your approach wouldn't work for me? Perhaps I am doing something wrong? Thanks RalphArticle: 57403
"Mike Treseler" <tres@tc.fluke.com> wrote in message news:3EFFBEE6.8030400@tc.fluke.com... > > > Ralph Mason wrote: > > > I am not much of a VHDL person, you wouln't by chance know how to set the > > values if the register is declared in a record that in instantiated using > > the above syntax? > > > > type v_reg_type is record > > -- registers > > IOLatch : std_logic_vector(4 downto 0); > > IOLatch2 : std_logic_vector(4 downto 0); > > end record; > > > > signal r, rin : v_reg_type; > > It's just a signal assignment, but > the right hand side value must match the type, for example: > > constant v_reg_init : v_reg_type := > > (IOLatch => ( others => '0'), > IOLatch2 => ( others => '0') > ); > Thanks Mike, that compiles nicely (although doesn't appear to have the desired effect! ) RalphArticle: 57404
Hi Ben, It is possible at the moment to build a Nios for FLEX10KE family with the SOPC builder. But since you talking about 70kgate FLEX I am guessing you are looking at FLEX10K (5.0V) family. This family is not at the moment supported in Quartus hence not supported for Nios. But the new release of Quartus version 3 will have support for 5.0 familys such as flex10k and max7000s (way to go Altera) according to the Altera web page. So my guess is that there will be support for FLEX10K and Nios in the next release. There is no limites on the number of ram needed with Nios, as long as you have more than 2000LE's you should be able to build a decent Nios system in any non CPLD family from Altera. Cheers Fredrik benn686@hotmail.com (Ben Nguyen) wrote in message news:<e604be8.0306281332.23e027a8@posting.google.com>... > Since Altera only sells Stratix, Cyclon, and APEX kits for their Nios, > can Quartus II synthesize the Nios on a small (70k gates) FLEX device? > > Is this possible or does it require too many internal ram blocks/multipliers > that the Flex simply doesnt have? > > Thanks!Article: 57405
Gian wrote: > Hello, <BR> > I am new with FPGA. <BR> > Is it possible to simulate a VLIW multiprocessor using a FPGA devise ? Yes. Not just to simulate one, but run it in reality. > <BR> If yes which system I should use for design and implementation ? <BR> That depends completely on your processor. Is it a smaller one, you need a smaller FPGA. Is it a bigger one, you need a bigger FPGA.... > If not do exist any other system capable to simulate such an architecture Of course, when you just want to simulate it, any hardware simulator will do the job. Regards, MarioArticle: 57406
> > half the slices are NOT full-featured: missing RAM & shift-register > > capability > > This has been discussed with mixed opinions. I think most designers > won't care since using more than half the chip as SRs is unlikely (other > than Ray Andraka). You forgot that RAM16X8S, RAM32X1D, RAM32X4S, RAM32X8S, RAM64X1D, RAM64X2S and RAM128X1S are absent in Spartan3. This is the "problem", not half of the ditributed memory! Luiz Carlos Oenning Martins KHOMP solutionsArticle: 57407
Playstation2 also use a MIPs microprocessor. This one with 128 bit registers! Luiz CarlosArticle: 57408
Hi, I'm a student in computer science and I'm working on the Singular Value Decomposition. I have implementd the Brent Luk Van Loan SVD systolic array using HandelC on FPGA and I'm looking for existing FPGA or VLSI implementations to compare with. Does anyone know about hardware implementaions of the SVD ? Thanks.Article: 57409
Seth <skintigh_spam@yahoo.com> wrote: > I need an FPGA board with a 64-bit 66MHz PCI bus and Linux drivers, > and I need to be able to demo it, and I need it fast. Alpha Data (http://www.alpha-data.com/) provides such boards. We are using a ADM-XPL with a V2P20 and the Linux drivers work fine. CU Felix -- /"\ ASCII ribbon campaign against HTML mail and postings. \ / X "Ich will eigentlich keinen Streit - ich will nur Recht haben" / \ Thorsten Gunkel am 15.01.2000Article: 57410
"P. Prasad" <pprasad@chandra.cse.iitb.ac.in> wrote in message news:Pine.GSO.4.40.0306212128530.29004-100000@chandra.cse.iitb.ac.in... > Hi, > I am working on a HANDELC project on Xilinx FPGA(RC1000 board) and using Celoxica's DK1 environment. I have some doubts regarding HANDELC. I am new to HANDELC and FPGA. > > > The Problem > ----------- > > As the project is getting bigger and bigger, the compilation(synthesis into EDIF) time is taking many hours. So the goal is to reduce the compilation time. > My experience of this is that people don't think enough about hardware. For instance, if you divide by 2^12, I have seen code where people write A = B /4096; This will result in HandelC attempting to synthesise a large divider. This is a) very slow in hardware b) very slow to compile. So my first suggestion is to look through your code for "sillies" like this. You can get big clues by getting the timing and area reports from DK1 and correlating them with the code you've written. (By the way, the above line should be A = B << 12; which essentially synthesises to some wires!) So step one is to check the code for sensible "hardware" style coding. > The approach which I tried to use was to break up the program into smaller parts, compile these into separate EDIFs and hook them into the main HANDELC program using interfaces(ports). So the parts of the program which have already been synthesized into EDIF do not take any time at all thus saving lot of time. > > But I am doing some mistake in my code and I am clueless to what is wrong. Actually I feel that I need to synchronise the EDIF component with the main HANDELC program but don't know how ( maybe use interfaces properly???). I have given below the detailed description of the things I tried. You approach makes sense. Remember that you need to create separate mains (i.e. separate projects) in DK1 to create separate EDIF netlists. Secondly, when you combine everything, you cannot simulate it in the C simulator - you would have to simulate it in the netlist simulator. I guess in your example below, you are talking about "actual hardware" rather than simulation? So step 2 is to check you are using the netlist simulator. Other than that, your code looks sensible, regards Alan -- Alan Fitch HDL Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK Tel: +44 (0)1425 471223 mail: alan.fitch@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 57411
Patrick MacGregor <patrickmacgregor@comcast.net> wrote in message
news:m6qcnRkZZZGrm2ajXTWJig@comcast.com...
> >
> > HDL doesn't force abstration - you can write gate-level HDL. There
> > are illustrious people populating this group who frequently do the
> > "design equivalent of assembly coding" in HDL.
>
> HDL by its very nature is abstraction in the same way that C abstracts
from
> assembly. You describe logic and let some piece of software try to figure
> out what it means.
Just the way a schematic editor has to work out what that connection you've
drawn between two nodes means.
In the following simplest example....
process(clk,reset)
begin
if(reset = '1') then
signal1 <= '0';
signal2 <= '0';
elsif(rising_edge(clk)) then
signal1 <= input;
signal2 <= signal1;
end if;
end process;
...signal1 can be nothing but a wire connection between two registers.
Don't forget an HDL _is_ a Hardware Description Language.
> Well, I guess we mean different things when we describe "simulations".
The
> Quartus tools allow me to simulate the design without having to "model"
> anything. I can take the actual design and throw signals at it directly
to
> see if it is doing what it should. If I've built the circuit according to
> the timing diagrams, I should see resultant waveforms that match what I
> expect. Very simple to follow visually, and it has the added benefit that
> you see a lot more about what is going on in the circuit instead of a
simple
> "pass/fail". BTW, with waveforms you can also do pass/fail tests really,
> really easily and automatically. There is no penalty from using
waveforms,
> but there is a lot to gain. Also, when you debug the board, you should be
> able to match appropriate I/O signals with ones witnessed in simulation.
> Seeing a blinky light turn on doesn't mean a circuit worked. You have to
> know how well it is working, and know what the signal integrity is along
the
> way. This usually means o'scopes, which means, you guessed it, waveforms.
In another part of this thread you mentioned an OC-48 framer you'd
developed.
In the not too distant past I developed a PDH -> STM1 framer capable of all
PDH -> STM1 structures. This was for a piece of test equipment and so was
very
configurable needing significant uP register configuration before anything
sensible would happen. In VHDL I wrote a simple model of the uP to drive my
FPGA uP interface. This model then read a list of instructions (rd/wr),
addresses and values from a text file to allow easy configuration of the
device for different modes of operation. Changing the text file allowed the
tests to be changed without touching the testbench.
I wouldn't like to think about how long this would take trying to set
up waveforms to drive the DUT.
Nial.
------------------------------------------------
Nial Stewart Developments Ltd
FPGA and High Speed Digital Design
www.nialstewartdevelopments.co.uk
Article: 57412Hi, I have read some where, saying that " RESET " signal has to be released with respect the the clock edge, though it is asynchronous RESET? Why is this required? Will the SET and RESET signals of the FFs will Fall under the signals list as D-in for clock timings (Setup / HOLD). Regards, MuthuSArticle: 57413
emanuel stiebler <emu@ecubics.com> wrote: > P.S. Are they any tools out there, which could automagically generate a > "top-level-schematic" out of VHDL code ? "HDL Analyst" (= schematic viewer) in Synplify does a reasonable job. In the latest version (7.3) it can even show you inside imported EDIFs! Hamish -- Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>Article: 57414
William LenihanIii <lenihan3we@earthlink.net> wrote: > half the slices are NOT full-featured: missing RAM & shift-register > capability That sounds a bit disappointing. Which half? > 8 global clocks ..... instead of V-II's 16 2V has 16 BUFGMUXs but you can only use 8 global clocks, or 8 clocks in any one quadrant. Not quite the same. > data sheet mentions BUFGMUX global clock buffer, but not BUFGCE ..... V-II > has both Same hardware in the 2V, so it's probably the same in the 3S. Hamish -- Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>Article: 57415
Eric Smith <eric-no-spam-for-me@brouhaha.com> wrote in message news:<qhhe6gjb2j.fsf@ruckus.brouhaha.com>... > kelvin_xq@hotmail.com (Kelvin Tsai @ Singapore) writes: > > Who uses MIPS? > > I wrote: > > People who don't want to pay the license fees for ARM? > > Kenneth Seefried <ken@seefried.com> writes: > > And would rather pay the license fee to MIPS Technologies? > > > > ObClue: The MIPS instruction set isn't freely available, certain > > aspects of it are patented, and MIPS is very agressive about defending > > their IP. Check any of the folks who've tried to do a public FPGA > > MIPS core. > > Sorry, no shortage of clues about that here. > > But IINM the MIPS license is less expensive than the ARM license. Hence > some people would rather use something other than an ARM, if a less > expensive choice is available. Are you sure you're comparing apples with apples ? MIPS would license you core+ISA or ISA alone. ARM normally gives you core+ISA (unless you are DEC/Intel). Does MIPS32 M4K core license cost significantly less than something like ARM9E Thumb license ?Article: 57416
After the release of Alliance 3 support was no longer offered in the tools for the XC3xxx family. Worse, if you did not happen to have the orignal software that supported these devices, Xilinx would not sell you a copy. Even today we still have product that uses the 3xxx family. I am looking at upgrading our group to Allience 5.x and again see that Xilinx has dropped all support for Spartan. Other families were dropped as well. For use we now would need three copies of software running to support the Xilinx devices we use. Of course, not all the Xilinx tools like to be co-installed. Xilinx, what is your problem? Altera may drop parts, but their router continues to support all of their devices.Article: 57417
After the release of Alliance 3 support was no longer offered in the tools for the XC3xxx family. Worse, if you did not happen to have the orignal software that supported these devices, Xilinx would not sell you a copy. Even today we still have product that uses the 3xxx family. I am looking at upgrading our group to Allience 5.x and again see that Xilinx has dropped all support for Spartan. Other families were dropped as well. For use we now would need three copies of software running to support the Xilinx devices we use. Of course, not all the Xilinx tools like to be co-installed. Xilinx, what is your problem? Altera may drop parts, but their router continues to support all of their devices.Article: 57418
Following PLL was generated with MegaWizard Plug In Manager and compiled (for Stratix) under Quartus 2.2: Input Frequency: 36MHz Dynamic reconfiguration is in use. c0 Clock Multiplication Factor = 158 c0 Clock Division Factor = 36 Other counters are not in use. The compilation report shows: M value = 79 N value = 3 VCO frequency = 948MHz !!!! It looks like Quartus design team is not aware of limitations of the Stratix PLL as listed in the respective datasheet (300 to 800MHz for -5 and -6 grades, 300 to 600MHz for -7 grade). They live under impression that everything up to 1000MHz is o.k. :(Article: 57419
Luiz Carlos wrote: > > > > half the slices are NOT full-featured: missing RAM & shift-register > > > capability > > > > This has been discussed with mixed opinions. I think most designers > > won't care since using more than half the chip as SRs is unlikely (other > > than Ray Andraka). > > You forgot that RAM16X8S, RAM32X1D, RAM32X4S, RAM32X8S, RAM64X1D, > RAM64X2S and RAM128X1S are absent in Spartan3. This is the "problem", > not half of the ditributed memory! Unless I am missing something, I still don't see the issue. My point is that it is a rare design indeed that needs even close to half the LUTs used as distributed RAM or SRs. Most designs use a small number of SRs and RAMs and the rest of the chip is used as logic. If eliminating these functions from the chip reduced the die area significantly, then it was a good thing, IMHO. But from days past I was always told that the routing ate up the lion's share of the chip. The saying goes, "We sell you the routing and give you the logic for free". -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 57420
In article <3F0049BB.5E590511@yahoo.com>, rickman <spamgoeshere4@yahoo.com> wrote: >> You forgot that RAM16X8S, RAM32X1D, RAM32X4S, RAM32X8S, RAM64X1D, >> RAM64X2S and RAM128X1S are absent in Spartan3. This is the "problem", >> not half of the ditributed memory! > >Unless I am missing something, I still don't see the issue. My point is >that it is a rare design indeed that needs even close to half the LUTs >used as distributed RAM or SRs. Most designs use a small number of SRs >and RAMs and the rest of the chip is used as logic. And the wider rams (using all 8 luts in a CLB) can generally be done with a BlockRam without that much wastage for most cases. >If eliminating these functions from the chip reduced the die area >significantly, then it was a good thing, IMHO. But from days past I was >always told that the routing ate up the lion's share of the chip. The >saying goes, "We sell you the routing and give you the logic for free". Well, it doesn't only make the lut smaller, but also saves on a couple of inputs! Removing inputs to a CLB really does save alot, as those are effectively routing. Also, the Spartan 3 doesn't have as rich an interconnect, but Xilinx isn't stating the details yet. Since the parts will be smaller even in the largest case, teh interconnect doesn't HAVE to be as rich anyway. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 57421
Sorry if this is off topic. I'm thinking of pursuing a career in Design w/FPGAs. Can anyone give any advice on: Technology/Tools to Specialize in Job Market status Getting a 'foot in the door' Salaries compared to other fields any other advice Many thanksArticle: 57422
Does anyone have any suggestions/examples for creating an interface between a Xilinx FPGA and NAND flash? I am working for the University of Michigan on the FEGI project, and we are experiencing difficulty communicating between our Spartan IIE FPGA board and the Samsung 128 MB NAND Flash we are using for data storage. We already looked at the Xilinx website and downloaded their one "schematic," but it was not detailed enough for us to make much sense out of it. If anyone here has any quick tips/advice, or an example bit of code that they have written, it would be greatly appreciated if you could send it to us. Thanks.--Matt Matthew John Duane University of Michigan-College of Engineering Computer Engineering Phone Number-School 734-663-9219 mduane@engin.umich.edu "Just imagine if your name was Anonymous. You'd get credit for everything no one wanted credit for."Article: 57423
> Hi,
Hello!
>
> I have read some where, saying that " RESET " signal has to be
> released with respect the the clock edge, though it is asynchronous
> RESET?
Below is example of asynchronous and synchronous reset:
(I hope you know something about VHDL)
ASyn: process (CLK, RESET)
begin
if RESET='1' then
-- reset or set your stuff
elsif rising_edge(CLK) then
-- something
end if;
end process;
Syn: process (CLK)
begin
if rising_edge(CLK) then
if RESET='1' then
-- reset or set your stuff
else
-- something
end if;
end if;
end process;
Good Luck
Arek
Article: 57424Morten, This might help. It might not. In one of my designs, I would get inconsistend PAR results when using different effort levels. It would work at effort level = 2 and not work at all at higher effort levels. Sounds similar to your problem. I was doing a design using an ENGINEERING SAMPLE (ES) of a Virtex2, NOT A PRODUCTION SAMPLE. The engineering samples of the Virtex2 do not have the same routing resources as the production samples do. It turns out that in the ES Virtex2, you the DCMs must be placed IN THE SAME QUADRANT as the input clock buffer. Some versions of Design Manager do not check for this, so you must put a locational constraint on the DCMs if you are using a version that does not. This is a bug in Design Manager (which it sounds like you are using). When using higher effort levels, timing would improve, but the DCMs would be placed at invalid locations. There is an app not at: http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=11756 Hope it helps. Ed "Morten Leikvoll" <mleikvol@online.nospam> wrote in message news:<h5_Ja.8835$Hb.155017@news4.e.nsc.no>... > When I implement my design using max effort (=5), and the timing analyser > reports no timing errors, the implemented design does not work at all (very > buggy!). I am using several clock nets, but I make sure (I hope) that all > domains are crossed in a safe way. (The design works fine at effort 4, even > if some of the timings are reported bad). I know others have had this > problem. (All my small state machines are binary) > > Does anyone know what the actual problem with effort 5 is: I'd like to try > tweaking my design around those problems. > > Thanks > Morten Leikvoll
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