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Some great advice here. Any recommendations for those providing this service in the Philadelphia area? -- Greg readgc.invalid@hotmail.com.invalid (Remove the '.invalid' twice to send Email) "Hal Murray" <hmurray@suespammers.org> wrote in message news:v65p414b85f2ff@corp.supernews.com... > If you had asked me a couple of years ago, I would have assumed > the right answer was to do it inhouse. The current trend seems > to be to outsource things, but that's just my view. > > Aside from asking here, I'd suggest asking around at work. > I think things like this are much easier to learn if you have > somebody nearby who is willing to answer questions and/or > give you some hints and checking. > > My batting average for outsourcing is mixed. We had two > big boards outsourced (both design and layout) and I wasn't > happy with the layout. I think that reflects more on the > overall project rather than the idea of outsourcing the layout. > (The guy who did the layout wasn't that sharp and the guys > who should have been checking/helping him didn't do a good > job. And somebody wanted it yesterday...) > > > I've outsourced the layout of two boards localy with good > results. One was via phone and the other was face to face. > They probably did as good a job as I could have done. > I'd happily do it again. > > Here is my checklist for outsourcing a PCB: > > Make a packet of the mechanical pages from the data sheets. > Scribble on the top the name you used in the libraries. > Be prepared to make a pass through your libaries tweaking > the names you used for the footprints. They might > want "R0603" where you used "0603". > > Make a mechanical drawing/sketch of the board outline and > mounting holes. > Add to that a rough placement of the big parts, especially > connectors. (Maybe their location is firm rather than rough.) > Make a list of the layers (stackup) and sketch of the plane cuts. > It's OK if the above are rough. Tell them what is firm. > Should they add layers or make the board bigger to get > the job done sooner and cleaner? > > Make a list of all the routing constraints by signal name: > differential pairs > controlled impedance > fat traces (for power) > ... > > Take a set of schematics and expect to sit with the layout > guy while he does the initial placement. (He will dump > all the parts next to the board and then move them onto > the board.) This is obviously easier if he is located > near enough so you can go there. > Show him where the differential pairs go. > > In a day or so, you will get back a trial layout. > If that's OK, you soon get a routed board. > I think all the board design packages include a free > viewer. You get to stare at it for a while and make > change requests/suggestions. > Expect to iterate a few times making minor tweaks. > A face to face session may be appropriate. > > > -- > The suespammers.org mail server is located in California. So are all my > other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited > commercial e-mail to my suespammers.org address or any of my other addresses. > These are my opinions, not necessarily my employer's. I hate spam. >Article: 53076
> > * Are there high density non-volatile FPGAs? > > Apparently not yet. I wondered myself why there is no flash included. > I heard somewhere that Altera is going to do a single chip with both an FPGA and a flash die for Cyclone components .Article: 53077
chris.rosewarne@calyptech.com (Chris Rosewarne) wrote in message news:<ef33e8a7.0303021535.2765a886@posting.google.com>... > "Sam Duncan" <damn_spam2001@yahoo.co.uk> wrote in message news:<b3nmd8$1osp5j$1@ID-167554.news.dfncis.de>... > > Hi > > > > I'm using an XC2V1000 and trying to drive two global clock nets at different > > speeds (using DCMs), using only one clock input pin. I get errors from > > ngdbuild if I try to drive two IBUFG's from the same pad. If I drive one > > IBUFG and split the output to two DCM's, the levels of logic reported on my > > clock net (post place and route) increase from 2 to 19. Is it possible to > > drive two DCM's and two clock nets from one input pin, or should there be a > > separate input for every DCM/clock net? > > > > Many thanks > > > > Sam > Sam, > > The way to do it is to drive the DCM #2 with the output from DCM #1. > DCM #1 is driven by the IBUFG in this case. > > regards, > Chris > Howdy, I have found that cascading DCMs is typically only necessary if you have either exceeded the divide/multiply abilities of the DCM, or if you require a derived clock to be locked to a divided clock (because there is no phase guarantee when using two DCM's in parallel to do dividing). To answer the original posters question, I have run 3 DCM's off a single global input. I didn't even have to call out an IBUFG as I recall (Synplify did it, I assume). Be aware that engineering sample Virtex-II's had restrictions on which GBUF's could drive which DCM's - since I assume you are using production parts, it seem unlikely that could be what you are up against. But perhaps you still have the _ES environment variable set? MarcArticle: 53078
[This followup was posted to comp.arch.fpga and a copy was sent to the cited author.] In article <4079434d.0302260716.651d95e7@posting.google.com>, jlcarret@teleline.es says... > Hi, > > How I can program an Altera EPC1 with a ByteBlaster cable? > I want to do an adapter to program it, but I canīt find any document > with the eprom program method. > I have not an external programmer. Can anybody help me? > > Thanks. > If I remember correctly, the EPC1 is not ISP'able with a ByteBlaster. The EPC2 is, but not the EPC1. -- Greg Deuerling Fermi National Accelerator Laboratory P.O.Box 500 MS368 Batavia, IL 60510 (630)840-4629 FAX (630)840-5406 Electronic Systems Engineering Group Work: egads@fnal.govArticle: 53079
I am using Aldec Active HDL for design entry and simulation for synthesis I use LeonardoSpectrum and for Implementation Billing Alliance I have some basic quires 1)Actually what happens during the functional simulation of a design.Is the design get converted into gates or a software based simulation 2)What happens while synthesizing using LeonardoSpectrum.Is the generated output file is the actual design represented in the form of basic cells we have to enter the target (FPGA family) before synthesis why is it necessary--is synthesized output is specific to a target.There is a schematic viewer in the LeonardoSpectrum how can I use it to found out what the tool do to my design. 3)I am aware of IP cores available in the netlist forms today how they are generated .I think they should not specific for a target what may be level of descriptions in these files is they are gate level representations 4)What actually the Implementation tool does 5)Suppose I want to make an ASIC out of my synthesized output from LeonardoSpectrum is it possible 6) What is post synthesis simulation--Is we use the actual gate level design in simulation is it mainly concentrate on timing issuesArticle: 53080
Anybody familiar with the term Bus Functional Model (BFM).Is any BFM is available for AHB (free or low cost).Is the devlopment of a BFM is complex . CommentsArticle: 53081
I'd be surprised if your one-off board winds up being cheaper than all
the demo boards out there. There are a few, like the older insight
SpartanII board that cost not much more than what it costs to get the
components in single quantities. If you can live with an older device,
you might be able to find one that someone is trying to unload.
ron wrote:
> I am looking for demo board schematic for small gate count (cheaper)
> CPLDs and Spartan FPGAs. I was able to see some at www.opencores.org
> but the FPGAs were quite expensive. Do you know where I can get this?
> I'm planning to make my own board since I cannot afford to buy demo
> board. THank you
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 53082A BFM is a model that describes the behavior of the external bus of a chip. "geeko" <jibin@ushustech.com> wrote in message news:b3vmsb$1phmjl$1@ID-159027.news.dfncis.de... > Anybody familiar with the term Bus Functional Model (BFM).Is any BFM is > available for AHB (free or low cost).Is the devlopment of a BFM is complex . > Comments > > > > > >Article: 53083
Are the samples the filter receives in the actual hardware the same as the samples you used for the simulation? What is the frequency of your input? What kind of FIR filter (LPF, BPF, HPF) are you designing and what is the cutoff frequency? Jim "Noddy" <g9731642@campus.ru.ac.za> wrote in message news:1046677992.102335@skink.ru.ac.za... > I posted a question (Ref: SDA FIR Filter) regarding the refusal of my SDA > FIR filter to work in hardware, although it works perfectly in simulation. I > noticed that in the CORE generator GUI, the latency (startup latency I > presume) was 9 clock cycles. I am feeding the filter 4 bit input samples > every 8 clock cycles, so should get an output every 4 clock cycles. However, > my complaint was that I am only getting a DC output in hardware, and am now > wondering whether the fact that I am giving samples every 8 clock cycles > from startup might have an effect on the filter, since the latency is 9 > clock cycles... to me this is not possible, but I am getting desperate!!! > > adrian > >Article: 53084
Hi Ron, Have a look at my Leon board at www.ht-lab.com . I would also suggest a quick look at : http://www.burched.biz/products.html http://www.xess.com/ http://www.associatedpro.com/. before building your own board :-) Good luck, Hans. "ron" <rathanon99@yahoo.com> wrote in message news:c661162.0303022311.3d87a075@posting.google.com... > I am looking for demo board schematic for small gate count (cheaper) > CPLDs and Spartan FPGAs. I was able to see some at www.opencores.org > but the FPGAs were quite expensive. Do you know where I can get this? > I'm planning to make my own board since I cannot afford to buy demo > board. THank youArticle: 53085
check out this link. It has some info on BFM's http://www.tempusf.com/DesignCon_2002.pdf cheers Puneet geeko wrote: > Anybody familiar with the term Bus Functional Model (BFM).Is any BFM is > available for AHB (free or low cost).Is the devlopment of a BFM is complex . > Comments > > > > > >Article: 53086
Hello everybody, We want our 16 bit Nios to execute code from a 8 bit wide external SRAM. The high speed parts should run from internal memory. Ist that possible ? I think it *must* be possible when we connect the SRAM with our own VHLD code to the Avalon Bus. But is it also possible without writing own logic ? Thanks to everybody reading this :) By TomArticle: 53087
In article <c661162.0303022311.3d87a075@posting.google.com>, ron <rathanon99@yahoo.com> wrote: >I am looking for demo board schematic for small gate count (cheaper) >CPLDs and Spartan FPGAs. I was able to see some at www.opencores.org >but the FPGAs were quite expensive. Do you know where I can get this? >I'm planning to make my own board since I cannot afford to buy demo >board. THank you Unless there is no board which meets your criteria (eg, it might be "Spartan IIe/Cyclone class part with a quad ethernet PHY" or something similar, or you want to ramp it up into volume production), you really should look at an off the shelf board. Others in the list have pointed to many different choices. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 53088
wangmanxi@yahoo.com (siriuswmx) wrote in message news:<4528663b.0303022311.409be59b@posting.google.com>... > Thank you,rene :) > as you say, i ask my colleagues for help, but i still have some > puzzles: > 1. What are the differences between the chips of altera and xilinix ? > at the aspects of power dissipation, speed and price. > 2. i feel that QUARTUSII is easier to use than ISE, but i also found > that many engineers preferred ISE, why? Both companies claim to have the lowest cost FPGAs. 8-) I haven't used Altera, so I can't make a good comparison. But, installing ISE Webpack was very easy. I got the CD and a product key from Xilinx for free, and it will run forever. The next thing I knew I was pushing buttons and synthesizing and fitting VHDL. Too cool. Altera uses a third party synthesis tool with Quartus, so licensing isn't so simple. AKAIK the Mentor evaluation license lasts for 30 days.Article: 53089
geeko wrote:
> 1)Actually what happens during the functional simulation of a design.Is the
> design get converted into gates or a software based simulation.
No conversion. The code is used directly.
> 2)What happens while synthesizing using LeonardoSpectrum.Is the generated
> output file is the actual design represented in the form of basic cells
Yes
> we have to enter the target (FPGA family) before synthesis why is it
> necessary--is synthesized output is specific to a target.
If you load a target library (or use the GUI) yes.
If you write a script, you can default the library
and get basic gates and flops.
> There is a
> schematic viewer in the
> LeonardoSpectrum how can I use it to found out what the tool do to my
> design.
After a successful synthesis you can view a netlist
of logic blocks or a gates and flops view.
> 3)I am aware of IP cores available in the netlist forms today how they are
> generated .I think they should not specific for a target what may be level
> of descriptions in these files is they are gate level representations
A netlist core is cheaper than a source code core.
Both are available.
> 4)What actually the Implementation tool does
Leo makes a primitive netlist that sims the same as your code.
> 5)Suppose I want to make an ASIC out of my synthesized output from
> LeonardoSpectrum is it possible
Yes. You need a library from the ASIC vendor.
> 6) What is post synthesis simulation--Is we use the actual gate level
> design in simulation is it mainly concentrate on timing issues
For synchronous designs it is mainly to verify synthesis.
-- Mike Treseler
Article: 53090Hi, I need to be able to programme the following parts on a board :- Altera EP2LC20 (I think that's the configuration device) Altera EP20K100E (FPGA) I have the .pof file from the guy who did the design and I'm looking for the simplest way of programming these parts through the ISP connector (I don't really want to get into the design software). I have built a ByteBlasterMV cable using the design on the Altera site. Could someone advise as to which software to download and what the settings should be? Many thanks Simon Fisher Swansea UKArticle: 53091
I'm using the LeonardoSpectrum that comes with the Altera software subscription. Is there a way to run it on the command line without going through the GUI? (Mostly I want to use a Makefile to manage the synthesis flow.) Thanks, LisArticle: 53093
lishu99@yahoo.com (Lis Hu) writes: > I'm using the LeonardoSpectrum that comes with the Altera software > subscription. Is there a way to run it on the command line without > going through the GUI? (Mostly I want to use a Makefile to manage > the synthesis flow.) Yes. You can write Tcl scripts to control Leonardo. I've only used it under Solaris, but I guess the same feature would exist under Windows. Consult your documentation. DUI means Driving Under Influence - what does GUI mean :-) Petter -- ________________________________________________________________________ Petter Gustad 8'h2B | ~8'h2B http://www.gustad.com/petterArticle: 53094
Lis Hu wrote: > I'm using the LeonardoSpectrum that comes with the Altera software > subscription. Is there a way to run it on the command line without > going through the GUI? (Mostly I want to use a Makefile to manage > the synthesis flow.) > > Thanks, > Lis I assume you mean the OS shell. On the unix version you can do something like: spectrum inc.vhd inc.edf -product=ls2 -file=myscript.tcl Don't know if the spectrum program works from DOS. What you *can* do is put a bunch of .tcl scripts in your project directory and do a File, Run Script, ... from the leo GUI, and click on the one you want. -- Mike TreselerArticle: 53095
Hi Mike, After many calls, I was never able to actually talk to anyone at the company or get anyone to return my calls. That's a bad sign as far as I'm concerned, so I'd try someone else. -robert Michael Nicklas wrote: > Hi > > I'm thinking of investing in the Avnet Xilinx Virtex-E development kit and > wondered if anybody had any previous experience with them and any opinions > of them as a company, in terms of product quality, tech support etc. > > Much appreciated. > > -- > Cheers! > > Mike > > >Article: 53096
Robert, Why would you call Avnet when the Xilinx University program supports Berkeley directly? Remember that Avnet is a "for profit" business, and they will concentrate on customers (because that is how we all make money and stay in business). For University support, there is a whole other organization set up just for that reason (so we can support reseach, and student learning, without impacting our sales partners and our day to day business). In fact, universities and schools are encouraged to use the newsgroup that is set up just for them....to obtain support on any technical questions. http://www.xilinx.com/univ/ Austin Robert Abiad wrote: > Hi Mike, > > After many calls, I was never able to actually talk to anyone at the > company or get anyone to return my calls. That's a bad sign as far as > I'm concerned, so I'd try someone else. > > -robert > > Michael Nicklas wrote: > > > Hi > > > > I'm thinking of investing in the Avnet Xilinx Virtex-E development kit and > > wondered if anybody had any previous experience with them and any opinions > > of them as a company, in terms of product quality, tech support etc. > > > > Much appreciated. > > > > -- > > Cheers! > > > > Mike > > > > > >Article: 53097
FYI - I found out that there are restrictions on IBUFG to DCM routings in the Virtex2. The virtex2 handbook says that an IBUFG can feed any DCM on the same edge of the device. It turns out that in "engineering samples" of the virtex2, you can only feed DCMs in the same quadrant. Xilinx PAR 4.2i did not account for this and placed a DCM on the same edge as the corresponding IBUFG, but on the opposite quadrant. More info at: http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=11756 Ed chris.rosewarne@calyptech.com (Chris Rosewarne) wrote in message news:<ef33e8a7.0303021546.536cdeaf@posting.google.com>... > Ed, > > This would be a timing issue as the guided P&R is reusing the old > placement and routing information where it can, which sets the timing > characteristics of the design. Try running an unconstrained path > report (trce -u) to check that the timing constraints are cover all > relevant paths. > > regards, > Chris > > agunos@cox.net (ed) wrote in message news:<c23bf65e.0302280902.4bdcdf3a@posting.google.com>... > > I have a design in a virtex2 which connects to a PCI interface chip > > (plx9080). With all other things begin equal (same edf file, same ucf > > file, same effort level or higher), the latest revision to my design > > only works (talks to the PCI bus) if I perform a guided place and > > route with a guide file from the previous working implementaion. I've > > ran the design without the par guide file AND with higher timing > > constraints succesfully and it still does not work. Without probing > > the bus signals, can I infer anything from this? Basically, can I > > reasonably say that this is not a timing issue? And if not, what else > > would a guided par affect? > > > > Thanks, > > EdArticle: 53098
Nicholas, I don't know what your experience is with building PCBs, but if you haven't done something like this before you should know what you're up against. Even if you outsource it, you'll need some background to check out your supplier and make sure they're doing a good job. I'd recommend taking a look at "High Speed Digital System Design" by Hall, Hall, and McCall and/or "High Speed Digital Design" by Johnson and Graham. I've heard the Hall, Hall, McCall is the better of the two (at least it is more recent), but I haven't read enough of it to judge. As for tools, if you are doing it for the university, you should check out Mentor's Higher Education Program. They offer a lot for little money. Try this: http://www.mentor.com/partners/hep/na1_app.html Good luck, -robert Nicholas C. Weaver wrote: > I'm in the very VERY preliminary planning stages, and looking to do > one or more FPGA board designs with multiple Gb (1000-baseSX) ports & > tranceivers. Thus there will be multiple 1.25 gigabaud differential > pair traces running around, between the FPGA and the transcievers. > > Whats the general (rough order ballpark) figure for an ousourced > design consisting of an FPGA, 8 transceivers, a DDR SO-DIMM slot, and > a compact flash/bootup? > > Similarly, if doing it in-house, what are the prefered tool-suites? > Is it the cadence branded tools? The cadence buyout ORCAD flow? > Mentor Graphics flow? > > Thanks. >Article: 53099
Hi Tom, Yes this certainly is possible and doesn't require intervention on your part. The Avalon bus interface supports something called "dynamic bus sizing" which allows wide masters to access narrow slaves - the logic generated in the SOPC Builder tool will automatically generate two reads, for example, if your 16-bit Nios requests 16-bits of data (or an instruction) from the 8-bit memory. A byte wide access from the CPU would be handled in the expected way, with data coming back a clock sooner. This operation is transparent to the user, and scales with any combination of master & slave widths (a 32-bit CPU can also connect to 8-bit memory in this way). You might wonder what the alternative to dynamic bus sizing is - its called "native alignment" in the Avalon spec and is useful for addressing register slaves where the designer needs one, and only one, access to the peripheral when addressed by the CPU. If you're using Nios 2.x, I'm assuming you'll add the memory interface using the "Interface to User Logic" GUI - while adding your memory interface, select "Use device as memory" under 'Avalon Slave' and dynamic bus sizing will be activated. We changed this slightly in Nios 3.0... in that case you'd select "Avalon Memory Slave" when starting the wizard. For more detail on this, check out the Avalon Bus Specification, under the section entitled "Avalon Bus Address Alignment Options": http://www.altera.com/literature/manual/mnl_avalon_bus.pdf Regards, Jesse Kempa Embedded Apps. Engr. Altera jkempa @ altera . com (nospam: remove spaces) thomas.lehner@contec.at (Thomas Lehner) wrote in message news:<4126d727.0303030912.624075f4@posting.google.com>... > Hello everybody, > > We want our 16 bit Nios to execute code from a 8 bit wide external > SRAM. The high speed parts should run from internal memory. > > Ist that possible ? I think it *must* be possible when we connect the > SRAM with our own VHLD code to the Avalon Bus. But is it also possible > without writing own logic ? > > Thanks to everybody reading this :) > > By > > Tom
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Compare FPGA features and resources
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