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Better for power consumption? Probably not. Better for estimating power,
maybe, but not without a lot of work.
Glen Herrmannsfeldt wrote:
>
>
> Well, I was trying to convince someone that an FPGA based design would be
> better than an ASIC design, before either one was built.
>
> > "They that give up essential liberty to obtain a little
> > temporary safety deserve neither liberty nor safety."
> > -Benjamin Franklin, 1759
>
> -- glen
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 55401> Andreas Wortmann wrote: > > > hi, > > > > i start using the rocket-io transceiver macro on the xilinx virtex-II pro > > device. does anybody have > > - or know of - some simple sample vhdl-code to start out with ? at this > > stage i do not aim at a specific > > transmission protocol, but i want to prove the device working. are there > > other important things i have > > to account for ? > > > > thanks, > > andreas Xilinx has a demo board/design for the RocketIO MGT available at - http://www.xilinx.com/ipcenter/catalog/search/reference/reference_xapp661_rocketio_transceiver.htm This is a pretty good reference design for anyone starting on RocketIO. -Vikram.Article: 55402
Sorry for not posting to the original message - newsgroup troubles at work. I just saw this part and the newsgroup thread wasn't that old... The Maxim MAX2150: "The super-high-resolution sigma-delta fractional-N synthesizer is capable of better than 50mHz resolution when used with a 10MHz reference. Other features include fully differential I/Q modulation inputs, an internal LO buffer, and a 50 wideband output driver amplifier" http://www.maxim-ic.com/quick_view2.cfm/qv_pk/3430/ln/en > hmurray@suespammers.org (Hal Murray) wrote in message news:<vb8rj1h4742fe1@corp.supernews.com>... > > Is there any obvious PLL chip to use with an FPGA? I want to do > > things like generate 100.0003001 MHz from 10 MHz. (Or generate > > 100 MHz from 9.999999371 MHz) begin 666 ohm.gif M1TE&.#EA# `)`)$#`!(2$HF)B<G)R?___R'Y! $```,`+ `````,``D```(@ BG!498BW QHL&A#8"<!#/TW&4A6E>^!G+Q%X9``L/?!4`.P`` ` endArticle: 55403
I was referring to FPGAs, not CPLDs. THe FPGA boards typically come with an
FPGA, power supply regulators and perhaps a brick, interfaces, PROM etc. If
you are really bent on getting a 50K device in hobby package, use the 144 pin
tqfp package. With a few minutes practice, you can solder these onto a board
with a decent soldering iron. They really are no harder to work with than SOIC
packages. As I mentioned earlier, you can also mount parts on an adapter such
as those made by Ironwood if you don't mind spending more for the adapter than
you did for the chip. As for the robot peripherals, I think you'd find
yourself bumping into pin limits pretty quickly in the small pinout devices.
Also, BGAs can work well for low pinout applications on two layer boards. In
that case, select your I/O to be on the outer ring, to keep the signal routing
on the top layer. Power goes to inner ring pins, but that can be rotued on the
bottom layer with vias. You can mount the BGAs using a toaster oven or with a
hot air gun for one up stuff (see the numerous threads that have appeared over
the years here).
Torquemada wrote:
> I have to agree with you. I'm definitely interested in accessible FPGAs
> for hobbyists. Robotics is a pretty popular hobby these days and most
> amateur projects are centred on microcontroller devices. But CPLDs
> and FPGAs are in many ways much more logical. With a microcontroller,
> dealing with multiple tasks with interrupts can be a headache.
> With a programmable logic device the design flows much more naturally
> and dealing with asynchronous events like collisions with a wall becomes
> much easier. But there are few devices that are easy for hobbyists to
> physically work with. The XCR3064XL is OK as you can get 0.1"
> spacing PLCC44 sockets. (Incidentally the lowest cost board for this is
> about $50 but the component itself costs only $3 so that stuff about
> the board being as cheap as the parts is plainly false. I built a working
> programmer for one of these things on a breadboard for about $4).
> But at 1600 gates there's a limit to how much behaviour you can get. I'd
> love to see a 50k gate device, say, in a similar package. There'd be plenty
> of I/O for robot peripherals and enough logic to have it do some fun stuff.
> --
> Torque
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 55404
>
If you really believe that the hobbyist market is a huge untapped market, why
don't you get a BGA or TQFP to dip adapter board made and assembled in some
reasonable quantity and sell them? There are plenty of fab/assembly houses
that are hungry for work right now, so I'm sure you could wrangle something. I
would at least put bypass caps on the adapter module. You might also consider
a socketed serial prom so as to not use up valuable pins for programming.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 55405Hi, I would like to design one fixed FPGA to program (and reprogram) other FPGAs, directed by the CPU. I asked Xilinx and they said that they didn't have any currently available functional simulation models for either the SelectMAP configuration interface or the System ACE MPU port, two mechanisms I'm considering. Does anyone know where any non-official but used & tested functional simulation models are available? Thanks, Amy MitbyArticle: 55406
> If you really believe that the hobbyist market is a huge untapped market, why > don't you get a BGA or TQFP to dip adapter board made and assembled in some > reasonable quantity and sell them? There are plenty of fab/assembly houses > that are hungry for work right now, so I'm sure you could wrangle something. I > would at least put bypass caps on the adapter module. You might also consider > a socketed serial prom so as to not use up valuable pins for programming. If I didn't already have a decently paying job that takes up most of my day I'd do exactly this! :-) I'll have to see if I can get some prototypes working... -- TorqueArticle: 55407
Well, in case anybody is interested - it seems that memec has a real nice s3 board (practically) available now. According to this fellow I spoke to the other day they'll be delivering them in a couple of months (in Scandinavia at least).Article: 55408
Hi! We have a prototype board with an XC4000 FPGA on int, we are trying to program it using the serial slave mode, we have the traces on the board for every pin in the parallel III cable, except the DONE pin. Theoretically the DONE pin only lets the programmer know that the devide was configured correctly right? The foundation tools' programmer refuses to even download the code because it claims it can not see a low DONE signal (I assume the signal transitions from hi to low while the device is being programmed, and back to low to hi once it is programmed). Is there a way of telling the programmer in the foundation tools to ignore the DONE signal (I have not found it), or do we need to "fool" the program by generating a DONE signal on our own using some discrete logic. Or does anyone know of a freeware program that downloads the bitstream files down the parallel cable, and that comes with source so that it can be modified to ignore DONE? Please any help will be very very appreciated!!! We do not want to resubmit the proto board just because a single signal went MIA!!!Article: 55409
christian sternell <christian@navitronic.dk> wrote: : Well, in case anybody is interested - it seems that memec has a real : nice s3 board (practically) available now. According to this fellow I : spoke to the other day they'll be delivering them in a couple of : months (in Scandinavia at least). "(practically) available now" ... "in a couple of months" :-( -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 55410
Thanks for all the suggestions/ideas. Yes, the context is GPS and a very good crystal. Yes, I'm willing to wait a minute for it to lock up and I'm willing to consider using a huge cap. This is a hobby/hack, so the "specs" get adjusted to fit budget and whatever seems neat at the time. (Or it may never get off the drawing board.) I was sloppy with the number of digits I typed in, but the idea is that I wanted lots of low order bits. Should be easy to do in an FPGA. The good/fancy crystals I've seen come with an analog input to tweak the frequency. With a good crystal, you end up needing a 16 bit D/A and the crystal aging has to be measured and factored in when coasting if the GPS runs out of satellites. I have a HP Z3801A GPS/crystal box. Ask Google if you are a geek and like neat toys. They are surplus from the cell phone people. The basic idea is to build a Unix time-of-day clock in a FPGA on PCI. That's 32 bits of microseconds-in-this-second, and 32 bits of seconds since 19xx. I've got a real-good 10 MHz clock so that much should be reasonable. 32 bits will hold nanoseconds-in-this-second for more accurate timimg. So a faster clock is interesting. (No real need, just feels like fun.) First idea is just a 10x PLL, or something like that to get a few more low order bits. (No point in going crazy. PCI is only 33 MHz.) Second idea is to put a GPS unit and good crystal on the card too. OEM GPS units are under $100. But round up for an antenna. Good crystals are now available that will fit on a PCI card. (Maybe not quite within all the rules, but close enough for this hack.) I'm not sure about price yet. But the general idea should still work with a not super fantastic crystal. So then I got to thinking about doing the corrections in the FPGA rather than tweaking the analog knob. Now I have another batch of ideas to consider... The board will be mostly empty. It's free to add a few more footprints that don't get used. Thanks again. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 55411
Hal Murray wrote: > > Thanks for all the suggestions/ideas. > > Yes, the context is GPS and a very good crystal. > > Yes, I'm willing to wait a minute for it to lock up > and I'm willing to consider using a huge cap. > > This is a hobby/hack, so the "specs" get adjusted to > fit budget and whatever seems neat at the time. (Or it > may never get off the drawing board.) > > I was sloppy with the number of digits I typed in, but the idea > is that I wanted lots of low order bits. Should be easy to do > in an FPGA. > > The good/fancy crystals I've seen come with an analog input > to tweak the frequency. With a good crystal, you end up needing > a 16 bit D/A and the crystal aging has to be measured and factored > in when coasting if the GPS runs out of satellites. > > I have a HP Z3801A GPS/crystal box. Ask Google if you > are a geek and like neat toys. They are surplus from the > cell phone people. > > The basic idea is to build a Unix time-of-day clock in a FPGA on > PCI. That's 32 bits of microseconds-in-this-second, and 32 bits > of seconds since 19xx. I've got a real-good 10 MHz clock so that > much should be reasonable. > > 32 bits will hold nanoseconds-in-this-second for more accurate > timimg. So a faster clock is interesting. (No real need, > just feels like fun.) First idea is just a 10x PLL, or something > like that to get a few more low order bits. > (No point in going crazy. PCI is only 33 MHz.) > > Second idea is to put a GPS unit and good crystal on the card too. > > OEM GPS units are under $100. But round up for an antenna. > > Good crystals are now available that will fit on a PCI card. > (Maybe not quite within all the rules, but close enough for > this hack.) I'm not sure about price yet. But the general > idea should still work with a not super fantastic crystal. > > So then I got to thinking about doing the corrections > in the FPGA rather than tweaking the analog knob. > > Now I have another batch of ideas to consider... > The board will be mostly empty. It's free to add a few > more footprints that don't get used. > > Thanks again. Since this is a corrected timebase, that will mostly be extrnally locked, look at the digital calib schemes used on some watch chips. They use a fixup scheme, of "so many LSB's" to nudge the timebase. - No caps, or analog, needed. eg I asssume you will want seconds to be as precise over 12 months as possible, but are perhaps not so worried if the counts per millisecond deviates by some few ppm. Also look at the Dual Crystal precision oscillators. Rather than a thermister and xtal, they use two crystals of different cuts, and the delta Freq gives the nett effective temperature. Measuring two Freqs sounds like a FPGA task :) -jgArticle: 55412
On Sun, 04 May 2003 18:26:28 GMT, "FPGA user" <nospam@aol.com> wrote: >Hi, > >Has anyone used LPM_ROM megafunctions in an EP1K50? They do NOT seem to >work in simulation. However, an EP1K30 or an EP1K100 DOES work. > >I'm using the latest version of MaxPlus II, and created a design with only >that megafunction, unclocked, with addr in/data out ports, and an >initialization file. I organized the part as 64 16 bit words. > >Compilling and changing nothing but the device shows up the problem. > > >Thanks! > > I have used LPM_ROM for a large(wide) microcode design, I recall it fitted/worked better if I split the ROMs into 8 bit chunks, so two 64x8 roms may be better. I think I retrospectively read something in the altera literature to do this ... YMMV Email me if still having probs as I probably have old code on my website www.eej.ulst.ac.uk try IJ.McCrum as my email username and ulster.ac.uk ad my email domain. Regards Ian McCrum, MI5AFLArticle: 55413
(I posted a similar message before whose subject was "RF transmitters/receivers with Xilinx Xtreme DSP Kit" - I am reposting with better details of what I need - this is not strictly do do with FPGAs but I hope some of you guys may have experience with this stuff - I may well do the I/Q modulation/demodulation on FPGA anyway so it is somewhat relevant... ;-) ) Hello, I am looking for several pieces of off the shelf equipment to perform RF transmission and reception across a table-top/room. The gear can therefore be very low power. The RF carrier frequency is flexible and a few hundred MHz would do although GHz would be nice - I guess if I track down a range of suitable equipment I will be able to trade Hz against cash! I have seen quite a lot of expensive and complicated pieces of equipment that will do the simple tasks I require but I cannot justify the cost when all I really need is some sin/cos mixing and modulation. I have searched some online catalogues and spoken to reps from various companies with no success so far - surely these simple boxes must exist to buy! Anyway, here is the list: TX Box 1: Inputs: 1 BNC input carrying an IF modulated signal This box just needs to AM modulate the IF input to an RF frequency and possibly perform some sort of filtering to reject images? Outputs: 1 - something suitable for feeding to an antenna...? not quite sure RX Box 2: Inputs: suitable connector coming from an antenna I guess This box needs to demodulate the RF signal from box 1 and output it at some IF or baseband. This box would need to do suitable filtering to demodulate with no problems. Outputs: 1 BNC output. TX Box 3: Inputs: 2 BNC inputs carrying I and Q signals at baseband/IF This box needs to mix the I/Q signals with cos/sin waves and add them together to produce an RF signal Outputs: 1 - something suitable for feeding to an antenna RX Box 4: Inputs: suitable connector coming from an antenna This box needs to mix the input with a cosine to get the I output and mix the input with a sine to get the Q output. This box would also need to do suitable filtering to demodulate with no problems. Outputs: 2 BNC outputs carrying I and Q. Some of the boxes may not need filters as the ADCs/DACs I will be using can possibly do this job depending on the specs. Any pointers towards suitable gear/places to buy it would be very much appreciated! Thanks in advance for your time, Ken -- To reply by email, please remove the _MENOWANTSPAM from my email address. -- To reply by email, please remove the _MENOWANTSPAM from my email address.Article: 55414
"Ken" <aeu96186_MENOWANTSPAM@yahoo.co.uk> wrote in message news:b9ams2$bjb$1@dennis.cc.strath.ac.uk... > (I posted a similar message before whose subject was "RF > transmitters/receivers with Xilinx Xtreme DSP Kit" - I am reposting with > better details of what I need - this is not strictly do do with FPGAs but I > hope some of you guys may have experience with this stuff - I may well do > the I/Q modulation/demodulation on FPGA anyway so it is somewhat relevant... > ;-) ) > > > > Hello, > > I am looking for several pieces of off the shelf equipment to perform RF > transmission and reception across a table-top/room. The gear can therefore > be very low power. The RF carrier frequency is flexible and a few hundred > MHz would do although GHz would be nice - I guess if I track down a range of > suitable equipment I will be able to trade Hz against cash! I've got a simple receiver design on my web site that will do conversion from up to 500 MHz down to baseband I and Q, if you use two of them with a quadrature oscillator. It's quite easy to make with my PCB design. Leon -- Leon Heller, G1HSM leon_heller@hotmail.com http://www.geocities.com/leon_hellerArticle: 55415
Hi all, I have problem with erasing XCR3064XL. I'm programming it from .svf file created with iMPACT. I have read, there was a problem with it, but in 5.1 SP3 it should be fixed. I have that version. I'm using .xsvf file, conversion utility svf2xsvf.exe, attached with xapp058. In the .svf file, there is one line (in the erase procedure) STATE DRCAPTURE DRPAUSE; which the utility svf2xsvf don't understand. I don't know why, because it knows STATE commands with multiple parameters. It must understand it badly, because it says error, 'DRCAPTURE invalid stable state'. I rewrite it to STATE DRPAUSE; and see how the states changes. It's going in that way: PauseIR -> Exit2IR -> UpdateIR -> SelectDR -> CaptureDR -> Exit1DR -> PauseDR. Does anybody know what's going wrong? Can be somewhere found newer version of the utility svf2xsvf? (I have 5.00) I'm programming it using playxsvf, with rewritten ports.c Thanks for answersArticle: 55416
I mean that disk have to work in hard conditions (vibration, hits etc.) "Michael Condon" <michael.condon@nrl.navy.mil> сообщил/сообщила в новостях следующее: news:b98e94$662$1@ra.nrl.navy.mil... > did you mean external ?!? > "Mikhail" <kostkin@asicdesign.ru> wrote in message > news:b983v1$al2$1@news.wplus.spb.ru... > > Could anyone recommend me flash-disk with IDE/ATA for "extremal" > > application? > > > > I found BiTMICRO (www.bitmicro.com) but few of thier technical > > characteristic seems strange ... > > > > > > > >Article: 55417
Austin Lesea wrote: > Michael, > > Faults are things like oxide break down, or junction breakdown. > > They are most likely from weak or originally defective oxides or junctions > that eventually broke from eventual overstress (due to their original weak > nature). > > These kinds of defects can not be totally avoided. One can burn in devices, > one can overstress devices, but lately there is a lot of data that shows > that doing so actually increases field failure rates (if you stress too > much, if you stress not much at all, it does very little for the long term > failure rate). > I am wondering whether the soft errors (if it does occur) in configuration memeory cell will destroy the device and bring in some permanent faults. From above discussion, it seems even even contension won't break the device easily. For example, what if a bidirectional hex line is driven by two drivers because one tri-buffer was opened due to SEU effect. Can the virtex device still tolerate that, if so, for how long? Thanks! > > This whole subject has nothing to do with FPGAs, so you should research > semiconductor reliability. > > Soft fails are another issue, and the following link covers that: > > http://www.xilinx.com/support/techxclusives/1000-techX35.htm > > Austin > > Michael Garvie wrote: > > > Given your FIT rates for high temperature, high moisture, electrical > > overstress, or purely random; what is the fault mode induced? Are these > > localized and permanent? Or do they go away with scrubbing? Or are > > they at the FPGA subsystem level? > > Regards, > > Miguel > > > > Austin Lesea wrote: > > > > > I suggest that if you have suddenly experienced a failure, that is the > > > kind of failure known as "random" and fits well within our FIT rate > > > predictions. > > > > > > As everyone knows, failures do happen, and if the designers, industry > > > and foundries could prevent that from happening, we would all be > > > happier when we have to design fail-safe systems. > > > > > > So, until then, fail safe systems fail, by failing to fail safely. > > > > > > AustinArticle: 55418
Greg, You forgot to mention that you have the jitter transfer function in an app note (I'll let you reference it), and the PLL is well behaved with no attenuation out to ~ 6 MHz, and then a small peak (typical of a critical damped stable loop) of a little jitter gain at around 6 MHz, and then the 20dB/decade classic slope attenuating jitter after that. The same plot also shows the Virtex II DCM jitter transfer function, which is identical from DC to 6 MHz, with just slightly higher jitter due to the 60 ps tap changes, and then it remains flat beyond 6 MHz (no attenuation at all). In comparison, a ICS PLL (8745) has a cutoff pole at 300 KHz, and thus would attenuate far more jitter (what we recommend if one needs to "clean up" the jitter). PLLs in FPGAs can not afford to have the pole set that low, as the capacitor size becomes huge, and that makes it a cost prohibitive feature. Thus the PLLs have the smallest possible capacitor to meet the intended application, and remain stable over process, voltage, and temperature. As well, these plots do little to show how they behave in a real design with IOs switching, and logic in the core toggling. "We have not come to bury PLLs, but to praise them...." (apologies for the miss-qoute of Brutus to Ceasar....). (We use PLLs in the Multi-gigabit transceivers in Virtex II Pro to multiply the reference clock by a factor of 20 from 156.25 MHz to 3.125 GHz, so we know all about PLLs, too. Thanks to Altera for the jitter transfer curves. By the way, how about publishing the jitter tolerance curves, and residual jitter output curves, too? One of the classic set of three is insufficient to tell the whole story about a PLL. It may be good at attenuating, but will it remain locked in the presence of input jitter?) Austin PS: Phil, I have found the button, and I apologize for being "newgroup archive hostile." Greg Steinke wrote: > > Joona, > On Cyclone, the way to change the PLL configuration is to reconfigure > the entire part. So for your particular application, what you could do > is store 8 possible configurations, and choose which one configures > the part depending on the user input. Since the user is going to > select the multiplication factor, it is probably not changing very > often. A way to do this would be to store the configurations in a > parallel Flash memory and use a MAX device (CPLD) to select which > configuration is used. > > The Enhanced PLLs on the Stratix devices do support real-time > reconfiguration without the need to reconfigure the entire device. For > example, logic within the device can change the multiplication and > division factors to meet your needs. This process is documented in > AN282: > http://www.altera.com/literature/an/an282.pdf > > For your final question on the jitter: > The relationship of input jitter to output jitter on a PLL is somewhat > complicated. It is not the case that multiplying the frequency by 5 > (as in your example) will multiply the jitter by 5. In general, a PLL > will pass through low-frequency jitter, but reduce high-frequency > jitter. A high-level explanation is that the PLL actually regenerates > the clock and does not simply pass it through with some delay, so > depending on its characteristics it will not pass through all > high-frequency variation of the clock period. Therefore high-frequency > jitter is attenuated. On the other hand, a slow variation of the clock > period (low-frequency jitter) will be tracked by the PLL oscillator > and so will be passed through to the output. > > The documentation for the various devices shows what the output jitter > will be, and this is specified for any multiplication factor. In some > cases there is a different spec depending on what multiplication > factor is used. > > For more details on the Stratix PLL and how it implements frequency > division/multiplication please consult: > http://www.altera.com/literature/hb/stx/ch_1_vol_2.pdf > For more details on the Cyclone PLL please consult: > http://www.altera.com/literature/an/an251.pdf > > Sincerely, > Greg Steinke > gregs@altera.com > > jonesky1@hotmail.com (Joona R) wrote in message news:<2f3990c3.0304261139.3be78e8c@posting.google.com>... > > Hello! > > > > Can I change Cyclone PLL's divisor and multiply counter values on the > > fly? I will use Quartus, after license has arrived. > > I want that user can change clock frequency of device by pressing a > > button. Needed frequencys are between 30MHz and 100MHz. Frequencys may > > be for example 10MHz distances (30, 40, 50, 60, 70, 80, 90 and > > 100MHz). > > > > I was thinking, if input frequency will be 20MHz. Then it is divided > > by two and then multiplyed with user's wanted value (3 to 10). Is this > > reasonable way? How is input frequency's jitter effecting to output > > freq? If fIn is 20MHz with 50ppm, is fOut then 100MHz with 250ppm? > > (M=10, N=2) > > > > Is this possible or is there some better way to do this? Good ideas > > are welcome! =) > > > > Best Regards, > > JoonaArticle: 55419
Weifeng, We took a device, (actually a number of them) and placed them in contention purposely. Current densities of 10-15 million amperes per cm squared. Far over any electromigration limits. We then took readings every month. That started over four years ago. No problems whatsoever. When we say these parts are tough, we mean it. We have no idea what the customer will do, and sometimes the static stress of contention is less than the operating stress a typical customer may require! Some anit-fuse FPGA vendor(s) have a lot of foolish FUD (fear, uncertainty, doubt) out there which is totally wrong, false, and intentionally mis-leading. We have countered that with the "1000 years between single event upsets" tech exclusive on the public website. This tech exclusive by Peter and myself has been a best seller, as evidenced by doing a search in Google. It is #1 on the "hit" list for a few months now. Never been #1 on Google before....... (search for: 1000 years between single event upsets) Austin Weifeng Xu wrote: > > > > Austin Lesea wrote: > > > Michael, > > > > Faults are things like oxide break down, or junction breakdown. > > > > They are most likely from weak or originally defective oxides or > > junctions > > that eventually broke from eventual overstress (due to their > > original weak > > nature). > > > > These kinds of defects can not be totally avoided. One can burn in > > devices, > > one can overstress devices, but lately there is a lot of data that > > shows > > that doing so actually increases field failure rates (if you stress > > too > > much, if you stress not much at all, it does very little for the > > long term > > failure rate). > > > > I am wondering whether the soft errors (if it does occur) in > configuration memeory cell will > destroy the device and bring in some permanent faults. From above > discussion, it seems even > even contension won't break the device easily. > For example, what if a bidirectional hex line is driven by two > drivers because one tri-buffer > was opened due to SEU effect. Can the virtex device still tolerate > that, if so, for how long? > Thanks! > > > > > This whole subject has nothing to do with FPGAs, so you should > > research > > semiconductor reliability. > > > > Soft fails are another issue, and the following link covers that: > > > > http://www.xilinx.com/support/techxclusives/1000-techX35.htm > > > > Austin > > > > Michael Garvie wrote: > > > > > Given your FIT rates for high temperature, high moisture, > > electrical > > > overstress, or purely random; what is the fault mode induced? Are > > these > > > localized and permanent? Or do they go away with scrubbing? Or > > are > > > they at the FPGA subsystem level? > > > Regards, > > > Miguel > > > > > > Austin Lesea wrote: > > > > > > > I suggest that if you have suddenly experienced a failure, that > > is the > > > > kind of failure known as "random" and fits well within our FIT > > rate > > > > predictions. > > > > > > > > As everyone knows, failures do happen, and if the designers, > > industry > > > > and foundries could prevent that from happening, we would all be > > > > > > happier when we have to design fail-safe systems. > > > > > > > > So, until then, fail safe systems fail, by failing to fail > > safely. > > > > > > > > AustinArticle: 55420
It shouldn't take you more than a week or so worth of nights and weekends to
get a netlist and layout package together for a board house to produce it. You
might talk to a few board houses first to get pricing as well as options for
input format. Some only work with specific board layout packages, others are
far more flexible. Some will even do the netlist capture for an additional
fee.
Torquemada wrote:
> ? If you really believe that the hobbyist market is a huge untapped market,
> why
> ? don't you get a BGA or TQFP to dip adapter board made and assembled in
> some
> ? reasonable quantity and sell them? There are plenty of fab/assembly
> houses
> ? that are hungry for work right now, so I'm sure you could wrangle
> something. I
> ? would at least put bypass caps on the adapter module. You might also
> consider
> ? a socketed serial prom so as to not use up valuable pins for programming.
>
> If I didn't already have a decently paying job that takes up most of my day
> I'd do
> exactly this! :-) I'll have to see if I can get some prototypes working...
> --
> Torque
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 55421
Ken,
Do yourself a favor and buy, borrow or steal a copy of the ARRL Handbook for
Radio Amateurs. It has simple circuits in it to do exactly what you want at a
cost far lower than any commercially available solutions.
Ken wrote:
> (I posted a similar message before whose subject was "RF
> transmitters/receivers with Xilinx Xtreme DSP Kit" - I am reposting with
> better details of what I need - this is not strictly do do with FPGAs but I
> hope some of you guys may have experience with this stuff - I may well do
> the I/Q modulation/demodulation on FPGA anyway so it is somewhat relevant...
> ;-) )
>
> Hello,
>
> I am looking for several pieces of off the shelf equipment to perform RF
> transmission and reception across a table-top/room. The gear can therefore
> be very low power. The RF carrier frequency is flexible and a few hundred
> MHz would do although GHz would be nice - I guess if I track down a range of
> suitable equipment I will be able to trade Hz against cash!
>
> I have seen quite a lot of expensive and complicated pieces of equipment
> that will do the simple tasks I require but I cannot justify the cost when
> all I really need is some sin/cos mixing and modulation. I have searched
> some online catalogues and spoken to reps from various companies with no
> success so far - surely these simple boxes must exist to buy!
>
> Anyway, here is the list:
>
> TX Box 1:
> Inputs: 1 BNC input carrying an IF modulated signal
> This box just needs to AM modulate the IF input to an RF frequency and
> possibly perform some sort of filtering to reject images?
> Outputs: 1 - something suitable for feeding to an antenna...? not quite
> sure
>
> RX Box 2:
> Inputs: suitable connector coming from an antenna I guess
> This box needs to demodulate the RF signal from box 1 and output it at some
> IF or baseband.
> This box would need to do suitable filtering to demodulate with no problems.
> Outputs: 1 BNC output.
>
> TX Box 3:
> Inputs: 2 BNC inputs carrying I and Q signals at baseband/IF
> This box needs to mix the I/Q signals with cos/sin waves and add them
> together to produce an RF signal
> Outputs: 1 - something suitable for feeding to an antenna
>
> RX Box 4:
> Inputs: suitable connector coming from an antenna
> This box needs to mix the input with a cosine to get the I output and mix
> the input with a sine to get the Q output.
> This box would also need to do suitable filtering to demodulate with no
> problems.
> Outputs: 2 BNC outputs carrying I and Q.
>
> Some of the boxes may not need filters as the ADCs/DACs I will be using can
> possibly do this job depending on the specs.
>
> Any pointers towards suitable gear/places to buy it would be very much
> appreciated!
>
> Thanks in advance for your time,
>
> Ken
>
> --
> To reply by email, please remove the _MENOWANTSPAM from my email address.
>
> --
> To reply by email, please remove the _MENOWANTSPAM from my email address.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 55422OK Ray - you've convinced me - if it has circuit diagrams then I can get our workshop to build exactly what I want. Cheers, Ken "Ray Andraka" <ray@andraka.com> wrote in message news:3EB921E5.4783FC52@andraka.com... > Ken, > > Do yourself a favor and buy, borrow or steal a copy of the ARRL Handbook for > Radio Amateurs. It has simple circuits in it to do exactly what you want at a > cost far lower than any commercially available solutions. > > Ken wrote: > > > (I posted a similar message before whose subject was "RF > > transmitters/receivers with Xilinx Xtreme DSP Kit" - I am reposting with > > better details of what I need - this is not strictly do do with FPGAs but I > > hope some of you guys may have experience with this stuff - I may well do > > the I/Q modulation/demodulation on FPGA anyway so it is somewhat relevant... > > ;-) ) > > > > Hello, > > > > I am looking for several pieces of off the shelf equipment to perform RF > > transmission and reception across a table-top/room. The gear can therefore > > be very low power. The RF carrier frequency is flexible and a few hundred > > MHz would do although GHz would be nice - I guess if I track down a range of > > suitable equipment I will be able to trade Hz against cash! > > > > I have seen quite a lot of expensive and complicated pieces of equipment > > that will do the simple tasks I require but I cannot justify the cost when > > all I really need is some sin/cos mixing and modulation. I have searched > > some online catalogues and spoken to reps from various companies with no > > success so far - surely these simple boxes must exist to buy! > > > > Anyway, here is the list: > > > > TX Box 1: > > Inputs: 1 BNC input carrying an IF modulated signal > > This box just needs to AM modulate the IF input to an RF frequency and > > possibly perform some sort of filtering to reject images? > > Outputs: 1 - something suitable for feeding to an antenna...? not quite > > sure > > > > RX Box 2: > > Inputs: suitable connector coming from an antenna I guess > > This box needs to demodulate the RF signal from box 1 and output it at some > > IF or baseband. > > This box would need to do suitable filtering to demodulate with no problems. > > Outputs: 1 BNC output. > > > > TX Box 3: > > Inputs: 2 BNC inputs carrying I and Q signals at baseband/IF > > This box needs to mix the I/Q signals with cos/sin waves and add them > > together to produce an RF signal > > Outputs: 1 - something suitable for feeding to an antenna > > > > RX Box 4: > > Inputs: suitable connector coming from an antenna > > This box needs to mix the input with a cosine to get the I output and mix > > the input with a sine to get the Q output. > > This box would also need to do suitable filtering to demodulate with no > > problems. > > Outputs: 2 BNC outputs carrying I and Q. > > > > Some of the boxes may not need filters as the ADCs/DACs I will be using can > > possibly do this job depending on the specs. > > > > Any pointers towards suitable gear/places to buy it would be very much > > appreciated! > > > > Thanks in advance for your time, > > > > Ken > > > > -- > > To reply by email, please remove the _MENOWANTSPAM from my email address. > > > > -- > > To reply by email, please remove the _MENOWANTSPAM from my email address. > > -- > --Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com > > "They that give up essential liberty to obtain a little > temporary safety deserve neither liberty nor safety." > -Benjamin Franklin, 1759 > >Article: 55423
"Ken" <aeu96186_MENOWANTSPAM@yahoo.co.uk> wrote in message news:<b9ams2$bjb$1@dennis.cc.strath.ac.uk>... > > Any pointers towards suitable gear/places to buy it would be very much > appreciated! > Here's a web page with pointers to newsgroups that can help: http://www.ve2dm.net/ve/hamnews.shtmlArticle: 55424
In article <3EB8D4F1.427@designtools.co.nz>, Jim Granville wrote:
>>
>> Yes, the context is GPS and a very good crystal.
>> I was sloppy with the number of digits I typed in, but the idea
>> is that I wanted lots of low order bits. Should be easy to do
>> in an FPGA.
>> The good/fancy crystals I've seen come with an analog input
>> to tweak the frequency. With a good crystal, you end up needing
>> a 16 bit D/A and the crystal aging has to be measured and factored
>> in when coasting if the GPS runs out of satellites.
>>
>> So then I got to thinking about doing the corrections
>> in the FPGA rather than tweaking the analog knob.
>
> Since this is a corrected timebase, that will mostly be
> extrnally locked, look at the digital calib schemes used on
> some watch chips. They use a fixup scheme, of "so many LSB's" to
> nudge the timebase. - No caps, or analog, needed.
I agree. In general, if you can replace hardware with firmware you
come out ahead. In this case, you want to build the inverse of a
DDS. Calibrate the number of femptoseconds per tick of the crystal,
and just do a very wide accumulate on every tick. The high order
bits will give you the time (you probably don't want to expose the
femptoseconds part to the software).
> eg I asssume you will want seconds to be as precise
> over 12 months as possible, but are perhaps not so worried
> if the counts per millisecond deviates by some few ppm.
Direct phase accumulation is never off by more than one lsb.
> Measuring two Freqs sounds like a FPGA task :)
_Everything_ sounds like an FPGA task these days. :-)
- Larry
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