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Austin Lesea wrote > Your choice. > > The HSWAP_EN pin on Virtex II and II Pro enables the weak pullups while the > part is configuring. After that, they are enabled if you have set the > attribute of the IO pin to do so. > > Tim wrote: > > > Peter Alfke wrote > > > > > With Xilinx, there are optional internal pull-up and pull-down resistors > > > ( 50...100kilohm), even an internal weak keeper that maintains the > > > previously-drive logic level. > > > > Is the weak keeper engaged under all circumstances? > > It certainly seems that way if I look at the pins > > with a very high impedence probe. I asked about the weak keeper, not the pullups.Article: 53951
iidigoras@ikerlan.es (ii) writes: > Hello, > > I have to design a control board with a TI DSP (C67xx). For providing > some peripherals (PWM generation, encoder read) I will use a Xilinx > FPGA. > > My concern is how to connect both of them. The DSP has the EMI block, > where the FPGA could be connected, as a memory mapped device. > That's right. Which C67xx are you using? All the following applies to my experience of the C6711, dunno if it applies to the 6701 or any others... > What are the best design practices for synchrous design? Do I use the > same clock for both devices? or different ones? how can I synch them? > Depends on how complex your interface needs to be. You can either use the EMIF in asynchronous mode (designed for async memories, but all the signals are synchronous to the ECLKOUT) - in which case the interfacing is fairly straightforward, as you can use the ARDY to hold off the transaction if you need to. You don't need to worry about synchronising the 'asynchronous' control signals if you use the ECLKOUT to clock the FPGA. However, performance is limited as you need at least one setup cycle, one strobe cycle and one hold cycle. For more performace, you can try and emulate a sync burst SRAM (or even a sync DRAM if the access patterns the DSP uses fit with your application) > Use the FPGA's built-in DPRAM or build registers? > Depends on your peripherals - if all you want to do is queue up some commands for them to perform, you could stick them in the DPRAM. I think you'll probably end up needing some status/control type registers as well though. HTH - feel free to ask more detailed questions! Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt, Solihull, UK http://www.trw.com/conektArticle: 53952
Ok, thanks a lot to u! Now i got it. In Verilog it's working similar to this VHDL example. Just including a Verilog source file (instead of the library) according to the architecture u use. So, in my case a file called "virtexe.v", whis is provided in one of the Synplicity folders with Synplify. Anyway what it does is basically adding the XILINX components as "black-boxes" as far as i understand. So, they are not synthesised by Synplify. XILINX tool will infer these blocks later on while place-and-route. Nearly everything is working until now. Simulation after place-and-route.... My design seems to work with the 2 clock signals generated by this DLL also on the FPGA as far as i've tested it. However, this "LOCKED" signal from the DLL which indicates when the clock outputs are stable is not always going high in the FPGA. In post-place-and-route simulation ok. But in the FPGA, it seems to work with frequencies above then 20 MHz. With lower frequencies, this "LOCKED" signal stays low, which i've tested with a lot of oscilators so far. Anyway, the clock-outputs seem (at least look) ok with every frequency. I don't understand this. Maybe someone has got an idea??? ThorstenArticle: 53953
Hello all, I'm having a problem exporting the quartus .vho file into leonardo, giving the following error .. "C:simulation/modelsim/Clock_Divider.vho",line 125: Error, formal port modesel(11) does not exist on cell apex20ke_io from library apex20e. Is this the correct file to use for the structure of the design ? DaveArticle: 53954
Look at the data sheet. Thd clock DLLs have a input minimum frequency of
about 25 MHz.
tote wrote:
>
> However, this "LOCKED" signal from the DLL which indicates when the
> clock outputs are stable is not always going high in the FPGA. In
> post-place-and-route simulation ok. But in the FPGA, it seems to work
> with frequencies above then 20 MHz. With lower frequencies, this
> "LOCKED" signal stays low, which i've tested with a lot of oscilators
> so far. Anyway, the clock-outputs seem (at least look) ok with every
> frequency.
>
> I don't understand this. Maybe someone has got an idea???
>
> Thorsten
--
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President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
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temporary safety deserve neither liberty nor safety."
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Article: 53955Hi I would like to know if/how it is possible to detect pin failure through boundary scan - i.e. I would like to know if my CPLD (or FPGA) has all pins fully working, because I have difficulties measuring all the signals and also difficulties with devices connected to CPLD. So by now you have probably figured it out - I can't find where the problem is. Much thanks. Joze DedicArticle: 53956
Kevin, Thanks that seems easy enough Dave C. "Kevin Brace" <kev0inbrac1eusen2et@ho3tmail.c4om> wrote in message news:b60j32$ipj$2@newsreader.mailgate.org... > Oops, I forgot to mention that you need to tell NGDBUILD where the > netlist generated from the VHDL part of the design is located. > > > Kevin Brace (If someone wants to respond to what I wrote, I prefer if > you will do so within the newsgroup.)Article: 53957
Joze, The XJTAG tool (www.xjtag.com) can be used in the way you suggest, more specifically it will implement the connection test to check that all the pins are down on a device, but it also does a lot more... XJEase is a simple BASIC like programming language that can be used to write tests for non-JTAG devices like RAMs or network controllers, using this tool you can write code to do loopback tests on ethernet controllers, or even read the time from a RTC, wait a second and read it again! Also the XJLink JTAG hardware can be bought with the XJAPI interface so you can write your own JTAG code to access embedded processors etc. If you need any more information you can contact us on support@xjtag.com Cheers Gordon Hollingworth PhD Dr Gordon Hollingworth "Joze Dedic" <joze.dedic@fe.uni-lj.si> wrote in message news:b61gsv$2c1$1@planja.arnes.si... > Hi > > I would like to know if/how it is possible to detect pin failure through > boundary scan - i.e. I would like to know if my CPLD (or FPGA) has all pins > fully working, because I have difficulties measuring all the signals and > also difficulties with devices connected to CPLD. So by now you have > probably figured it out - I can't find where the problem is. > > Much thanks. > > Joze Dedic > >Article: 53958
Hello, We are finding one of the biggest hurdles to those new to the Confluence logic design language is the use of recursion and high order components for building flexible and scalable logic structures. So, we've added a section to the docs illustrating a few practical design examples. One example builds a generic FIR filter with a variable number of taps and variable precision in less than 20 lines of code. The current docs are at: http://www.launchbird.com/documentation.html If anyone has suggestions, or would like to see a particular example in the tutorial, please drop me a line. Thanks, Tom -- Tom Hawkins tom1@launchbird.com Launchbird Design Systems, Inc. http://www.launchbird.com/Article: 53959
some newbie questions if someone could help, I have been given Quartus to learn and a couple of altera boards ( and directions from the boss to use VHDL instead of Verilog when required ) ... TIA, CB 1) For my first design to get my feet wet, I am going to use a EPM7128 to replace a couple of 22V10's in an older design, I haven't been able to find any simple registered sum of products type designs on the net as examples ... so I guess I need to enter the pal equations in VHDL , anyone have any simple example of what that looks like, the boss also tossed a VHDL book my way but I'm having trouble finding how to do something simple like enter a pal term , if there is an appl note on the net or something to help that would be great 2) Quartus II provides VHDL synthesis OR you can use LeonardoSpectrum ... is Spectrum different ? or superior ? ... so does everyone use Spectrum or do different projects fit one or the other better.Article: 53960
"joan rodo" <joanrodo@betaprint.com> wrote in message news:<b5pum8$i7q$1@nsnmrro2-gest.nuria.telefonica-data.net>... > Hi Guys > > I'm developing a new board with a spartan II xc2s50 and I want to > integrated the programming of the FPGA in my C software there any routine > that translates from mcs file to a C file. > > Or there are any easy solution for to that. > > Thanks for all. Have you ever considered a dedicated processor for an FPGA/CPLD programming? SystemBIST embedded test and configuration processor seems an interesting product. You may check this web site: www.intellitech.com. AliArticle: 53961
OOPS, Weak keeper is never enabled unless you set the attributte for it. Austin (got pullups/pulldowns on the brain) Tim wrote: > Austin Lesea wrote > > Your choice. > > > > The HSWAP_EN pin on Virtex II and II Pro enables the weak pullups while the > > part is configuring. After that, they are enabled if you have set the > > attribute of the IO pin to do so. > > > > Tim wrote: > > > > > Peter Alfke wrote > > > > > > > With Xilinx, there are optional internal pull-up and pull-down resistors > > > > ( 50...100kilohm), even an internal weak keeper that maintains the > > > > previously-drive logic level. > > > > > > Is the weak keeper engaged under all circumstances? > > > It certainly seems that way if I look at the pins > > > with a very high impedence probe. > > I asked about the weak keeper, not the pullups.Article: 53962
Hi, It changes from language to language, and from tool to tool. Yes, there is a way to fix the pins in the HDL. There is also a way to fix the pins in the FPGA tool. You need to tell us which tools you are using! SH mhelshou@yahoo.com (Mohammed Hamed) wrote in message news:<e0d0cbd0.0303271013.46580125@posting.google.com>... > Hi All, > > Sorry I'm new to this. Can I fix a certain input to a module or a > certain FPGA pin using constraints file or in HDL code? I want to do > this for testing, so that for example when implementing DES encryption > I don't have to connect real FPGA pins to logic 1 or 0. Instead I want > to fix those pins from the Verilog/VHDL code and reprogram it. > > I hope this is not a homework thing, if so just point me to where to > look. > > Thank you,Article: 53963
"CB" <charleybrant@hotmail.com> wrote > 1) For my first design to get my feet wet, I am going to use a > EPM7128 to replace a couple of 22V10's in an older design, I haven't > been able to find any simple registered sum of products type designs > on the net as examples ... so I guess I need to enter the pal > equations in VHDL , anyone have any simple example of what that looks > like, the boss also tossed a VHDL book my way but I'm having trouble > finding how to do something simple like enter a pal term , if there is > an appl note on the net or something to help that would be great You wouldn't normally start a VHDL design by doing SOP description - it's the synthesis tool's problem to do that, not yours. But you *can* do it, if you really must. When you say "a PAL term", what are you talking about? A line of fuses? One line of products from a PALASM description? ??? Give us an example of what you want to rewrite and we can suggest a VHDL "translation". > 2) Quartus II provides VHDL synthesis OR you can use LeonardoSpectrum > ... is Spectrum different ? or superior ? ... so does everyone use > Spectrum or do different projects fit one or the other better. For simple jobs it shouldn't make much difference. LeoSpec in its full-blown version can target many more devices than just Altera, but the version you get with Quartus is limited to Altera-only. It's just possible that you may find a few little-used VHDL features that Leo can understand but Quartus doesn't - but all the standard stuff should be fine. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK Tel: +44 (0)1425 471223 mail: jonathan.bromley@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 53964
Thank you for your answer. I have spend several hours searching for appropriate solutions in a meantime. Now, when I know that it is possible, I would like to address the people who know how to do that with non commercial tools, if there are any. What I would like is to simply read from and write to pin. Is that too much for free? Or there might be some commercial solution with university price-discount. I am a PhD junior research student an we will use it for educational reasons. Regards, Joze Dedic "Gordon Hollingworth" <gordon.hollingworth@NOSPAMoptionexist.co.uk> wrote in message news:b61ka7$fok$1$8300dec7@news.demon.co.uk... > Joze, > > The XJTAG tool (www.xjtag.com) can be used in the way you suggest, more > specifically it will implement the connection test to check that all the > pins are down on a device, but it also does a lot more... > > XJEase is a simple BASIC like programming language that can be used to write > tests for non-JTAG devices like RAMs or network controllers, using this tool > you can write code to do loopback tests on ethernet controllers, or even > read the time from a RTC, wait a second and read it again! > > Also the XJLink JTAG hardware can be bought with the XJAPI interface so you > can write your own JTAG code to access embedded processors etc. > > If you need any more information you can contact us on support@xjtag.com > > Cheers > > Gordon Hollingworth PhD > > > Dr Gordon Hollingworth > > > "Joze Dedic" <joze.dedic@fe.uni-lj.si> wrote in message > news:b61gsv$2c1$1@planja.arnes.si... > > Hi > > > > I would like to know if/how it is possible to detect pin failure through > > boundary scan - i.e. I would like to know if my CPLD (or FPGA) has all > pins > > fully working, because I have difficulties measuring all the signals and > > also difficulties with devices connected to CPLD. So by now you have > > probably figured it out - I can't find where the problem is. > > > > Much thanks. > > > > Joze Dedic > > > > > >Article: 53965
Dave Wilson wrote: > I'm having a problem exporting the quartus .vho file into leonardo, > giving the following error .. > "C:simulation/modelsim/Clock_Divider.vho",line 125: Error, formal port > modesel(11) does not exist on cell apex20ke_io from library apex20e. > Is this the correct file to use for the structure of the design ? The normal flow after simulation is: foo.vhd => [leo] => foo.edf => [quartus] => foo.rbf => [device] -- Mike TreselerArticle: 53966
I realize this is asking a big favour : can you please e-mail me the exe or source files to me? As I said, I am having difficulty downloading the core and if you managed to get it without difficulty hopefully I can get it from you. Just as a technical aside, what was your environment when you downloaded? (i.e. computer platform/hardware, OS, network protocols and networks connected to, browser type and version, browser environment (i.e. security settings, cookies enabled/disabled, etc). If somebody was able to download successfully I must assume that it isn't a problem with the source site, and therefore must be some particular aspect of how my environment is set up. Any relevant details you could provide would be *greatly* appreciated. Thanks. -- Alex Rast ad.rast.7@nwnotlink.NOSPAM.com (remove d., .7, not, and .NOSPAM to reply) at Thu, 27 Mar 2003 08:54:05 GMT in <UZyga.1052$ck7.28244@newsfep1-win.server.ntli.net>, hansydelm@no-spam-ntlworld.com (Hans) wrote : >From: "Hans" <hansydelm@no-spam-ntlworld.com> >Newsgroups: comp.arch.fpga,comp.arch.embedded >Subject: Re: Anyone have difficulty downloading this core? > >Works fine for me, nice core!! > >Hans. >www.ht-lab.com > >"Alex Rast" <ad.rast.7@nwnotlink.NOSPAM.com> wrote in message >news:93499217Eadrastnwnotlinkcom@216.168.3.44... >> http://www02.so-net.ne.jp/~morioka/cqpic.htm >> >> Supposedly a PIC16F84 implementation in VHDL. Version 1.00b appears to >> be downloadable on the site. But when I click the link, I get the >> following: >> >> "Forbidden >> You don't have permission to access /fb3/morioka/pic100a/cqpic100b.exe >> on this server." >> >> i.e. the standard no-access message. Are others running into this? If >> so, is there some other location from which I can download? Or is it >> somehow something in my environment that I need to change in order to >> download successfully? >> -- >> Alex Rast >> ad.rast.7@nwnotlink.NOSPAM.com >> (remove d., .7, not, and .NOSPAM to reply)Article: 53967
"Alex Rast" wrote > http://www02.so-net.ne.jp/~morioka/cqpic.htm > > Supposedly a PIC16F84 implementation in VHDL. Version 1.00b appears to be > downloadable on the site. But when I click the link, I get the following: > > "Forbidden > You don't have permission to access /fb3/morioka/pic100a/cqpic100b.exe on > this server." Left-click fails. Right-click and "save as..." works. Regards, Arie de MuynckArticle: 53968
"Sriram" <machosri@yahoo.com> wrote in message news:56210527.0303271552.2a7e1fbe@posting.google.com... > Hi , > Well the basic question is that I would like to interface a XILINX > Virtex fpga on a fpga development board to a SUN machine .I want the > FPGA to act as a hardware accelerator,wherein I can do computationally > intensive parts of an algorithm on the fpga and the rest on the SUN > workstation.So thus there will have to be an interface through > interrupts when i come across those functions to be done using > hardware.The result of these hardware operations has to be stored in a > memory which should be accessible by the SUN workstation,through a > common bus. VCC ( http://www.vcc.com ) used to do things like this. The SBUS one might have been in the XC4000 days, and newer ones might be PCI. -- glenArticle: 53969
charleybrant@hotmail.com (CB) wrote in message news:<3e846a7f.3575606@news.compuserve.com>... > some newbie questions if someone could help, I have been given Quartus > to learn and a couple of altera boards ( and directions from the boss > to use VHDL instead of Verilog when required ) ... TIA, CB > ...... Your boss probably gave you a book that may not have been the right "get their in a hurry". I and many others will strongly recoment the "HDL Chip Design" by Douglas Smith. It says nothing of FPGAs but don't let that fool you, it is just as valuable for FPGA as ASIC, probably more so given background of newer designers. It gives literally hundreds of examples you will understand right away, most of them include problem description, both the Verilog & the VHDL code & the corresponding schematic in gates & flops, sometimes state machines & tables if needed. Each example covers 1 or 2 pages, jump in where ever you see something interesting. All the drawings look like they were done by hand, not auto genenerated. I don't think you will be using just pal equations to get ahead, the book will probably have something close enough for you to draw analogy from. JJArticle: 53970
at Fri, 28 Mar 2003 18:53:30 GMT in <3e849a3e$0$49106$e4fe514c@news.xs4all.nl>, no-please@no-spam (Arie de Muynck) wrote : > >"Alex Rast" wrote >> http://www02.so-net.ne.jp/~morioka/cqpic.htm >> >> Supposedly a PIC16F84 implementation in VHDL. Version 1.00b appears to >> be downloadable on the site. But when I click the link, I get the >> following: >> >> "Forbidden >> You don't have permission to access /fb3/morioka/pic100a/cqpic100b.exe >> on this server." > > >Left-click fails. >Right-click and "save as..." works. > >Regards, >Arie de Muynck > > > > Did you check the actual file that was downloaded when you tried this technique? You might be in for a surprise. I already tested that possibility before posting and discovered that it seems to work, but in fact all it did is download the HTML page with the "Forbidden" message. FWIW, my environment is as follows: I'm using a PC-platform (AMD Athlon) computer running Windows 2000. I have the NetWare client loaded. Communication to NetWare servers is via IPX only, so I use TCP/IP exclusively for the Internet connection. This is through a DSL modem, NAT enabled so that the only visible external IP address is that of the modem. Meanwhile, browser-wise I've tried using both Opera 7.02 and Netscape 4.08. I've tried both enabling and disabling cookies, security blocking, etc. -- Alex Rast ad.rast.7@nwnotlink.NOSPAM.com (remove d., .7, not, and .NOSPAM to reply)Article: 53971
I've seen this question answered in the FAQ, but only for older devices. I have a design which is mostly composed of adder-subtractors (i.e. you add or subtract depending on a third data input) of between 16 and 32 bits wide. Some of these need to run as fast as 120 MHz. Previous posts seem to indicate that Xilinx is much better for things of this type, but the posts were pre-Cyclone. Does this still apply? We were planning on using the Spartan 2E with 300K-gates, but we are constrained to use a non-BGA part, and thus have become pin-limited. The Cyclone parts have more I/Os in the PQFP packages, so the EP1C6 and EP1C12 looked interesting. If Cyclone is usable for this sort of application, which part is closest in functionality to the SpartanII 300? Thanks MattArticle: 53972
The vho file is intended as input to VHDL simulators like Modelsim. It is not intended as input for synthesis tools. - Subroto Datta Altera Corp. da_wils@hotmail.com (Dave Wilson) wrote in message news:<6895fdb2.0303280407.252054f2@posting.google.com>... > Hello all, > > I'm having a problem exporting the quartus .vho file into leonardo, > giving the following error .. > > "C:simulation/modelsim/Clock_Divider.vho",line 125: Error, formal port > modesel(11) does not exist on cell apex20ke_io from library apex20e. > > Is this the correct file to use for the structure of the design ? > > DaveArticle: 53973
machosri@yahoo.com (Sriram) wrote in message news:<56210527.0303271552.2a7e1fbe@posting.google.com>... > Hi , > Well the basic question is that I would like to interface a XILINX > Virtex fpga on a fpga development board to a SUN machine .I want the > FPGA to act as a hardware accelerator,wherein I can do computationally > intensive parts of an algorithm on the fpga and the rest on the SUN > workstation.So thus there will have to be an interface through > interrupts when i come across those functions to be done using > hardware.The result of these hardware operations has to be stored in a > memory which should be accessible by the SUN workstation,through a > common bus. > > I was thinking that I could perhaps use the PCI/SBus interface for > this purpose and wanted to find out about any off the shelf products > and help from > somebody who perhaps has done somethng similar. > > Thanks, > Sriram DINI PCI 64 bit boards definitely get used in Sun servers as well as Dell, don't know if you have to roll your own support though. Any 64/66 card should be OK see above. As everyone else says, "Its the IO stupid", do as many ops per possible on each data point transferred across a relatively slow bus, and it might just be faster than a 3Ghz P4, maybe not. You want to make sure the fattest part of the data stream remains inside the FPGA and lesser trafic back to CPU, buts thats not always possible. JJArticle: 53974
Kevin Brace <kev0inbrac1eusen2et@ho3tmail.c4om> wrote in message news:<b60g8m$g92$1@newsreader.mailgate.org>...
> Jan,
>
> I am not exactly sure what is causing this problem, but there are there
> things I don't like with your RTL code.
>
<snip>
Same here, but would like to go one step further -
1. It would be nice to seperate the combinational and sequential parts
into seperate always blocks -
________________________________________________________________________________
always @ (posedge clock or negedge reset_n)
begin
if (~reset_n)
state <= #1 lcd_function;
else
state <= #1 next_state ; //will need to define the next state reg
end
always @(// fill in all signals to which this block is sensitive)
begin
case(state)
lcd_idle: .......
other states : ......
default : ......
endcase
end
________________________________________________________________________________
2. Remember to assign all outputs in all branches of the case
statement, else you might get unwanted latches inferred.
Hope this helps,
Vikram.
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