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John Larkin wrote: > > Hi, > > It looks like I'm going to have to use an FPGA in a BGA package... > this circuit idea needs about 320 I/O pins, and no other package can > do that. 12 10-bit flash ADCs, VME32 interface, 68332 uP interface, > and tons of fast static RAM. Vibration measurement in jet engine > turbine blades. Ouch. > > We use PADS for PCB layout. So, does anybody know where we can get a > PADS library part for Xilinx Xc2S400E-6FG676 or similar, or just the > PCB decal for the FG676 package? This monster has 676 solder balls in > a 26x26 array, on 1 mm centers. Should be fun to solder and > troubleshoot! > > Respondants will get gratitude, beer, or money, ideally in that order > of priority. PCB decal should be a snip - just use the PADS PowerPCB FPGA decal Wizard, and fill out 26:X 26:Y and 1mm pitch - faster than this email, or about as long as it takes to fetch and open a can of cold beer :) Schematic decal is not so fast, and a common approach is to split into multiple symbols, in a design-specific manner. A bit more work, but makes the schematics more readable. -jgArticle: 56576
>How much delay skew do you need ? - it might be cleaner to >apply the same idea to an external tiny-logic gate, where the >Vcc range can be wider, and there is no Vcc/Gnd competing noise They make chips designed to add an adjustable delay. The target market is testing gear. On-Semi MC100E195 and friends. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 56577
"Josh Model" <model@ll.mit.edu> wrote in message news:<hr4Fa.51$Du1.40@llnews.ll.mit.edu>... > Hi all, > > Sorry to echo the common call on this group, but I've added a little twist. > I was looking for FPGA prototype boards that fit the PC/104 form factor and > standard. I've checked out the optimagic site, but most of the companies > listed there either don't the newer fpga's. Closest I came was Nova > Engineering's Altera boards, but Xilinx is much more in my comfort zone. > > Any suggestions? Thanks. > > --Josh Model > MIT/LL A little magic with google on <fpga pc104> should get you started! APS has been around awhile too.Article: 56578
Anyone pop one of them open? I wonder if you could just find the pinouts and reprogram the Xilinx inside. Steve "Antti Lukats" <antti@case2000.com> wrote in message news:80a3aea5.0306091301.161566e0@posting.google.com... > Larry Doolittle <ldoolitt@recycle.lbl.gov> wrote in message news:<slrnbe9bc7.ni6.ldoolitt@recycle.lbl.gov>... > > A quick trip through google and the Xilinx web pages did not > > disclose the interface description between the Parallel Cable IV > > and the PC Parallel port. With the III version, they gave schematics, > > > > Can anyone from Xilinx forward me that the interface description? > > Or has someone else already reverse engineered it? > > > > - Larry > Hi Larry, > > I think there will be silence from Xilinx, no matter how you ask. > > the IV interface specs are not public ASFAIK, but there may be a better way - > ChipScope Pro what is a java application uses a windows native DLL that talks > to all xilinx cables, so its much more elegant to extract the entry point > information from this dll and call them :) its some guess work, and you > may have to write a 'bypass dll' for trace logging, but then you are all > the time 100% compatible with all the same hardware as ChipScope :) > this may or may not work, but it could be one option at least. > hmmm this may require chipscope license, even if the dll's work after > trial period expires. > > I'd prefer of course if xilinx would disclose the cable IV specs, then I > could write software/drivers that dont fail as badly as xilinx provided ones. > > antti lukatsArticle: 56579
Hi all, I am trying to find a place where i can buy virtex ii online (xc2v500 or xc2v1000), but i am having a hard time. Can anyone help me?, Does anyone know where i can buy? tanks.Article: 56580
"Martin Euredjian" <0_0_0_0_@pacbell.net> wrote in message news:<8v5Fa.509$9c1.55732444@newssvr13.news.prodigy.com>... > Xilinx, Virtex II > > Are there any architecture-related performance (or other) advantages in > implementing shift registers with the output on the LSB vs. MSB? In other > words: > > output <= sr[3]; > sr[3] <= sr[2]; > sr[2] <= sr[1]; > sr[1] <= sr[0]; > sr[0] <= input; > > vs, > > output <= sr[0]; > sr[0] <= sr[1]; > sr[1] <= sr[2]; > sr[2] <= sr[3]; > sr[3] <= input; Howdy Martin, Absolutely... if you feed into the lsb and do not reset those nets, you can obtain resource savings (flops and routing) by letting the tools infer an SRL: http://support.xilinx.com/xlnx/xil_ans_display.jsp?getPagePath=9785 If you have a wide bus, or a deep pipeline wait, the savings can be considerable. There is a slight timing penality associated with this, but you shouldn't notice it unless you're running well over 200 MHz. Have fun, MarcArticle: 56581
ftp://ftp.xilinx.com But I can't login in. what is the user and password? -- Best RegardsArticle: 56582
Maybe you can consider www.ebay.com put "xilinx" keyword in the search column. Basuki Keren -----Original Message----- From: Henrique [mailto:henrique@bmrio.com.br]=20 Posted At: Tuesday, June 10, 2003 9:46 AM Posted To: fpga Conversation: Where can i buy virtex II ? Subject: Where can i buy virtex II ? Hi all, I am trying to find a place where i can buy virtex ii online (xc2v500 or xc2v1000), but i am having a hard time. Can anyone help me?, Does anyone know where i can buy? tanks.Article: 56583
>Absolutely... if you feed into the lsb and do not reset those nets, >you can obtain resource savings (flops and routing) by letting the >tools infer an SRL: Are the tools not smart enough to recognize the other pattern? (left shift vs right shift, if you want to think that way) The SRL only goes in one direction, but the software could/should be smart enough to assign FFs in either order. (or for that matter, to find a chain of arbitrarily named signals that don't go anyplace other than the input of the next FF.) -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 56584
> I would use the frequency of a ring oscillator, since a frequency can be > measured with very high accuracy. Well, I wanted to create a DLL-type circuit where I measure and control the phase-shift of the delay line. That should be accurate enough too. > But: > You are forced to make a guess at a certain mixture of transistor and > routing delays > Plus: you will inevitably run out of adjustment range. > If we make the very simplified assumption that delays change at a rate > of 0.3% per degree C, and that delays are inversely proportional to Vcc, > then you see that 5% allowable Vcc adjustment does not get you very far. Thanks for the information. From this it seems to me that I can cover ~30C temperature range without getting out of spec. I guess getting lower in VCCINT than spec at least won't demage the device, so if I allow it to go down to ~1.6V I can even cover a 45C range. That I is enough for me at least for start. Andras TantosArticle: 56585
>>How much delay skew do you need ? - it might be cleaner to >>apply the same idea to an external tiny-logic gate, where the >>Vcc range can be wider, and there is no Vcc/Gnd competing noise The problem there is that the interface levels are tied to the VCC while the Xilinx FPGA has different VCCIO and VCCINT voltages. The delay I need is in the 30-40ns range total but I would like to have taps at each 2-3ns point. > > They make chips designed to add an adjustable delay. The target > market is testing gear. On-Semi MC100E195 and friends. > I don't really want to go off-chip with this. As soon as I have to through the IO ring I loose a bunch of time, consume a bunch of power, use up a bunch of I/O etc. Also, these are ECL devices and that standard is not directly supported by the Xilinx device. You need interface chips which add additional delay and PCB space and power consumption and price, the whole design starts to explode... Thanks for the ideas, Andras TantosArticle: 56586
"Cooley" <305liuzg@163.net> wrote in message news:bc3hjo$2knd$1@mail.cn99.com... > ftp://ftp.xilinx.com > But I can't login in. > what is the user and password? I just tried it and got straight in, with IE. If you need to input user/password they are the usual for anonymous FTP (IIRC): email address and 'anonymous'. Leon -- Leon Heller, G1HSM leon_heller@hotmail.com http://www.geocities.com/leon_hellerArticle: 56587
Hi Khan, Are you using Xilinx ISE? If so, find the command in the implimentation menu to 'edit the constraints file'. Under that, you'll find a helpful GUI for the Xilinx-specific way of fixing the pins. I wouldn't try to do it any other way. Yes, you can fix the pinout in the HDL, but it's non-standard, and certainly not portable. Hope that helps, SH On 9 Jun 2003 13:10:34 -0700, kalimuddin@hotmail.com (Muhammad Khan) wrote: >Hi there , > >I am Khan and I have a problem regarding material suppiled by Xilinx. >I am using Xilinx FPGA Editor to view the placed route in actual >hardware. The problem is the proper pin assignment. For example in my >Constraint file I define signal X to pin 57 and when I observed that >particular signal in the editor than I find that this signal is being >placed at pin 107. I am using actual hardware to implement my design >so I can not just download the code in to chip. The package I am using >is HQ240 and device is Xilinx Vertex XCV600 with speed 4. I used all >the above mentioned parameter in my project file. > >Does any body have any idea how to overcome this problem. > >Thanking you in advance.Article: 56588
Hi All, I have several embedded system boards and one of them has a faulty MACH210A IC and I am unable to get the data off the other boards due to the security fuse on the IC is blown. Does anyone know if it is possible to overcome the security fuse and recover the data? Are there any specialty companies that can do this kind of work? Thanks in advance Wes.Article: 56589
80 bits wide, 32 stages, 100 to 160MHz ... that's why I was asking. Thanks, -Martin "Marc Randolph" <mrand@my-deja.com> wrote in message news:15881dde.0306091851.55ec76ca@posting.google.com... > "Martin Euredjian" <0_0_0_0_@pacbell.net> wrote in message news:<8v5Fa.509$9c1.55732444@newssvr13.news.prodigy.com>... > > Xilinx, Virtex II > > > > Are there any architecture-related performance (or other) advantages in > > implementing shift registers with the output on the LSB vs. MSB? In other > > words: > > > > output <= sr[3]; > > sr[3] <= sr[2]; > > sr[2] <= sr[1]; > > sr[1] <= sr[0]; > > sr[0] <= input; > > > > vs, > > > > output <= sr[0]; > > sr[0] <= sr[1]; > > sr[1] <= sr[2]; > > sr[2] <= sr[3]; > > sr[3] <= input; > > Howdy Martin, > > Absolutely... if you feed into the lsb and do not reset those nets, > you can obtain resource savings (flops and routing) by letting the > tools infer an SRL: > > http://support.xilinx.com/xlnx/xil_ans_display.jsp?getPagePath=9785 > > If you have a wide bus, or a deep pipeline wait, the savings can be > considerable. > > There is a slight timing penality associated with this, but you > shouldn't notice it unless you're running well over 200 MHz. > > Have fun, > > MarcArticle: 56590
Hi, Can we use system generator v3.1 to design a system that can map to the Virtex2Pro including program the PowerPC inside? Since from the advertisement of Virtex2Pro Platform which introduce SystemGenerator as a high level design tool for the system design. But I can not find any support in the system generator document is talking about Virtex2Pro HW/SW codesign. There is only XtremeDSP Kit is mentioned which is a virtex2 series product. Also what is WindRiver? Is it a design tool? Thanks! TerrenceArticle: 56591
Hi Terrence, For HW/SW development (HDL-based for the FPGA Fabric, C/C++ based for the PowerPC or MicroBlaze processors) you need EDK (Embedded Development Kit), which includes the GNU toolset. EDK also includes the interface you need to configure the processors and peripherals, and finally merge the two bitstreams to program the FPGA and the PowerPC. EDK includes the netlists of the MicroBlaze and the peripherals. System Generator can help you design at System level using the BlockSets in Simulink which are basically the DSP IPs available in Xilinx ISE CoreGen. SysGen generates synthesizable HDL which you can use in your top-level design. A new interesting feature in SysGen is Hardware-in-Loop which helps you verify your design in hardware and compare these results with the Simulink results. WindRiver-Xilinx-Edition is an additional tool you can use for processor development. This tool includes the OEM edition of the Wind River Diab C/C++ compiler, SingleStep Debugger and a cable for connection (VisionProbe). Hope this helps. "Terrence Mak" <stmak@cuhk.edu.hk> wrote in message news:1055223236.388340@eng-ser4... > Hi, > > Can we use system generator v3.1 to design a system that can map to the > Virtex2Pro including program the PowerPC inside? Since from the > advertisement of Virtex2Pro Platform which introduce SystemGenerator as a > high level design tool for the system design. But I can not find any support > in the system generator document is talking about Virtex2Pro HW/SW codesign. > There is only XtremeDSP Kit is mentioned which is a virtex2 series product. > > Also what is WindRiver? Is it a design tool? > > Thanks! > Terrence > >Article: 56592
Hi all, I'm designing a NIOS based system using custom instruction using Quartus II SP 2. 1) How can I constraint NIOS synthesis without knowing its internal architecture? 2) How can I determine when custom instruction signals (dataa, datab, ...) are ready to start a custom instruction in order to optimize the number of clock cycle it requires? 3) How can I trace a particulare path delay? (I mean something like "trace path from x to y") Thanks AndreaArticle: 56593
>I already said, that for the 24x7 folks, there are well known, and already used >techniques, and cores, that take care of the issue. In fact, I would suggest >that our FPGAs are the only technology capable of performing these functions, >which leads to an interesting thought: how are CPUs, ASIC's and ASSP's going to >deal with this issue? I think it's common to use parity (maybe even ECC?) on large secondary caches. For non-dirty cache info, you can just pretend it didn't get a hit and keep going. I wasn't trying to say that Xilinx wasn't doing a good job - rather the opposite, by publishing some solid data, you are taking a giant step in the right direction - giving designers enough info to know where the rough edges are. (enough rope to hang themselves?) What I was trying to point out is that altough a number like "800 years" may seem huge at first glance, it can still be a serious problem if you are serious about reliability and are shipping many systems. Metastability has the same sort of issues. The numbers on systems with large RAMs are scary/interesting. There is a large collection of data on error statistics and what to do about it. I think the main item is to touch each ECC block occasionally and do a read/rewrite to fix the bad bits. (buzzword is memory scrubbing) Jim Gray (Tandem) had a neat talk on why "Non Stop" systems Stop. Power and air-conditioning were reasonably high on the list. I think operator error was the top. Yes, you have to work hard to get to that point. (But the "hard" part may be resisting the temptation to "fix" things that don't really need fixing.) -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 56594
Hello I have a problem with programming the XC95288-HQ208-15 device. I can see the chip in JTAG chain and I can erase it. Unfortunately, a program process was failed. I have used the ISE 5.2.02i and the ISE 5.2.03i software. In the ISE 5.2.02i a program process was failed. In the ISE 5.2.03i a program process was hanged. The device worked correctly for 2 years and now I was trying to reconfigure it. Did anybody have a similar problem? Regards, KrzysiekArticle: 56595
"Krzysztof Szczepanski" <kszczepa@poczta.wp.pl> schrieb im Newsbeitrag news:bc442u$bfs$1@korweta.task.gda.pl... > Hello > > I have a problem with programming the XC95288-HQ208-15 device. I can see the > chip in JTAG chain and I can erase it. Unfortunately, a program process was > failed. > I have used the ISE 5.2.02i and the ISE 5.2.03i software. > In the ISE 5.2.02i a program process was failed. > In the ISE 5.2.03i a program process was hanged. > > The device worked correctly for 2 years and now I was trying to reconfigure > it. > > Did anybody have a similar problem? > > Regards, > Krzysiek > > > > Any clocks connected to the pld ? The chip must not have any free running signal on any pin during programming. see: http://www.xilinx.com/xapp/xapp104.pdf MIKEArticle: 56596
I believe Benoit wants to transfer the pinout in the opposite direction. KrestenArticle: 56597
hmurray@suespammers.org (Hal Murray) wrote: >>Absolutely... if you feed into the lsb and do not reset those nets, >>you can obtain resource savings (flops and routing) by letting the >>tools infer an SRL: > >Are the tools not smart enough to recognize the other pattern? >(left shift vs right shift, if you want to think that way) You'd think so, but apparently not according to the link. Pardon if this is a common question, but is there any sort of standard for inferring complex functions? I've used 4 VHDL compilers, and they each had differences. (The most recent spec I've got to hand is IEEE 1076-1993 and that doesn't even mention flip-flops) -- Dave FarranceArticle: 56598
I'm generating a edf file with Symplify Pro. When I want to place&route or generate a bit file with the project navigator, the XILINX tool doesn't use my ucf file with all my pin assignments. This does not happen when I synthesise the whole design with the project navigator. Anyway I can see all the constraints and pin assignments in the constraints editor (exactly what is in the ucf file) but the tool generates another pin assignment. Does anybody have an idea why this could happen? Does it have anything to do with the pcf file? Thanks for any help. ThorstenArticle: 56599
Benoit <bhb22l@yahoo.fr> wrote: : Hi all, : I have just finished my scheme (Orcad) with a big stratix and I would like : to insert automatically I/Os in : Quartus. : Can anyone describe me a method ?. Export a netlist from Orcad, Scan for the Connections to the FPGA and generate a constraint file for Quartus. Omit supply, Jtag and probably programming connections to the FPGA. That is at least what I do for eagle. Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
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Compare FPGA features and resources
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