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Another fun application of FPGAs. http://www.fpga4fun.com/RCServos.html I'd like to build a CD-changer robot now. But the mechanical part is tough... JeanArticle: 57776
mrand@my-deja.com (Marc Randolph) wrote in message news:<15881dde.0307040458.4365e54@posting.google.com>... > yuhaiwen@hotmail.com (Yu Haiwen) wrote in message news:<4c1bc2c3.0307031906.4b53145@posting.google.com>... > > such a application > > 40MHz clkin, 20MHz clkdv output and 30MHz clkfx output > > use clk0 feedback to clkfb > > > > can both the clkdv and clkfx's de-skew be guaranteed? > > Howdy Yu, > > What exactly do you mean by the "clkfx de-skew" portion of your > question? Considering that there is no fixed phase relationship > between asynchronous clocks (like your 30 MHz and 40 MHz), what good > would the de-skew be? > > If you post a more complete description of your application, it would > likely result in multiple responses, possibly each outlining a > different way to meet your requirements. > > Good luck, > > Marc Thanks for your suggestion. Let me explain the situation. When we use the DLL function of DCM. All DCM output clocks are phase-aligned to CLK0 and, therefore, are also phase-aligned to the input clock. There's no problem if I only use one of the clkdv output or clkfx output. But now I want to use both the tow output clocks, can they still both phase-aligned to clkin? I've read the Xilinx answer record 12582, which sugest to use tow DCMs in series. Though my application is a little different, and I'm thinking how about using tow DCMs in parallel. Would there be any improvement?Article: 57777
rickman <spamgoeshere4@yahoo.com> writes: > Thomas Heller wrote: >> >> Steve Lass <lass@xilinx.com> writes: >> >> > Jim Granville wrote: >> > >> >> Can we get a quick summary of what's removed, and what legacy >> >> versions of SW are needed to support which family ? >> >> >> > The current software (version 5.1i, 5.2i, 6.1i) supports Virtex, >> > Virtex-E, Virtex-II, Virtex-II Pro, Spartan II, Spartan IIE, and >> > Spartan-3. >> > ISE Classics (version 4.2i) supports XC4000E, XC4000L, XC4000EX, >> > XC4000XL, XC4000XLA, Spartan, and SpartanXL. >> > >> > Contact the hotline if you need software for: >> > 3.1i supporting XC3000A, XC3000L and XC5200. >> > XACT 6 supporting XC2000, XC3000, and XC4000, XC4000A and XC5200. >> >> This sounds like I better terminate my Xilinx software subscription, and >> use the free versions instead. >> >> I recently changed my PC to a new one, and tried to install the licensed >> version of ISE 4.2, because I need Spartan and Spartan XL. It was a >> pain to make it work again because one design uses FPGA express, and it >> always complained about the license being invalid. >> >> The only solution was, as a Xilinx FAE told me, to use use tool to >> change the volume serial number of my hard disk to the one that the old >> PC had. Fortunately I didn' have to reregister Windows XP again. > > Which tool did you find that would let you change the disk serial > number? http://www.sysinternals.com/ntw2k/source/misc.shtml#VolumeIdArticle: 57778
Hi, does anybody have detailed information on what conditions contention occurs, while dynamically reconfiguring Xilinx Virtex devices? Xilinx FAQs say short term reconfiguration (<30 ms) of large modules across multiple columns won't damage a Virtex device. What does "multiple" mean? If I take the 30 ms boundary seriuosly a full (re)configuration would destroy the device :o) Is it possible to create a reconfigurable design with a static and a dynamically changed module arranged on top of each other (share the same columns)? Actually, it should work with differential bitstreams due to the fact that only bits are toggled that where modified. Cheers, ChristianArticle: 57779
antti@case2000.com (Antti Lukats) wrote in message news:<80a3aea5.0307040005.6e6ba1ab@posting.google.com>... > impact generates JAM files, well called STAPL but it is the same thing. > there are some problems though most of the files generates will not > work with non-patched JAM player :( > > antti Are there any required patches somewhere for download? Or do i have to write my own one?Article: 57780
"Brad Smallridge" <bsmallridge@dslextreme.com> wrote in message news:vgbmmurk77rs22@corp.supernews.com... > A follow up: > > Someone sent this solution to me and said it would provide no assymetrical > delays and would be better than a long elsif chain. "Better" is a style choice. The "assymetrical delays" (sic) is a canard caused by the respondent's lack of understanding of VHDL signal assignment, I suspect. The meaning of the VHDL is the same in both cases. As you say, a good synthesis tool should give the same results for both (it's not really a "fitter" problem). Finally, any design that relies on symmetry of delay through synthesised asynchronous logic deserves to fail. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK Tel: +44 (0)1425 471223 mail: jonathan.bromley@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 57781
Hello I want to use Spartan XL FPGA for a project and found out that my installation of the Xilinx ISE 5.2 i (Alliance) does not support this device. I can only install later versions of the Spartan devices and not the XL family. Can I get some suggestions on what I should do to use Spartan XL? I dont want to go to the WebPack Option. Thanks AnupArticle: 57782
consider the following code: (the rom is essentially a RAMB4_S1 block) -- rom ROM port map ( CLK => Clock, -- get data at rising edge ADDR => BUS_Address(11 downto 0), DATA => local_Data ); debug <= local_Data; process(Reset, Clock, ChipSelect, BUS_WriteEnable) is begin if(Reset = '1') then BUS_DataOut <= (others => 'Z'); elsif(falling_edge(Clock)) then -- present data at falling edge if(ChipSelect = '1' AND BUS_WriteEnable = '0') then BUS_DataOut <= local_Data; else BUS_DataOut <= (others => 'Z'); end if; end if; end process; when doing a simulate "post translate VHDL model" or simulate "post map", everything works fine when doing a simulate "post place and route vhdl model", it fails; all my outputs are 'XX' and I get pages of the following warning: ** Warning: */X_RAMB4_S1 SETUP Low VIOLATION ON ADDR(9) WITH RESPECT TO CLK; # Expected := 1.04 ns; Observed := 0.12 ns; At : 6.7 ns # Time: 6700 ps Iteration: 1 Instance: /testbench/uut/rom_inst5 any idea what is wrong? (I'd like to point out that in real life, it is actually working, but I'd like to straighten it out in the simulator)Article: 57783
Hi Anup, Current 5.2i version does not support SpartanXL. For using the XC4000 or Spartan/XL devices, you should download the free ISE-Classics package (which is basically version 4.2i +Sp-3) from here for the PAR support (no synthesis): http://www.xilinx.com/webpack/classics/index.htm For synthesis, you should use the old FPGA Express if you still have the license, or go with a 3rd party synthesis tool like Leonardo/Synplify. If you are based in India, I can help you with a CD, send me an email offline. --Neeraj "Anup Kumar Raghavan" <araghava@asc.corp.mot.com> wrote in message news:3F09321B.786229F8@asc.corp.mot.com... > Hello I want to use Spartan XL FPGA for a project and found out that my > installation of the Xilinx ISE 5.2 i (Alliance) does not support this > device. > I can only install later versions of the Spartan devices and not the XL > family. > > Can I get some suggestions on what I should do to use Spartan XL? I dont > want to go to the WebPack Option. > > Thanks > Anup > > >Article: 57784
Major thanks to Mike Tressler, Peter Alfke, and Philip Freidin for all of the advice concerning my syncronization problems, specifically the dreaded 'data crossing clock domains' problem. I had a good feeling this might have been contributing to my difficulties, but you folks put this into words in a way I could understand WHY it was causing problems, and also offered suggestions for remedying the situation. I'm happy to report that I have completely cleared all of my issues 100% as of this morning! All of the strange behavior has now been explained, and I have a much more solid understanding of how to write these things properly in VHDL! :D Special thanks to Philip Freidin - there was a usenet article of his I dug up out of the archives from Dec 2001 that specifically explained the clock-domain-crossing problem, and an elegantly stable solution for reliably detecting asyncronous clock edges coming from other domains. It can be found here: http://www.fpga-faq.com/archives/37250.html Thanks again guys - this has solved an incredibly irritating problem that has been eating at me for the past two weeks! All the best, -- MattArticle: 57785
"rickman" <spamgoeshere4@yahoo.com> wrote in message news:3F08C992.AB23BADB@yahoo.com... > Andy Peters wrote: > > > > rickman <spamgoeshere4@yahoo.com> wrote in message news:<3F07008B.5E495267@yahoo.com>... > > > I just tried to install the Quartus II web edition software and I see > > > that to get a license I need to have an Ethernet card. Does Altera > > > provide for any other sort of license? It seems silly to require me to > > > buy and install an Ethernet interface just so they can key a license for > > > *free* software. > > > > Rick -- ask the REAL question: why do they continue bother with the > > licensing bullshit AT ALL, esp. for FREE SOFTWARE that enables us to > > design with their chips? Rant rant rant. > > > > If I had a nickel for every minute I've wasted on FlexLM, I'd retire. > > I would very much like to rant until they dropped the licencing on the > free tools. But I feel I rant a bit too much already and I don't want > to alienate anyone (or anyone more than I have). I know that sometimes > I push buttons with Peter and Austin. I hope they don't mind too much. > > I remember telling the Orcad people what I thought of their new > licensing scheme when they were bought by some larger, high end player. > The new owners felt that Orcad should have high end licensing and I let > them know that I would not be installing the upgrade because of it. I > belive it would have required me to either buy an Ethernet card or to > use a dongle. These days I am not willing to do either to use > software. But a hard drive key is within my comfort zone. I know that > if I replace my hard drive I can set my own serial number and be back on > the air without depending on them. Orcad is one company I will *never* > depend on for anything. > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAX Hello Rick, Would you care to explain how you set the serial number ? I've looked before but never been able to find out how. Michael Kellett www.mkesc.co.ukArticle: 57786
Hi, I am using Quartus 2.2 SP2 with Nios 3.0 I have fit my logic with the SOPC into the Niosstructure and generating and compiling of this is fine. I am testing on a stratix devel. board. Programming of the fpga works out fine too. The problem is, that no programm runs on the nios. (i.e. hello_world) The srec file is downloaded to the chip and then just the terminal appears. (nr -r hello_world.srec) After I press the CPU-Reset the nios string appears. So it seems like the programm is running in an endless loop. If I use the nios-consol I am able to access the peripherie, like turning on/off the leds in writing directly to the addresses. By the way, without my logic the nios executes the code. Has anyone an idea what the reason could be ? Thanks ThorstenArticle: 57787
<cut> > > Arius - A Signal Processing Solutions Company > > Specializing in DSP and FPGA design URL http://www.arius.com > > 4 King Ave 301-682-7772 Voice > > Frederick, MD 21701-3110 301-682-7666 FAX > > Hello Rick, > > Would you care to explain how you set the serial number ? > I've looked before but never been able to find out how. > > Michael Kellett > www.mkesc.co.uk > Just using the program "VOLUMEID.exe" from the www.sysinternals.com site. Bye GiuseppeArticle: 57788
Eventough they claim that XC3S1000 is about $20, actual price at avnet.com is about: 1 - 24 @ $248.6000 25 - 99 @ $191.4000 So, what is the price for the quantity of 1K-10K of XC3S1000? rickman <spamgoeshere4@yahoo.com> wrote in message news:<3F064C7F.E2E7E863@yahoo.com>... > Uwe Bonnes wrote: > > > > Manfred Kraus <news@cesys.com> wrote: > > : I got a call from Insight. Of course I can get samples of the ESJ-part > > : immediately. > > : The Problem was, that I didn't ask for ESJ-Parts. They assumed I know what > > : to ask for. > > > > The problem is also, that distributors often ask for an exact number, while > > the user mostly needs _any_ part with only few constraints. That way, you > > have to prepare a lot of fallback fits, and ask the distributor for each. > > > > If they could cope with wildcards in the part number, things would be > > easier... > > You are looking at using some 30 to 100 parts on your board. The distis > have to deal with thousands of parts every day. It is very hard for > them to keep up with what means what in the part numbers. It is much > better if you tell them the variations in part numbers that you can work > with. Normally the only option you have is a faster speed or a wider > temperature (which often does not make a part *more* available). I have > been able to give them a starting part number and tell them that this > letter is a don't care and they can tell me what is up with inventory > and product volume. > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAXArticle: 57789
Tolga wrote: > > Eventough they claim that XC3S1000 is about $20, actual price at avnet.com is about: > > 1 - 24 @ $248.6000 > 25 - 99 @ $191.4000 > > So, what is the price for the quantity of 1K-10K of XC3S1000? You are not going to get a good price on a part that is so far from production. From what I have read about the expected prices, I would guess that you can expect a price below $30 at those volumes. But the XC3S1000 is now one of the later parts to be in production and may not be available until 1Q04 or later. Even if they make the 4Q03 prediction, the price will likely not come down much until 1Q04 or later. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 57790
Hi Bob, I suspect that you're violating this specification of the OPB: "All OPB devices (masters and slaves) are required to output logic zero when inactive." (page 13 of the Proc IP Reference Guide) If that's the case then you're causing contention on the OPB when the pwm core is inactive but another peripheral on the OPB becomes active. You may be accounting for this with additional logic, but if not then you need to make sure that the core is puting out '0' when inactive. Best regards, Ryan Laity Xilinx Applications GpsBob wrote: > Using the Memec MB1000 eval board with the Virtex-2 on it, I tried one > of the Memec projects "Lab06_Own_Periph_VirtexII1000". Building this > under the EDK 3.2 works fine on eval board. But, if I change line 163 > of the file "opb_pwm_core.vhd" which reads: > > SIn_DBus(I) <= '0'; > > to > > SIn_DBus(I) <= '1'; > > which just changes the default output of the user IP, the system just > hangs after downloading the bitstream to the eval board. Any ideas? > Could there be some kind of contention within the OPB bus? I assume > that contentions are generally caught by the synthesis tools. If I > inspect the automatically generated vhdl, it seems that the bus > interfaces are generated correctly for the various peripherals tied to > the OPB bus. So, I'm at a loss as to why this is happening! > > Bob > >Article: 57791
40 MHz has a period of 25 ns, and 30 MHz has 33.33333 ns. They meet every third period of 30 MHz = every fourth period of 25 MHz. Peter Alfke Yu Haiwen wrote: > > such a application > 40MHz clkin, 20MHz clkdv output and 30MHz clkfx output > use clk0 feedback to clkfb > > can both the clkdv and clkfx's de-skew be guaranteed?Article: 57792
Hello to All I don't know what I did wring but I've uninstalled Nios by mistake and when I try to install it back, I get the following messages when I run the sopc_builder and also the bash: bash.exe: warning: could not find /tmp, please create! bash: uname: command not found bash: grep: command not found bash: uname: command not found bash: grep: command not found bash: uname: command not found bash: grep: command not found bash: uname: command not found ... This is very weird, because when I try to go directly to C:\Altera\Excalibur\sopc_builder_2_5\Cygwin\bin and double click the bash.exe file I also get a message saying that /tmp is not found and it does not know any commands (grep, uname, ls etc). I've uninstalled and reinstalled Nios but with no success. One success I did have though: when I log in as a different user all is well. The problem is that I don't to log in as a different user each time I have to work on Nios. This has happened a few times to other people in my company and we could not get any help from our local Altera representative. I'm sure someone here must have encountered this in the past. Please help me Thanks in advance NirArticle: 57793
If you are dc coupled, then dc offset does not matter. Don't worry! Peter Alfke Guest wrote: > > Hi everyone, > Iam an student having doubt in LVDS communication, > Let say xilinx vertex FPGA is used for this pupose. > I have LVDS transmitter and receiver, No AC coupling is been > used between them. > > Let say transmitter is in one board and receiver is in another board > connected through backplane (no AC coupling), > > I am not recoevring the clock at the receiver, clock (77.77MHz) given > to both transmitter and receiver through single source. > Do i need to use any scrambling or encoding techniques before > transmitting the bit stream over LVDS to remove DC offset for better > BER? > > Thanks in Advance,Article: 57794
I ran into similar problems and it was 100% due to my custom logic. Always because of a fclk violation. When you compiled the HDL design in Quartus did you receive timing violations? Sometimes my HDL design would still run even with the timing violations... this appears to be a side effect of instruction and data caching in the NIOS CPU. When eliminating the caching, my HDL design would not run at all with the timing violations. Fixing the timing violations allowed the NIOS CPU to run... it didn't mean my custom logic was correct though. At least when the CPU is running you can use the debugger in the SOPC directory tree to see what's going on with your application and try to figure out what's up with the custom logic interface. Jim "Thorsten Klatt" <tklatt@mut-gmbh.de> wrote in message news:<bebmr2$pi6$1@news.shlink.de>... > Hi, > I am using Quartus 2.2 SP2 with Nios 3.0 > > I have fit my logic with the SOPC into the Niosstructure and generating and > compiling of this is fine. > I am testing on a stratix devel. board. Programming of the fpga works out > fine too. > The problem is, that no programm runs on the nios. (i.e. hello_world) > The srec file is downloaded to the chip and then just the terminal appears. > (nr -r hello_world.srec) After I press the CPU-Reset the nios string > appears. So it seems like the programm is running in an endless loop. > If I use the nios-consol I am able to access the peripherie, like turning > on/off the leds in writing directly to the addresses. > > By the way, without my logic the nios executes the code. > Has anyone an idea what the reason could be ? > > Thanks ThorstenArticle: 57796
> I found some linux stuff (.h files, .so files, python, etc) still looking > for the c compiler, (on the microdrive). GCC has been removed from the target file system. Please keep in mind that the MicroDrive contains a Linux demo, and a pretty extensive one this is, and not a development system. > and montavista, guess it makes sense to ask for ver 3.0 > ml300 microdrive has 2.1 Professional installed. When the ML300 went into production MVL3.0 was not yet released. - PeterArticle: 57797
something like this in verilog.....
// Now we can use long division to determine the result
for (bit = 16; bit >0; bit=bit-1) begin // for all bits
diff = dividend - divider; // calculate difference
SdivF = SdivF << 1; // Shift result
if( !diff[31] ) begin // If negative
dividend = diff; // add one
SdivF[0] = 1'b1;
end
divider = divider >> 1; // else shift
end // bit = bit - 1;
Try google search for homework answers
Dave
"Mario Trams" <mtr@informatik.tu-chemnitz.de> wrote in message
news:bea7c6$g5a$3@anderson.hrz.tu-chemnitz.de...
> Replace_latter8717_with_manorsway wrote:
>
> > remember log division from schoool, now try that in base 2!
>
> Yes.
> And then develop a hardware design that can do that...
>
> When this is done, it's a small step to describe it in VHDL.
>
> Regards,
> Mario
>
> >
> > "Ketan" <ketone007sa@yahoo.com> wrote in message
> > news:cf47f3cc.0307042130.1eec1888@posting.google.com...
> >> hello there
> >> i am relatively new to VHDL..this might sound simple
> >> any ideas how to carry out division (floating point) in VHDL??
>
> --
> ----------------------------------------------------------------------
> Digital Force / Mario Trams Mario.Trams@informatik.tu-chemnitz.de
> Mario.Trams@wooden-technology.de
> Chemnitz University of Technology http://www.tu-chemnitz.de/~mtr
> Dept. of Computer Science Tel.: (+49) 371 531 1660
> Chair of Computer Architecture Fax.: (+49) 371 531 1818
> ----------------------------------------------------------------------
Article: 57798In <9b862770.0307070826.214d4754@posting.google.com> Nir wrote: > I've uninstalled and reinstalled Nios but with no success. One success > I did have though: when I log in as a different user all is well. The > problem is that I don't to log in as a different user each time I have > to work on Nios. I do not know NIOS development kit, but try to compare environment variables in non-working and working user account, then fix it. This should do the trick. Not sure if it's the matter of Win environment, or missing bash startup file. It looks more like cygwin problem, not NIOS DK itself. Regards ChrisArticle: 57799
You can get free tools for the SpartanXL here: http://www.xilinx.com/ise_classics/index.html Anup Kumar Raghavan wrote: >Hello I want to use Spartan XL FPGA for a project and found out that my >installation of the Xilinx ISE 5.2 i (Alliance) does not support this >device. >I can only install later versions of the Spartan devices and not the XL >family. > >Can I get some suggestions on what I should do to use Spartan XL? I dont >want to go to the WebPack Option. > >Thanks >Anup > > > > >
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