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Anup Kumar Raghavan <anup@csee.uq.edu.au> writes: > Hello, is there a way to verify Virtex bitstreams before they are > downloaded onto the device? I am modifying Virtex bitstreams using JBits > and want to verify or simulate my modify design at this level? Well, if you are using JBits, there are the BoardScope and VirtexDS (nee DeviceSimulator) Tools in there. Have you looked at those? -- Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/ Hacker, Unix Guru, El Eng HTL/BSc, Programmer, Archer, Blacksmith - hardware runs the world, software controls the hardware code generates the software, have you coded today?Article: 58051
Many of the comments here have been great. I would add this from some thoughts and experience in layout. If the device is not being used near any RF circuitry then the bypass caps are of adequate value. If there is nearby RF circuitry then add either 100pF or 30pF caps. The 100pF is good for VHF frequencies and the 30pF cap is good for UHF. I would change from tant caps to ceramic for the 10uF caps though. Still all the steps used to elliminate EMI suggested are good. A note on the 208 pin package, it is big and it will radiate no matter how careful your bypasses are and board layout. I reccommend that the you do a signal layer, followed by a ground layer, then power, and finally the bottom layer can be mixed but should primarily be signal. The power layer can have multiple voltages on the plane. It is best to keep a 20 to 1 separation between powers. Thus if you are using a 0.062 laminate, you will have between 18 and 22 mils between layers. I then would leave at least 40 mils preferably 80 mils between traces on the different power busses. This will minimize E-fields that fringe off the power runners. I am not a big fan of blind vias as Xilinx shows in their app note. They are expensive and difficult to troubleshoot. Heaven forbid if one is open either. The board is then shot. Avoid them at all costs. Vias to the ground plane and power should be at least two of them per trace. Especially in high current, peak or constant, traces. Good idea in case the PCB fabricator screws up on the plated through holes. Vias through the power and ground planes should have at least 20 mil anular space around the via. More on faster switching lines if possible. One very important thing. Layout power and ground first. Before you route any signal line do power and ground first. They should be as direct from the source to the devices as possible. Avoid power loops. Branch power from the power buss to the components. Also keep all power runners 40 to 80 mils from the edge of the board. Ground plane can extend to about 10 mils to the edge. Signals should not be closer than 20 mils to the edge. some thoughts james On Fri, 11 Jul 2003 15:51:01 -0400, "..:: Gabster ::.." <gabsterblue@hotmail.com> wrote: >Hi, > >I'm made many 2-layer PCB's in the past years, but I'm about to start the >desgin of my first 4-layer PCB. The board is basically a FPGA (Xilinx >Spartan IIE XC2S300 in PQ208 package running at ±12MHz), 3 power supply >regulators, an oscillator block, a PROM and a logic IC. > >In addition to other literature, I read the following document: >http://www.xilinx.com/xapp/xapp623.pdf >but it is rather complicated and not straight foward for a rookie like me in >FPGA design! So here's a few direct questions: > >1) 4-layer, why is it so important? > >2) In what order should I stack the layers (TOP/GND/POWER/BOTTOM or >TOP/POWER/GND/BOTTOM), why? > >3) Decoupling caps surroung the FPGA: I figured out I needed one 0.1µF per >power pin (1.8V and 3.3V) + one 10µF per power supply (1.8V and 3.3V). Is >that accurate? Should I do more? What should I avoid? > >4) What is the concept surrounding islands on the power plane? What should >that plane look like? What should I avoid? What the hell about it, this >plane is a mystery for me!!! > >In order to avoid asking 1000's other questions, I wonder if someone could >also direct me toward a complete document talking about PCB design >guidelines for PQ package FPGA's. I found that for the BGA packages on >xilinx website, but it didn't help me much. > >Thanks a lot, >Gabriel >Article: 58052
"Allan Herriman" <allan_herriman.hates.spam@agilent.com> wrote > <Marc.Battyani@fractalconcept.com> wrote: > > >> I sometimes find myself in the situation of having to work out the > >> spectral characteristics of the phase noise (jitter) of the msb of a > >> phase accumulator. E.g. if I am using a post-NCO PLL (as Peter A. > >> suggested) then I only care about the phase noise components at offset > >> frequencies less than the loop bandwidth of the PLL. > > > >I thought about filtering and integrating the phase error after the phase > >comparator. I don't think I need a PLL as I'm not synthesising a frequency. > > You are synthesising a frequency with the NCO, even if that wasn't > your intention. > > >> I don't know of a closed form expression for spectrum of the noise, > >> but it's trivial to work out the spectrum with a spreadsheet (once you > >> know how). This is much easier that trying to measure the spectrum in > >> the lab. > >> (Reply if you are interested in the method.) > > > >Sure, please explain how to do it, I'm really interested. > > Rough description here: > http://groups.google.com/groups?threadm=379cf6a6.1375761%40newshost I've read it. Very interesting. I would be interested by your spreadsheet if you are still willing to email it. MarcArticle: 58053
"maxfoo" <maxfoo@punkass.com> wrote > <Marc.Battyani@fractalconcept.com> wrote: > > >I want to make a phase measurement at 100MHz with a NCO at 200+ MHz > >This NCO will have a 32 bit phase accumulator and a 32 bits phase offset. The > >output will be only one bit. > >I will use a phase comparator followed by an integrator (digital or analogic > >if needed). > >At 100MHz the NCO output will be very very noisy but if I integrate it for a > >rather long time (10ms) will it have a 0 mean ? > >Can I implement this in an FPGA or should I use a DDS chip (AD9854) ? > >Where can I find some maths on this subject ? > > I've used the Ad9954 DDS and the phase noise is about -140dBc/Hz @ > 10KHz 0ffset. Your clk ref needs to be better than that if you want an > accurae measurement. I used a DRO for the reference and an Agilent > E5500 phase noise test set to measure it. Download the Analog Devices > dds tutorial for all the math involved. The AD's DDS are really nice and I have already used 3 AD9854 with an XC2V1500 on a same board. But here I am trying to see if I can go without them... Otherwise I will use an AD9954. MarcArticle: 58054
On Sun, 13 Jul 2003 04:22:54 -0000, hmurray@suespammers.org (Hal Murray) wrote: >>If you can arrange all the parts for for each voltage together, it should be >>easier. Then put the regulators near the junction between the different >>voltage planes. > >I think the star approach comes from the analog guys. > >The idea is that heavy currents in one section won't add IR drop >on the ground traces of another section that is processing >low level signals. The cost is another (ground) wire for the >low level signal. ********************************************* To some point yes. Actually more from when digital and RF circuits reside near each other. Clock signals and high and medium speed switching lines generate harmonics well into the VHF region. Add any loops in the signal or power runners along with distributed capacitances can form a resonace that will reradiate undesired signals to the RF circuits. There are also harmonics that are conducted on power and signal lines common to both digital and RF circuits. Conducted harmonics are easier to minimize than radiation from traces. Radiation from the ICs themselves can really only be minimized by reduced package size. Chip on board/glass is by far the best to minimize IC radiation. Costly as it requires fine pitch runners, 3 mil or less runner widths and spacing. Also requires that IC fabrication to be compatable to direct chip placement. jamesArticle: 58055
"Jim Granville" <jim.granville@designtools.co.nz> wrote > Marc Battyani wrote: > Sounds challenging : If I have this right > You have 100MHz 'incomming' (hopefully very clean and phase stable :) > You want to lock to 0.1%, (or 10ps), nominally 200MHz local Osc > You can tolerate longer lock acquire times > > Analog Phase locked loops work because they integrate > the phase-magnitude errors, > - In a digital system, edge resolution of 10ps may be just possible, but > I'm not sure you can get any error-proportional siganl. > Go-right/Go-Left control is likely to be swamped by the phase-noise of > the DDS signal..... I don't need the 10ps resolution as I'm only interested in the low frequency phase measurement. Even if I have a 2ns jitter, I don't care if the mean value of the jitter is 0 after low pass filtering. MarcArticle: 58056
l nguyen wrote: > Hello everyone, > > I can't use Foundation 4.2 Aldec simulator to simulate CLKFX, no matter > what I set the M and D, the CLKFX is always 4x. The "Answer Record # > 11736" doesn't help much. What kind of simulator do I need to work with > Foundation SW? please I don't have a specific answer, but a suggestion on something to look into. The DCMs are funny in that for synthesis you set the parameters (like M & D) via attributes or constraints, whereas for simulation you use the VHDL generics. So, make sure you have consistency between your generic instantiations and synthesis attributes. It's a painful state of affairs, probably would be a good idea to put a wrapper around the whole thing that takes VHDL generics and instantiates a DCM with *both* synthesis attributes *and* simulation generics set properly. Hope this is useful, JohnArticle: 58057
Stifler, do what your mother should have taught you: wash out your mouth with soap. We do not tolerate your arrogant tone in this newsgroup. Rickman has made many valuable contributions to this newsgroup, which is more than can be said about you. Style derailments like yours must be "nipped in the bud," to use a mixed metaphor. Now, lets get back to our normal civilized and helpful tone. Peter Alfke Stifler wrote: > > Rick, > > You are missing something. Any shred of digital design capability or > ability to solve any problem on your own. Why don't you just give up? > McDonald's is always looking for someone with your ability. > > I would recommend you go to college and get a BSEE. Concentrate on > digital design techniques. > > Is Arius even a company? I'd be embarassed if my boss could see my > incompetence so publicly. You must be the CEO, President, VP of > Engineering and lone grunt at Arius all rolled into one. > > Good luck buddy. > > Stifler > > rickman <spamgoeshere4@yahoo.com> wrote in message news:<3F0EEEC8.D5038C4B@yahoo.com>... > > Amontec Team wrote: > > > > > > For myself, I never use both ieee.numeric_std.all and > > > ieee.STD_LOGIC_ARITH together ... can produce many troubles since there > > > describe same functions. It is very dangerous, because the compiler or > > > syntheziser can interprete different things. > > > > > > For your code, why > > > ELSE STD_LOGIC_VECTOR (7 downto 0)'(others => 'Z'); > > > > > > and not > > > ELSE (others => 'Z'); > > > > > > maybe this casting can be not so nice, try to skip it, you very don't > > > need that! > > > > I need to sit back down with my books! It has been so long since I have > > written VHDL that I don't remember what all the libraries do. I do > > remember that you want to use numeric_std rather than the Synopsis > > signed and unsigned libraries. > > > > The type cast was held over from where I started with this example. I > > started with a 16 bit data bus and an 8 bit register. I had it written > > to force the unused bits to 0 like this... > > > > Data <= STD_LOGIC_VECTOR (7 downto 0)'(others => 'Z') & ScratchReg; > > > > This is the sort of thing that is not always obvious in VHDL since the > > strong typing can get in the way of what you want to do. I remember > > that aggregates and concatenation could give errors very easily between > > the language *features* and the compiler bugs. > > > > Now my work is to build this up into a useful circuit while mapping out > > all the quirks of the tools. > > > > -- > > > > Rick "rickman" Collins > > > > rick.collins@XYarius.com > > Ignore the reply address. To email me use the above address with the XY > > removed. > > > > Arius - A Signal Processing Solutions Company > > Specializing in DSP and FPGA design URL http://www.arius.com > > 4 King Ave 301-682-7772 Voice > > Frederick, MD 21701-3110 301-682-7666 FAXArticle: 58058
Denis, I assume (correctly?) that you implement your logic in Xilinx or Altera FPGAs. In these parts, the logic is implemented in 4-input look-up tables, and the distinction between AND, OR, and INV is meaningless. It all ends up as the through-delay in a ROM with 4 address inputs and thus 16 stored bits. You can, however, force the software to use one LUT for each gate, but there still is no systematic difference between different gate types. I might suggest the clock phase adjust feature in Virtex-II, where you can define and even step the clock output in increments of (one clock period divided by 256) or 50 ps. That might give you a far more predictable solution, and it would be a synchronous design, which we all prefer. Peter Alfke, Xilinx Applications ============================ Denis Gleeson wrote: > > Hello All > > I have a combinational logic circuit generating a number of waveforms > from the main clock input. There are a number of external inputs to > this circuit controlling the turning on and off of different outputs. > > My problem is that I need a certain timing relationship between four of > the outputs. > > I realise that normally to obtain a given timing relationship one would > use synchronous logic. But in this case as I require signals with the > same frequency as the main clock I must use combinational logic. > > From the output of my logic simulator I am seeing some issues which > confuse me: > > (a) Different logic gates have different delays, A NOT has less delay than > an OR gate. May be this should have been obvious to me. Is it correct? > > (b) If I add a gate to create a delay, it seems to be getting optimised out. > Is there some way to stop a gate added for this purpose from being removed? > > Thanks for all assistance in advance. > > DenisArticle: 58059
James,
Some good points, however I will disagree on two issues. First, I
personally do my power routing last on multilayer boards. I expect that I
will need to shove some traces slightly in order to get them in. However,
for me this gets better overall routing with very short traces to power
pads. The one exception to this is in FPGA designs where I do carefully
route the FPGA supplies first. Even then I expect that I will need to do
some substantial re-routing to finally get all the signals in.
Also, I detest high value ceramics. From painful experiences with
strange leakage behavior (such as behaving like a low voltage zener) I am
now avoiding them like the plague.
Of course, these are only my personal experiences. The routing, I am
sure is puerly a matter of personal preference. I know that many people use
large value ceramics with no problems, so consider that to be just a
warning. If you see the same issues, then you usually can get away with
mounting a small tantalum on a large (1206 size or bigger) ceramic as long
as the voltage is very low. By the way, I use many more bulk capacitors
that the norm as I have had problems with noise showing up in the low noise
analog parts of my system. On a spartan2e, I am using 8 0.1uf ceramics and
8 10uf 4v tantalums per supply (1 pair {tant and ceramic} per bank per
supply) . And before you ask... Is that _really_ necessary? Yes, it does
seem to show up in the final system noise behavior.
Thanks,
Theron
<james> wrote in message news:cog3hv8kgkapng9q83fr24h9n7nqtgiud3@4ax.com...
> Many of the comments here have been great.
>
> I would add this from some thoughts and experience in layout.
>
> If the device is not being used near any RF circuitry then the bypass
> caps are of adequate value. If there is nearby RF circuitry then add
> either 100pF or 30pF caps. The 100pF is good for VHF frequencies and
> the 30pF cap is good for UHF. I would change from tant caps to ceramic
> for the 10uF caps though.
>
> Still all the steps used to elliminate EMI suggested are good. A note
> on the 208 pin package, it is big and it will radiate no matter how
> careful your bypasses are and board layout.
>
> I reccommend that the you do a signal layer, followed by a ground
> layer, then power, and finally the bottom layer can be mixed but
> should primarily be signal. The power layer can have multiple voltages
> on the plane. It is best to keep a 20 to 1 separation between powers.
> Thus if you are using a 0.062 laminate, you will have between 18 and
> 22 mils between layers. I then would leave at least 40 mils preferably
> 80 mils between traces on the different power busses. This will
> minimize E-fields that fringe off the power runners.
>
> I am not a big fan of blind vias as Xilinx shows in their app note.
> They are expensive and difficult to troubleshoot. Heaven forbid if one
> is open either. The board is then shot. Avoid them at all costs.
>
> Vias to the ground plane and power should be at least two of them per
> trace. Especially in high current, peak or constant, traces. Good idea
> in case the PCB fabricator screws up on the plated through holes. Vias
> through the power and ground planes should have at least 20 mil anular
> space around the via. More on faster switching lines if possible.
>
> One very important thing. Layout power and ground first. Before you
> route any signal line do power and ground first. They should be as
> direct from the source to the devices as possible. Avoid power loops.
> Branch power from the power buss to the components. Also keep all
> power runners 40 to 80 mils from the edge of the board. Ground plane
> can extend to about 10 mils to the edge. Signals should not be closer
> than 20 mils to the edge.
>
> some thoughts
>
> james
>
> On Fri, 11 Jul 2003 15:51:01 -0400, "..:: Gabster ::.."
> <gabsterblue@hotmail.com> wrote:
>
> >Hi,
> >
> >I'm made many 2-layer PCB's in the past years, but I'm about to start the
> >desgin of my first 4-layer PCB. The board is basically a FPGA (Xilinx
> >Spartan IIE XC2S300 in PQ208 package running at ±12MHz), 3 power supply
> >regulators, an oscillator block, a PROM and a logic IC.
> >
> >In addition to other literature, I read the following document:
> >http://www.xilinx.com/xapp/xapp623.pdf
> >but it is rather complicated and not straight foward for a rookie like me
in
> >FPGA design! So here's a few direct questions:
> >
> >1) 4-layer, why is it so important?
> >
> >2) In what order should I stack the layers (TOP/GND/POWER/BOTTOM or
> >TOP/POWER/GND/BOTTOM), why?
> >
> >3) Decoupling caps surroung the FPGA: I figured out I needed one 0.1µF
per
> >power pin (1.8V and 3.3V) + one 10µF per power supply (1.8V and 3.3V). Is
> >that accurate? Should I do more? What should I avoid?
> >
> >4) What is the concept surrounding islands on the power plane? What
should
> >that plane look like? What should I avoid? What the hell about it, this
> >plane is a mystery for me!!!
> >
> >In order to avoid asking 1000's other questions, I wonder if someone
could
> >also direct me toward a complete document talking about PCB design
> >guidelines for PQ package FPGA's. I found that for the BGA packages on
> >xilinx website, but it didn't help me much.
> >
> >Thanks a lot,
> >Gabriel
> >
>
Article: 58060> Also, I detest high value ceramics. From painful experiences with >strange leakage behavior (such as behaving like a low voltage zener) I am >now avoiding them like the plague. Seems strange. Was it just one cap, or one batch? Lots of people are using them because they have better ESR than tantalum for the same value. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 58061
"..:: Gabster ::.." <gabsterblue@hotmail.com> wrote in message news:<CyEPa.22790$Pe2.716265@wagner.videotron.net>... > Hi, > > In order to avoid asking 1000's other questions, I wonder if someone could > also direct me toward a complete document talking about PCB design > guidelines for PQ package FPGA's. I found that for the BGA packages on > xilinx website, but it didn't help me much. > > Thanks a lot, > Gabriel AN-75 from Altera: "High-speed Board Designs" just FYIArticle: 58062
"rickman" <spamgoeshere4@yahoo.com> wrote in message
news:3F0F337C.27A8ED76@yahoo.com...
<snip>
> -- VERSION 1
> -- These lines work correctly
> -- Data (15 downto 8) <= (others => '0') WHEN (ReadScratchReg =
'1')
> -- ELSE (others => 'Z');
> -- Data (7 downto 0) <= ScratchReg WHEN (ReadScratchReg = '1')
> -- ELSE (others => 'Z');
>
> -- VERSION 2
> -- This line fails by disabling the tristate buffers
> -- Data <= STD_LOGIC_VECTOR (15 downto 8)'(others => '0') &
> ScratchReg WHEN (ReadScratchReg = '1')
> -- ELSE (others => 'Z');
> -- The difference seems to be the use of the type cast.
> -- Using a type cast with the (others => aggregate seems to fail in
> other cases as well.
>
> -- VERSION 3
> -- This version produces open drain outputs
> Data <= DataOut WHEN (ReadScratchReg = '1')
> ELSE (others => 'Z');
> -- This seems to work ok
> -- DataOut <= "00000000" & ScratchReg;
> -- This produces no register and open drain drivers
> DataOut <= STD_LOGIC_VECTOR (15 downto 8)'(others => '0') &
> ScratchReg;
>
Hallo Rick,
just out of curiosity, have you tried using a named
subtype?
E.g.
architecture...
subtype vec8 is std_logic_vector(7 downto 0);
begin
...
-- VERSION 3
-- This version produces open drain outputs
Data <= DataOut WHEN (ReadScratchReg = '1')
ELSE (others => 'Z');
-- This seems to work ok
-- DataOut <= "00000000" & ScratchReg;
-- This produces no register and open drain drivers
DataOut <= Vec8'(others => '0') & ScratchReg;
I wondered if Quartus is getting confused by the (15 downto 8) slice?
The reason I'm asking is that by using STD_LOGIC_VECTOR(15 downto 8)
you create an anonymous subtype, and I know that anonymous subtypes
are not always allowed where named subtypes are allowed. For instance,
it's illegal to declare a function returning an anonymous subtype,
but it's OK with a named subtype.
regards
Alan
--
Alan Fitch
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Article: 58063thanx i was looking for such link ... cu yttrium "Philip Freidin" <philip@fliptronics.com> wrote in message news:hkd1hvcl64n2ue7v8cldne7rims4cnp10r@4ax.com... > On 12 Jul 2003 14:27:22 -0700, yijun_lily@yahoo.com (yxl) wrote: > >I found there are many FPGA devices, how to choose a good one for myself? > > Try this: > > http://www.fpga-faq.com/FAQ_Pages/0014_Xilinx_vs_Altera.htm > > > > > > =================== > Philip Freidin > philip@fliptronics.com > Host for WWW.FPGA-FAQ.COMArticle: 58064
Johnny <noone@nowhere.com> wrote in message beksl8$4ep$1@lacerta.tiscalinet.it... > Hi, > Anyone know if exist any implementation, for free, of > 802.11 protol on FPGA? I'm currently working on it: an implementation of the 802.11a/b/g MAC in a SpartanIIE FPGA... If you are interested, you can drop me an email (stevenson@infinito.it). TonyArticle: 58065
Hi I posted this on the comp.arch.vhdl group but didn't get the response I was looking for so please do not be put off if you have already seen this. The problem relates to libraries, I am also looking for any document which gives a high level description of the libraries and their content. The original message was as follows: ******************************************************************* Hi I am currently trying to replicate a core provided by a manufacturer which was developed on older Xilinx tools. In a dual port ram module generated using an early version of COREGen a library called 'xul' is referenced. I have conducted searches on the groups and have only found posts dating from around 1999/2000. Another library it has difficulties locating is the std.textio packages. Does this sound like an overall larger problem with accessing libraries or does it merely stem from the older tools. I am using ISE 5.1i here is the header for the file: -- output of CoreGen module generator -- $Header: dpbmemVHT.vhd,v 1.5 1998/06/29 23:29:18 hare Exp $ -- ************************************************************************ -- Copyright 1997 - Xilinx, Inc. -- All rights reserved. -- ************************************************************************ -- -- Description: -- Parameterized Dual Port RAM -- library std; use std.textio.all; -- library ieee; use ieee.std_logic_1164.all; -- library xul; use xul.ul_utils.all; -- ENTITY rm32x512 IS ... ... ... etc. Any suggestions would be greatly appreciated. Thanks in advance. -- Cheers! Mike -- Cheers! MikeArticle: 58066
"Brad Eckert" <brad@tinyboot.com> wrote in message news:4da09e32.0307111552.189961b8@posting.google.com... > I have a CPU core and testbench in synthesizable VHDL. I can > synthesize using Xilinx ISE 5.1 and it will tell me such-and-such > maximum frequency. However, the CPU won't exercise all datapath > combinations and it does different things in different cycles so I > don't really trust the fitter's max frequency estimate. > > My plan is to run the post-fit simulation model through my testbench > with different clock frequencies until the CPU fails. Then I'll add a > little overhead to meet minimum register setup times and that will be > my minimum clock period. > > Am I being too pessimistic about XST's timing estimating capability, > and if not, does this sound like a reasonable approach? > > -- > Brad Eckert In my opinion, the timing numbers from the post place and route timing analyzer are reliable. If you have extra jitter on your clock or other system interface issues that might compromise your timing a bit, it might be healthy to add 100ps-300ps of margin to your frequency requirement. There are problems with running the real part until failure and backing off for a "real" number. If the device you're testing with is on the faster end of the speed grade in a lab environment, the margin may not be enough to handle one of the slower parts from the speed grade binning at a higher temperature with a slighly lower supply voltage. The timing numbers from the Xilinx tool are worst-case for all three issues. If you run your experiment I'd expect the results would give you a higher frequency than that specified by the tools. Another issue is coverage. The Timing Analyzer will cover 100% of the paths that your timing constraints cover. The "live" test won't guarantee 100% of the paths - there are too many exception conditions for you to test without extensive test coverage analysis; even then, I wouldn't expect to find 100% test coverage. Also, not all timing violations would result in hard, observable errors. You can give yourself more confidence in the tools by running the live test for the verification of a much higher frequency before failure. Then you can rely more heavily on the Timing Analyzer results.Article: 58067
Ah! Now I've got a better clue as to what you're doing. To avoid the low frequency spurs - the ones that will produce the errors in your lowpass filter - you can go to a non-standard DDS configuration. The reason the low frequency spurs are there is a slight mismatch between your measurement frequency and your DDS frequency for a "nice fraction." If you consider the ideal DDS output frequency fraction of the DDS clock, I'd suggest using a "closest fraction" approach to drive a variable-modulus DDS accumulator. As an example, if you're generating a 100MHz signal from a 240MHz system clock, the ideal fraction is 100/240 or 1789569707/2^32. If, instead of having that huge number in the standard 32 bit accumulator which will give you spurs across the spectrum, you could just use an accumulator that's effectively a 12 modulus. Using a 4 bit accumulator (0-15, modulo 16) you could add an extra 4 whenever the phase accumulator rolls over. Normally you add 5 each cycle but once per cycle you add 9 instead. The result is a modulo 12 accumulator with a 5/12 fraction for your precise frequency match. I figured out a pleasant method of figuring the "next best fraction" for any number but you might find an algorithm through an internet search much faster that I could recreate what I did. If your fraction is simple like the 5/12 to extract 100MHz from 240MHz, your life is simple. One quick caveat.... FPGAs are great for digital work. The output from the FPGA could have jitter added by some of what's going on inside the device. Rather than driving the FPGA output directly to the phase comparator, reclock it externally through a single D Flip-Flop with power supply filtering appropriate to an analog supply. The DDS output gets de-jittered (the FPGA jitter, not the DDS jitter) before going to the phase comparator. Your results are clean. I hope you get your design to do your bidding! "Marc Battyani" <Marc.Battyani@fractalconcept.com> wrote in message news:besl8n$57s@library2.airnews.net... > > "Jim Granville" <jim.granville@designtools.co.nz> wrote > > Marc Battyani wrote: > > Sounds challenging : If I have this right > > You have 100MHz 'incomming' (hopefully very clean and phase stable :) > > You want to lock to 0.1%, (or 10ps), nominally 200MHz local Osc > > You can tolerate longer lock acquire times > > > > Analog Phase locked loops work because they integrate > > the phase-magnitude errors, > > - In a digital system, edge resolution of 10ps may be just possible, but > > I'm not sure you can get any error-proportional siganl. > > Go-right/Go-Left control is likely to be swamped by the phase-noise of > > the DDS signal..... > > I don't need the 10ps resolution as I'm only interested in the low frequency > phase measurement. > Even if I have a 2ns jitter, I don't care if the mean value of the jitter is > 0 after low pass filtering. > > Marc > >Article: 58068
adarsh arora escribió: > can u tell me from where i will get free downloadable softwares for > VHDL/verilog simulation and synthesis , SPICE ,IC Station...... with > free licences. > waiting for ur help http://ghdl.free.frArticle: 58069
Denis Gleeson wrote: > I realise that normally to obtain a given timing relationship one would > use synchronous logic. But in this case as I require signals with the > same frequency as the main clock I must use combinational logic. > > From the output of my logic simulator I am seeing some issues which > confuse me: > > (a) Different logic gates have different delays, A NOT has less delay than > an OR gate. May be this should have been obvious to me. Is it correct? > > (b) If I add a gate to create a delay, it seems to be getting optimised out. > Is there some way to stop a gate added for this purpose from being removed? Consider using an FPGA with an on-chip PLL. With a 4x internal clock you might be able to use the synchonous template for your design and eliminate those issues. -- Mike TreselerArticle: 58070
Hi Peter Thanks as always for your help. I am using a Spartan XL XCS05XL. I dont think features like that from the Virtex - II are available. Thanks for the point on the delay. As you can see Im new to some of the more basic points. Amazing how far you can get without understanding everything that goes on under the hood. In the simulation of my final design I can see that signals that travel through more gates in my schematic have a greater delay. Does this tie in with the look up table implementation. Thanks Denis Peter Alfke <peter@xilinx.com> wrote in message news:<3F11F909.A2E41D61@xilinx.com>... > Denis, I assume (correctly?) that you implement your logic in Xilinx or > Altera FPGAs. > In these parts, the logic is implemented in 4-input look-up tables, and > the distinction between AND, OR, and INV is meaningless. It all ends up > as the through-delay in a ROM with 4 address inputs and thus 16 stored bits. > You can, however, force the software to use one LUT for each gate, but > there still is no systematic difference between different gate types. > > I might suggest the clock phase adjust feature in Virtex-II, where you > can define and even step the clock output in increments of (one clock > period divided by 256) or 50 ps. That might give you a far more > predictable solution, and it would be a synchronous design, which we all prefer. > > Peter Alfke, Xilinx Applications > ============================ > Denis Gleeson wrote: > > > > Hello All > > > > I have a combinational logic circuit generating a number of waveforms > > from the main clock input. There are a number of external inputs to > > this circuit controlling the turning on and off of different outputs. > > > > My problem is that I need a certain timing relationship between four of > > the outputs. > > > > I realise that normally to obtain a given timing relationship one would > > use synchronous logic. But in this case as I require signals with the > > same frequency as the main clock I must use combinational logic. > > > > From the output of my logic simulator I am seeing some issues which > > confuse me: > > > > (a) Different logic gates have different delays, A NOT has less delay than > > an OR gate. May be this should have been obvious to me. Is it correct? > > > > (b) If I add a gate to create a delay, it seems to be getting optimised out. > > Is there some way to stop a gate added for this purpose from being removed? > > > > Thanks for all assistance in advance. > > > > DenisArticle: 58071
Hello to All, I was wondering if it is possible to program a PLD/CPLD via a PIC (without connecting external memory). The PIC I am using has a internal RAM of 768 bytes and 16k of flash. I have seen some app.notes from Altera/Xilinx/Lattice but I think that I need a more powerful micro for doing the CPLD reprograming with it. Is there any new small CPLD easy to reprogram?. I would appreciate any suggestion or link. Thanks a lot and best regards, JavierArticle: 58072
Hello All, I am developing a Xilinx SPARTAN 2E based System. I wonder how I can select an ideal Oscilaltor for this chip. I am looking for a 20 - 100Mhz clock. I could not find a document or write up regarding this clock selection or connection. I am facing a similar problem in selecting a powersupply also. But I got a white paper from Texas Instruments (http://focus.ti.com/lit/an/slua277/slua277.pdf) for that. I thinks I can rely on that. Can anyone sugggest/guide me in selecting a clock generator or point to a reference design. Thanks in advance ./greatinArticle: 58073
Hi Peter and All
This implementation and consequent resulting delays issue is begining to
drive me around the bend.
Below is a small diagram of my schematic.
To ensure tha OP2 (Output 2) changes state after OP1 (Output 1)
I set up the circuit as shown.
However I find in my simulation results that OP2 changes state
before OP1.
This appears to defy the laws of physics but Im sure there is a simple
explenation.
Signals control 1 and control 2 are low throughout.
Regards
Denis
OP2
OP1 _|_
| OR
| |__|
| ||____ control 1
| |
|_____________| Not |_____|
_|_
OR
|__|
||____
| |
| Not
control2 |
|
Main Clk
Peter Alfke <peter@xilinx.com> wrote in message news:<3F11F909.A2E41D61@xilinx.com>...
> Denis, I assume (correctly?) that you implement your logic in Xilinx or
> Altera FPGAs.
> In these parts, the logic is implemented in 4-input look-up tables, and
> the distinction between AND, OR, and INV is meaningless. It all ends up
> as the through-delay in a ROM with 4 address inputs and thus 16 stored bits.
> You can, however, force the software to use one LUT for each gate, but
> there still is no systematic difference between different gate types.
>
> I might suggest the clock phase adjust feature in Virtex-II, where you
> can define and even step the clock output in increments of (one clock
> period divided by 256) or 50 ps. That might give you a far more
> predictable solution, and it would be a synchronous design, which we all prefer.
>
> Peter Alfke, Xilinx Applications
> ============================
> Denis Gleeson wrote:
> >
> > Hello All
> >
> > I have a combinational logic circuit generating a number of waveforms
> > from the main clock input. There are a number of external inputs to
> > this circuit controlling the turning on and off of different outputs.
> >
> > My problem is that I need a certain timing relationship between four of
> > the outputs.
> >
> > I realise that normally to obtain a given timing relationship one would
> > use synchronous logic. But in this case as I require signals with the
> > same frequency as the main clock I must use combinational logic.
> >
> > From the output of my logic simulator I am seeing some issues which
> > confuse me:
> >
> > (a) Different logic gates have different delays, A NOT has less delay than
> > an OR gate. May be this should have been obvious to me. Is it correct?
> >
> > (b) If I add a gate to create a delay, it seems to be getting optimised out.
> > Is there some way to stop a gate added for this purpose from being removed?
> >
> > Thanks for all assistance in advance.
> >
> > Denis
Article: 58074Phil Hays <SpamPostmaster@attbi.com> wrote in message news:<3F0E42D2.A45D76D@attbi.com>... > Jun wrote: > > > I really don't see any advantage of using DQS to latch read data. > > A very simplified example. Suppose the Clock period was 10 ns. Clock to > DQS/data varied from 2 to 8 ns, and delay tracks, or in other words, if > the data delay is 7 ns, the DQS delay is also 7 ns. > > As the half period of the clock is 5 ns, there is NO time that the data > can be sampled by clock. > If the data delay is 7 ns, you may want to add another 2.5 ns delay on DQS to sample the data. But I don't see any difference between sampling data with a 9.5 ns delayed memory clock and with a 2.5 ns delayed DQS? > After the data is sampled by DQS, it is now no longer double data rate, > and can be sampled by plain old clock (with 2 ns setup and 2 ns hold). Even though not double rate, the app note can't garantee that the data will be safely transferred from DQS to "old plain clock". It still has to figure out the data delay time and shift read clock accordingly to meet the setup/hold requirement. The delay issue was outside FPGA and the app note only moves it inside. But it is still there. Only a FIFO may help to solve the problem I guess.
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