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Hi , Thanks for your reply. I even tried to initialize this inout port to all 0, but it still shows "UU" when I start simulation. During pre-synthesis simulation, the initial value of DATA is also "UU", but it changes to correct value after assignment take effect in the test bench. I try to figure out which one is driving this DATA port when its value is changed. But I don't know how to do this in Active HDL. The break point is located in the lsi_10k library and I can't trace it until the program control comes back to my program. Thanks. Liang Here is my code: --design.vhd library lsi_10k; use lsi_10k.all; ... entity DESIGN_UNIT is port( DATA : inout std_logic_vector (7 downto 0) := "ZZZZZZZZ"; ...); end DESIGN_UNIT; --testbench.vhd entity test_bench is end entity test_bench; architecture behav of test_bench is signal DATA: std_logic_vector(7 downto 0); signal Clock: bit :='0'; ... begin DUT: entity DESIGN_UNIT port map(DATA, ctl_data, ctl_op, Reset, Clock); simulation: process is begin clock <= '0'; wait for 20 ns; DATA <= "00000001"; Clock <= '1'; wait for 20 ns; -- DATA port will become "XX" at 20+1 ns wait; end process; end architecture behav; "Mike Treseler" <mike.treseler@flukenetworks.com> wrote in message news:3F0AF3F7.3010105@flukenetworks.com... > Mike wrote: > > > I declared a std_logic_vector(7 downto 0) (inout type) entity port > > in my VHDL program. In the testbench, I will try > > to assign some value to this port. But after synthesis > > using Synopsys Design Compiler, I found this port wouldn't > > accept the value from signal assignment in the test bench > > and the value of this port becomes "XX". > > > Post your code. Your output enable logic is likely the problem. > > -- Mike Treseler >Article: 57876
SP wrote: > I am looking for an FPGA kit that has a CPU like ARM that can run Linux. > Basically I want to play with idea of accelerating some functions in the > FPGA and expose them as device drivers to Linux. We are porting (almost done) uClinux to the Xilinx microblaze soft-core processor. Accelerating app- and kernel-specific tasks in hardware and putting device drivers around them is part of our research roadmap. http://www.itee.uq.edu.au/~jwilliams/mblaze-uclinux if you're interested. It's all open source, there's a mailing list and so on. Cheers, John > > Am still green in FPGAs. > > Thanks a lot!! > -Sumeet -- Dr John Williams, Research Fellow, Reconfigurable Computing, School of ITEE University of Queensland, Brisbane, Australia Ph : (07) 3365 8305Article: 57877
"DK" <dknews@ueidaq.com> wrote in news:3eff173f$1_3@newsfeed: > Hi, All > > for the new multichannel filter design I have a choice - > Altera Cyclone EP1C12 ($60) or Xilinx Spartan-3 XC3S1000(???) $60? What speed grade are you using? Also, is this low quantity pricing (~<100)? I could have sworn I was quoted a similar price for something as large as a EP1C20 in lower quantities (~<100) for a respin/cost reduction project I was going to do. Don't hold me to that...I'd have to check my notes at work! Thanks! Ed > > Xilinx part has a embedded MAC units. > > I've used in a past Altera chips and they have a good tech support and > free tools. > > Does any one has experience with Xilinx support? And is it possible to > obtain a free tools from Xilinx or they charge for the software? > > Any other hidden issues? > > Thanks, > > Dennis > > dknews@ueidaq.com > > >Article: 57878
Hi, Have a look at Ben Cohen's book. That's my choice. Please visit http://www.vhdlcohen.com HTH, Ajeetha http://www.noveldv.com vhdl_uk@yahoo.co.uk (MACEI'S) wrote in message news:<fdfcada5.0307081038.6f1c5d22@posting.google.com>... > Can anyone tell me good books or web sites related to following. > 1. MAKE file for VHDL ( XILINX) > 2. Implementation of Coding using FPGA > > Rgds > > MACIEArticle: 57879
BRANE-NEWS wrote: > > "rickman" <spamgoeshere4@yahoo.com> wrote in message > > <SNIP> > > I am not looking for champagne on a beer budget, but I would sure like > > to be able to pour them both into the same glass. > > Isn't that a bit of redneck perspective -champagne in Budweiser glass ? ;o) That's what we call a Fredneck around here... :) -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 57880
CB wrote: > > Geeze .... I'm glad altera doesn't waste valuable time on your problem > , they have real work to do. They have standardized on the ethernet > interface, if you have a desktop spend $15 and buy one, if you have a > laptop without one you may have to spend twice that on a USB version > or something. You must have lots of time and little work. Or maybe you don't understand the constraints. Some of the work I do is for the government and they have some very strict standards about control of the work environment. I don't want to have to switch between machines for different jobs. I just want to set up one machine and leave it alone. Virus protection is not an entirely trivial matter and is best handled by having no direct connections to the outside world. If there is an Ethernet card in the machine, I can't assure my customers that it will not be connected in a forgetful manner. Everybody does not work in the same environment that you might. On the other hand, they have responded and sent me a license file. Seems that this is not a big deal, you just have to go though the FAEs rather than through the support people. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 57881
In article <3F0BA49F.2FBCB891@yahoo.com>, rickman <spamgoeshere4@yahoo.com> wrote: >If there is an Ethernet card in the machine, I can't assure my customers >that it will not be connected in a forgetful manner. Why not take the ethernet card and attack the connector with wirecutters? You get a MAC address but the net don't work. :) -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 57882
Rick, In article <3F0CD81B.ED457D18@yahoo.com>, spamgoeshere4@yahoo.com says... > John wrote: > > > > Rick, > > > > > > WGET! > > > > Wget does it all and it's open source, doesn't include spyware, works > > really really well (hey, some of us HAVE been on dial-up too). > > Thanks. A couple of others have suggested WGET. I'll take a look. Is > this available for Windows without having to use Cygwin? If you would read my original posting, you would see I provided links for *stand-alone* WINDOWS binaries. Thanks, TR.Article: 57883
Dear Sir, Thanks, is it ok if i designed with DC coupling for 155.54 MHz serial LVDS link or do i need to use AC coupling. I have used Xilinx termination technique (resistor network) at both transmitter (SpartanIIE FPGA used) and receiver (spartanIIE FPGA used). Is the design will work for above configuration, Thanks in Advance, Regards, KarthikArticle: 57886
Hey, I'm trying to create a 20-bit pipelined adder using the lpm_add_sub megafunction, but when I try and compile my project in leonardo it changes the name in the .edf file from lpm_add_sub to lpm_add_sub_20_add_no_5 which Altera Max+PLUS does not recognize. In order for it to place and route correctly, I have to manually change the name back to lpm_add_sub. Does anybody know if there is a way to prevent this from happening. I've already tried setting the noopt and dont_touch attribute in the architecture block. Thanks in Advance, Jared HolzmanArticle: 57887
Hello Steve, Thanks for the information. ChristianArticle: 57888
"Peter Alfke" <peter@xilinx.com> wrote: > You might want to look at an article I wrote some time ago: > "Moving data across asynchronous clock boundaries". > You find it among the TechXclusives. > http://support.xilinx.com/xlnx/xweb/xil_tx_home.jsp Thanks, I will. -MartinArticle: 57889
On Wed, 9 Jul 2003 01:08:36 +0200, "Marc Battyani" <Marc.Battyani@fractalconcept.com> wrote: > >"Allan Herriman" <allan_herriman.hates.spam@agilent.com> >> On Tue, 8 Jul 2003 14:33:20 +0200, "Marc Battyani" >> <Marc.Battyani@fractalconcept.com> wrote: >> >I want to make a phase measurement at 100MHz with a NCO at 200+ MHz >> >This NCO will have a 32 bit phase accumulator and a 32 bits phase offset. >The >> >output will be only one bit. >> >I will use a phase comparator followed by an integrator (digital or >analogic >> >if needed). >> >At 100MHz the NCO output will be very very noisy but if I integrate it for >a >> >rather long time (10ms) will it have a 0 mean ? >> >Can I implement this in an FPGA or should I use a DDS chip (AD9854) ? >> >Where can I find some maths on this subject ? >> >> Do you need to know the spectrum of the noise, or just the peak to >> peak value? > >The spectrum I think. In fact I need to have a very precise phase lock >(0.1%). The frequency lock is already ok as I have the reference clock. Hmmm, 0.1% of what? "Phase lock" is usually specified as an angle (degrees, radians or unit intervals) or as phase noise (dBc/Hz). What are you actually trying to do? >> I sometimes find myself in the situation of having to work out the >> spectral characteristics of the phase noise (jitter) of the msb of a >> phase accumulator. E.g. if I am using a post-NCO PLL (as Peter A. >> suggested) then I only care about the phase noise components at offset >> frequencies less than the loop bandwidth of the PLL. > >I thought about filtering and integrating the phase error after the phase >comparator. I don't think I need a PLL as I'm not synthesising a frequency. You are synthesising a frequency with the NCO, even if that wasn't your intention. >> I don't know of a closed form expression for spectrum of the noise, >> but it's trivial to work out the spectrum with a spreadsheet (once you >> know how). This is much easier that trying to measure the spectrum in >> the lab. >> (Reply if you are interested in the method.) > >Sure, please explain how to do it, I'm really interested. Rough description here: http://groups.google.com/groups?threadm=379cf6a6.1375761%40newshost >> BTW, Peter's trick of reducing the jitter by a factor of 4 (I assume) >> relies on using a 4 phase clock. This is almost certainly worth the >> effort if you are trying to reduce the jitter. >> I have a worked example that uses a 2 phase clock (actually it uses >> both edges of a single clock) in my free fractional N divider >> generator, at this web site: >> http://fractional_divider.tripod.com/ >> (Note: some web proxies don't like domain names with underscores.) > >Thanks, I will look at it. > >Marc > > >Article: 57890
lecroy7200@chek.com (lecroy) wrote in message news:<9297c711.0307071137.4a64f1fd@posting.google.com>... > I think we covered the archive a while back. > > > It's hardly realistic to expect todays tools to support parts that have > > been obsolete for 10 years. > > Again, we are talking Spartan which has not been obsolete for ten > years. > > > Periodically some major component of the tools > > gets completely rewritten, when that happens it's hard enough for them to > > put in support for all of the current parts let alone add support for all > > of the old parts. > > Altera just keeps adding more support for their older devices to > Quartus. It's their newest tool. Maybe they have more time on their > hands. For the record, many years ago when Altera launched their very first stab at an FPGA a MAX5128 design suddenly stopped fitting. Almost all of Altera's revenue was from Max5x and Max7x at the time but their QA had let the fitter algorithms change for the FPGA while breaking it for Max5x. I am much more comfortable with Xilinx's attitude, but I expect that guys designing with rad hardened 4's (spartan) wish it were otherwise. RobArticle: 57891
1. Especially if the problem at hand is that easy to solve, altera should help them out. If a company reacts like that to simple problems I would get suspicious what happens if something serious goes wrong. (BTW.: I had very similar problems with Xilinx in germany.) 2. I always thought that ethernet based protection is particulary useless as one can - install the software inside a virtual machine with any virtual MAC address one likes - write a dummy driver that tells the system that a deactivated NIC with the MAC address of choice is present in the system. The only protection mechanism that is even more useless is volume-ID base protection. Kolja Sulimma charleybrant@hotmail.com (CB) wrote in message news:<3f0b2099.10419733@news.compuserve.com>... > Geeze .... I'm glad altera doesn't waste valuable time on your problem > , they have real work to do. They have standardized on the ethernet > interface, if you have a desktop spend $15 and buy one,Article: 57892
Hi, I've just had a look at marshall's (avnet) web site and it seems that the Xilinx Virtex II XC2VP100 is $11512. Did I miss something or lost some zeroes ? Is it that kind of price ? Thanks a lot for your comments StéphaneArticle: 57893
I do a rather heavy cascaded clock division/multiplication using DLL's in a VirtexE and have problems with routing resources from/to the dll's. I do not have enough resources to route all LOCKED signals through an inverter (and delay for 2x feedback's) and therefore do a delayed reset from one to the next. My question is:How much delay do I need to be sure that the output of one DLL is locked before I reset the next one? Does anyone have experience with this?Article: 57894
On Mon, 7 Jul 2003 18:16:33 -0500, John <ngp1011@yahoo.com> wrote: >Hey Rickman, > >In article <3F0AE7CC.68F9D9D0@yahoo.com>, spamgoeshere4@yahoo.com >says... >> I need to vent a little steam. So at risk of making myself look stupid >> (or more stupid) I will do it here. >> >> I have been trying to get the Quartus 3.0 software and a license since >> last Thursday. I tried three times over the weekend to download it, but >> the slow modem link I have to use would not complete the entire transfer >> without a problem. I think I have that licked as my brother tells me he >> has downloaded it for me. > >You might want to look into a *great* utility called "wget". > >It's probably comes standard on every modern FreeBSD/Linux >implementation, but not many people in the Windows world know about >it... > >See this for a command-line vanilla Windows version: > >http://space.tin.it/computer/hherold/ > >and see this for a Visual Basic GUI wrap-around: > >http://www.jensroesner.de/wgetgui/ > >If you use the plain-vanilla command-line version, just launch like >this: > >wget -c <url> > >-c tells it to continue if a download is aborted...this way if your >modem drops, when you re-connect, just re-issue wget -c <url> and it'll >continue where the file was chopped off. BTW, wget is also available for windows as part of the cygwin unix-like emulation. Regards, Allan.Article: 57895
Hi, I am using singal of 32 bit's lenght in my .vhd file and I am compiling using Makefile. I have also defined a UCF file. My UCF file is generating error when run ngd build using Makefile. The error is given below : ERROR: Reading component libraries for design expansion... Annotating constraints to design from file "VIR3.ucf" ... ERROR:NgdBuild:755 - Line 49 in 'VIR3.ucf': Could not find net(s) 'Input<7>' in the design. To suppress this error use the -aul switch, specify the correct net name or remove the constraint. ERROR:NgdBuild:755 - Line 50 in 'VIR3.ucf': Could not find net(s) 'Input<8>' in the design. To suppress this error use the -aul switch, specify the correct net name or remove the constraint. ERROR:NgdBuild:755 - Line 51 in 'VIR3.ucf': Could not find net(s) 'Input<9>' in the design. To suppress this error use the -aul switch, specify the correct net name or remove the constraint. ERROR:NgdBuild:755 - Line 52 in 'VIR3.ucf': Could not find net(s) 'Input<10>' in the design. To suppress this error use the -aul switch, specify the correct net name or remove the constraint. ERROR:NgdBuild:755 - Line 53 in 'VIR3.ucf': Could not find net(s) 'Input<11>' in the design. To suppress this error use the -aul switch, specify the correct net name or remove the constraint. ERROR:NgdBuild:755 - Line 54 in 'VIR3.ucf': Could not find net(s) 'Input<12>' in the design. To suppress this error use the -aul switch, specify the correct net name or remove the constraint. ERROR:NgdBuild:755 - Line 55 in 'VIR3.ucf': Could not find net(s) 'Input<13>' in the design. To suppress this error use the -aul switch, specify the correct net name or remove the constraint. ERROR:NgdBuild:755 - Line 56 in 'VIR3.ucf': Could not find net(s) 'Input<14>' in the design. To suppress this error use the -aul switch, specify the correct net name or remove the constraint. ERROR:NgdBuild:755 - Line 57 in 'VIR3.ucf': Could not find net(s) 'Input<15>' in the design. To suppress this error use the -aul switch, specify the correct net name or remove the constraint. ERROR:NgdBuild:755 - Line 58 in 'VIR3.ucf': Could not find net(s) 'Input<16>' in the design. To suppress this error use the -aul switch, specify the correct net name or remove the constraint. ERROR:NgdBuild:755 - Line 59 in 'VIR3.ucf': Could not find net(s) 'Input<17>' in the design. To suppress this error use the -aul switch, specify the correct net name or remove the constraint. ERROR:NgdBuild:755 - Line 60 in 'VIR3.ucf': Could not find net(s) 'Input<18>' in the design. To suppress this error use the -aul switch, specify the correct net name or remove the constraint. ERROR:NgdBuild:755 - Line 61 in 'VIR3.ucf': Could not find net(s) 'Input<19>' in the design. To suppress this error use the -aul switch, specify the correct net name or remove the constraint. ERROR:NgdBuild:755 - Line 62 in 'VIR3.ucf': Could not find net(s) 'Input<20>' in the design. To suppress this error use the -aul switch, specify the correct net name or remove the constraint. ERROR:NgdBuild:755 - Line 63 in 'VIR3.ucf': Could not find net(s) 'Input<21>' in the design. To suppress this error use the -aul switch, specify the correct net name or remove the constraint. ERROR:NgdBuild:755 - Line 64 in 'VIR3.ucf': Could not find net(s) 'Input<22>' in the design. To suppress this error use the -aul switch, specify the correct net name or remove the constraint. ERROR:NgdBuild:755 - Line 65 in 'VIR3.ucf': Could not find net(s) 'Input<23>' in the design. To suppress this error use the -aul switch, specify the correct net name or remove the constraint. ERROR:NgdBuild:755 - Line 66 in 'VIR3.ucf': Could not find net(s) 'Input<24>' in the design. To suppress this error use the -aul switch, specify the correct net name or remove the constraint. ERROR:NgdBuild:755 - Line 67 in 'VIR3.ucf': Could not find net(s) 'Input<25>' in the design. To suppress this error use the -aul switch, specify the correct net name or remove the constraint. ERROR:NgdBuild:755 - Line 68 in 'VIR3.ucf': Could not find net(s) 'Input<26>' in the design. To suppress this error use the -aul switch, specify the correct net name or remove the constraint. ERROR:NgdBuild:755 - Line 69 in 'VIR3.ucf': Could not find net(s) 'Input<27>' in the design. To suppress this error use the -aul switch, specify the correct net name or remove the constraint. ERROR:NgdBuild:755 - Line 70 in 'VIR3.ucf': Could not find net(s) 'Input<28>' in the design. To suppress this error use the -aul switch, specify the correct net name or remove the constraint. ERROR:NgdBuild:755 - Line 71 in 'VIR3.ucf': Could not find net(s) 'Input<29>' in the design. To suppress this error use the -aul switch, specify the correct net name or remove the constraint. ERROR:NgdBuild:755 - Line 72 in 'VIR3.ucf': Could not find net(s) 'Input<30>' in the design. To suppress this error use the -aul switch, specify the correct net name or remove the constraint. ERROR:NgdBuild:755 - Line 73 in 'VIR3.ucf': Could not find net(s) 'Input<31>' in the design. To suppress this error use the -aul switch, specify the correct net name or remove the constraint. ERROR:Parsers:11 - Encountered unrecognized constraint while parsing. ERROR:NgdBuild:19 - Errors found while parsing constraint file "VIR3.ucf". -------------------------------------------------------------------------------- I used -aul switch in my ngdbuild statement but this action simply delete this message. And in the actual *.par file I could not see signal's greater than 6th bits ( i.e there is no pin assignent of Input greater than Input<6>. Then, I comment all the signal Input<7> to Input <31> in my UCF file and did NDG bulild. After doing this I could see pin assignment for Input <0> to Input <6> as before. After doing this I used ngd file and UCF file ( but this time all signal's Input <0> to Input <31> were uncommented) . I used these both file to see whats happening in Contraint Editor comes with Xilinx ISE 5.1 Keep one thing in mind that ngd file is produce using constraint higher than 6 being commented and UCF file is used having all the signal 0 to 31 uncommented . I found that 1. In UCF Contraint (Read-Write) tab NET "Input<0>" LOC = "P94" ; NET "Input<1>" LOC = "P96" ; NET "Input<2>" LOC = "P99" ; NET "Input<3>" LOC = "P101" ; NET "Input<4>" LOC = "P103" ; NET "Input<5>" LOC = "P107" ; NET "Input<6>" LOC = "P109" ; 2. In UCF Constraint ( Read Only) tab NET "Input<7>" LOC = "P111" ; NET "Input<8>" LOC = "P125" ; NET "Input<9>" LOC = "P126" ; NET "Input<10>" LOC = "P127" ; NET "Input<11>" LOC = "P128" ; NET "Input<12>" LOC = "P130" ; NET "Input<13>" LOC = "P131" ; NET "Input<14>" LOC = "P132" ; NET "Input<15>" LOC = "P133" ; NET "Input<16>" LOC = "P139" ; NET "Input<17>" LOC = "P140" ; NET "Input<18>" LOC = "P141" ; NET "Input<19>" LOC = "P142" ; NET "Input<20>" LOC = "P144" ; NET "Input<21>" LOC = "P146" ; NET "Input<22>" LOC = "P147" ; NET "Input<23>" LOC = "P149" ; NET "Input<24>" LOC = "P152" ; NET "Input<25>" LOC = "P153" ; NET "Input<26>" LOC = "P154" ; NET "Input<27>" LOC = "P155" ; NET "Input<28>" LOC = "P157" ; NET "Input<29>" LOC = "P159" ; NET "Input<30>" LOC = "P160" ; NET "Input<31>" LOC = "P161" ; Now, could any body tell what to do now in order to assigned pin's to all the rest of the bit's Any help would be appreciated Rgds IsaacArticle: 57896
On 9 Jul 2003 06:08:30 -0700, fpga_uk@yahoo.co.uk (Isaac) wrote >Hi, > >I am using singal of 32 bit's lenght in my .vhd file and I am >compiling using Makefile. I have also defined a UCF file. My UCF file >is generating error when run ngd build using Makefile. The error is >given below : Are you sure your signal is 32 bits? You might have declared it as 32 bits, but the synthesiser may remove bits (such as 31 downto 7) if they are not used. This could cause the error messages you saw. For an input port, "not used" means that (after logic reduction) it doesn't affect any outputs. Regards, Allan.Article: 57897
"Phil Hays" <SpamPostmaster@attbi.com> wrote in message news:3F0B9CF6.B2694711@attbi.com... > Jun wrote: > > > > Phil Hays <SpamPostmaster@attbi.com> wrote in message news:<3F0251F7.C10AA8D5@attbi.com>... > > > Jon Terje Haugland wrote: > > > > > > > I am designing a DDR SDRAM controller in a Virtex-II 1500 -5 FFA896. > > > > It should operate at 166 MHz towrads the DDR SDRAM. I have used > > > > XAPP266 as reference regarding the timing analysis towards the DDR > > > > SDRAM. In XAPP266 one of the "results" is: > > > > 0.503ns<tDQS-tDQ<1.025 (midpoint at 0.76ns). This delay is introduced > > > > by routing? If the PCB delay is 180ps pr. inch. it would require a DQS > > > > net that is 4.2 inches? Is this correct??? > > > > > > Yes, this is correct. This delay is the difference between the DQ line > > > length on the PCB and the DQS line length on the PCB. If the DQ lines > > > are 1.5 inches, the DQS lines need to be 1.5 inches + 4.2 inches = 5.7 > > > inches, assuming 180ps/inch. The delay of the PCB varies with stackup, > > > use care. Delay of vias can be significant, make sure the number and > > > placement of vias match or that this delay is included in the > > > calculation. > > > > Why don't use a phase shifted DDR clock instead of DQS to latch the > > reading data? The delay is more manageable I guess. > > Sure, if the design is running at 100 MHz clock rate (200 MHz data rate) > or a little faster. Using the DQS signals from the DDR DIMM as source > synchronous clocks allows running just about twice as fast: 200 MHz > clock rate (400 MHz data rate), or again a little faster. For a > reference design, see: > > http://www.xilinx.com/xapp/xapp253.pdf > > > -- > Phil Hays The timing relationship between DQ and DQS is required for the writes to the DDR SDRAM; the SDRAM latches the incoming data on DQ on both edges of the DQS. Presumably the extra delay on the DQS is to ensure that the setup and hold time of DQ around the DQS is met. The read timing IS latched using a phase shifted clock; it is not possible (at high speed) to latched the read data (data coming back from the SDRAM) using the DQS. The DQS is provided by the RAM as a "clock" for the return data, but unfortunately, this is useless for an FPGA. The DQS provided by the SDRAM is not a periodic clock; aside from the fact that it is bidirectional, it only runs during the data phases of the read data. Since it is not a periodic clock, it cannot be fed into a DCM; while the DCM allows for clock stopping and starting, there is a 3 to 4 clock pulse delay in the DCM, so you would miss the incoming data. Furthermore, it would be difficult (impossible?) to prevent the outgoing DQS from unlocking the DCM. Using the DQS as a clock without deskewing it using a DCM results in HUGE setup/hold requirements for the IOB flops (for some parts, over a 2ns required valid window); the setup/hold window of the flops is far larger than the data valid window provided by the RAM at any reasonable clock rate. Therefore, the soultion in the app note (using a phase shifted internal clock to capture the read data) is the only way to go. Similarly, since the DQ/DQS timing relationship is required to do writes to the DDR-SDRAM, it is necessary to generate a delay, either using a DCM or board delays (as is done in the app note). AvrumArticle: 57898
Hi, There doesn't seem to be an architecture associated with your DESIGN_UNIT entity. "Liang Yang" <yangliang_mr@hotmail.com> wrote in message news:befnvc$4bc$1@news.asu.edu... > Hi , > > Thanks for your reply. > > I even tried to initialize this inout port to all 0, but it still shows "UU" > when I start simulation. During pre-synthesis simulation, > the initial value of DATA is also "UU", but it changes to correct value > after assignment take effect in the test bench. > > I try to figure out which one is driving this DATA port when its value > is changed. But I don't know how to do this in Active HDL. The break point > is located in the lsi_10k library and I can't trace it until the program > control > comes back to my program. > > Thanks. > > Liang > > > Here is my code: > --design.vhd > library lsi_10k; > use lsi_10k.all; > ... > entity DESIGN_UNIT is > > port( DATA : inout std_logic_vector (7 downto 0) := "ZZZZZZZZ"; ...); > > end DESIGN_UNIT; > > --testbench.vhd > entity test_bench is > end entity test_bench; > > architecture behav of test_bench is > signal DATA: std_logic_vector(7 downto 0); > signal Clock: bit :='0'; > ... > begin > DUT: entity DESIGN_UNIT > port map(DATA, ctl_data, ctl_op, Reset, Clock); > > simulation: process is > begin > clock <= '0'; > wait for 20 ns; > > DATA <= "00000001"; > Clock <= '1'; > wait for 20 ns; -- DATA port will become "XX" at 20+1 ns > > wait; > end process; > end architecture behav; > > "Mike Treseler" <mike.treseler@flukenetworks.com> wrote in message > news:3F0AF3F7.3010105@flukenetworks.com... > > Mike wrote: > > > > > I declared a std_logic_vector(7 downto 0) (inout type) entity port > > > in my VHDL program. In the testbench, I will try > > > to assign some value to this port. But after synthesis > > > using Synopsys Design Compiler, I found this port wouldn't > > > accept the value from signal assignment in the test bench > > > and the value of this port becomes "XX". > > > > > > Post your code. Your output enable logic is likely the problem. > > > > -- Mike Treseler > > > >Article: 57899
"Nicholas C. Weaver" wrote: > > In article <3F0BA49F.2FBCB891@yahoo.com>, > rickman <spamgoeshere4@yahoo.com> wrote: > >If there is an Ethernet card in the machine, I can't assure my customers > >that it will not be connected in a forgetful manner. > > Why not take the ethernet card and attack the connector with > wirecutters? You get a MAC address but the net don't work. :) At this point there is no reason. Altera has provided a license file keyed to the HDD SN. I was also told that this will be added to the web site in the near future just as they have for MaxPlusII. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX
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